Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4429429 1 T1 2575 T2 8523 T3 25074
auto[1] 2653512 1 T1 5778 T2 4251 T3 21316


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2670438 1 T1 3285 T2 5733 T3 19644
auto[1] 4412503 1 T1 5068 T2 7041 T3 26746


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3244843 1 T1 4200 T2 5353 T4 5
auto[1] 3838098 1 T1 4153 T2 7421 T3 46390


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4421245 1 T1 3608 T2 7530 T3 27869
auto[1] 2661696 1 T1 4745 T2 5244 T3 18521


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6360342 1 T1 7517 T2 11463 T3 41432
fifo_depth[1] 122808 1 T1 188 T2 226 T3 789
fifo_depth[2] 97682 1 T1 195 T2 224 T3 800
fifo_depth[3] 76953 1 T1 166 T2 218 T3 738
fifo_depth[4] 69874 1 T1 102 T2 197 T3 743
fifo_depth[5] 53124 1 T1 73 T2 176 T3 657
fifo_depth[6] 43314 1 T1 50 T2 114 T3 516
fifo_depth[7] 27285 1 T1 30 T2 88 T3 369


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 722599 1 T1 836 T2 1311 T3 4958
auto[1] 6360342 1 T1 7517 T2 11463 T3 41432


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7069305 1 T1 8353 T2 12774 T3 46390
auto[1] 13636 1 T24 20 T25 172 T146 27


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 24779 1 T8 1 T12 9 T22 60
auto[0] auto[0] auto[0] auto[0] auto[1] 29393 1 T22 65 T23 1 T51 21
auto[0] auto[0] auto[0] auto[1] auto[0] 33761 1 T2 137 T12 22 T16 5
auto[0] auto[0] auto[0] auto[1] auto[1] 21087 1 T4 1 T12 25 T7 5
auto[0] auto[0] auto[1] auto[0] auto[0] 206635 1 T2 390 T12 11 T22 126
auto[0] auto[0] auto[1] auto[0] auto[1] 30236 1 T1 28 T2 49 T6 1
auto[0] auto[0] auto[1] auto[1] auto[0] 26123 1 T1 121 T2 166 T4 1
auto[0] auto[0] auto[1] auto[1] auto[1] 24947 1 T1 117 T2 36 T4 1
auto[0] auto[1] auto[0] auto[0] auto[0] 40336 1 T3 726 T8 1 T6 1
auto[0] auto[1] auto[0] auto[0] auto[1] 40826 1 T1 169 T8 2 T12 14
auto[0] auto[1] auto[0] auto[1] auto[0] 35210 1 T2 138 T3 1165 T5 76
auto[0] auto[1] auto[0] auto[1] auto[1] 47400 1 T1 295 T6 1 T7 5
auto[0] auto[1] auto[1] auto[0] auto[0] 51176 1 T3 1926 T7 12 T23 1
auto[0] auto[1] auto[1] auto[0] auto[1] 33246 1 T2 262 T3 558 T5 26
auto[0] auto[1] auto[1] auto[1] auto[0] 42755 1 T1 106 T2 133 T3 411
auto[0] auto[1] auto[1] auto[1] auto[1] 34689 1 T3 172 T8 2 T12 17
auto[1] auto[0] auto[0] auto[0] auto[0] 155998 1 T1 397 T2 340 T8 98
auto[1] auto[0] auto[0] auto[0] auto[1] 175733 1 T1 1 T2 330 T12 2
auto[1] auto[0] auto[0] auto[1] auto[0] 190347 1 T1 1 T2 487 T4 1
auto[1] auto[0] auto[0] auto[1] auto[1] 160511 1 T1 385 T2 814 T4 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1660018 1 T1 652 T2 834 T8 31
auto[1] auto[0] auto[1] auto[0] auto[1] 178917 1 T1 290 T2 1065 T8 12
auto[1] auto[0] auto[1] auto[1] auto[0] 155760 1 T1 552 T2 576 T8 1
auto[1] auto[0] auto[1] auto[1] auto[1] 170598 1 T1 1656 T2 129 T8 59
auto[1] auto[1] auto[0] auto[0] auto[0] 438931 1 T1 174 T2 2493 T3 5865
auto[1] auto[1] auto[0] auto[0] auto[1] 426952 1 T1 565 T3 3404 T8 15
auto[1] auto[1] auto[0] auto[1] auto[0] 417538 1 T1 360 T2 557 T3 4085
auto[1] auto[1] auto[0] auto[1] auto[1] 431636 1 T1 938 T2 437 T3 4399
auto[1] auto[1] auto[1] auto[0] auto[0] 503663 1 T2 638 T3 7440 T4 1
auto[1] auto[1] auto[1] auto[0] auto[1] 432590 1 T1 299 T2 2122 T3 5155
auto[1] auto[1] auto[1] auto[1] auto[0] 438215 1 T1 1245 T2 641 T3 6251
auto[1] auto[1] auto[1] auto[1] auto[1] 422935 1 T1 2 T3 4833 T8 48


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 179518 1 T1 397 T2 340 T8 99
auto[0] auto[0] auto[0] auto[0] auto[1] 204561 1 T1 1 T2 330 T12 2
auto[0] auto[0] auto[0] auto[1] auto[0] 223359 1 T1 1 T2 624 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] 181341 1 T1 385 T2 814 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] 1865781 1 T1 652 T2 1224 T8 31
auto[0] auto[0] auto[1] auto[0] auto[1] 208832 1 T1 318 T2 1114 T8 12
auto[0] auto[0] auto[1] auto[1] auto[0] 180713 1 T1 673 T2 742 T4 1
auto[0] auto[0] auto[1] auto[1] auto[1] 195321 1 T1 1773 T2 165 T4 1
auto[0] auto[1] auto[0] auto[0] auto[0] 478849 1 T1 174 T2 2493 T3 6591
auto[0] auto[1] auto[0] auto[0] auto[1] 466833 1 T1 734 T3 3404 T8 17
auto[0] auto[1] auto[0] auto[1] auto[0] 452671 1 T1 360 T2 695 T3 5250
auto[0] auto[1] auto[0] auto[1] auto[1] 478528 1 T1 1233 T2 437 T3 4399
auto[0] auto[1] auto[1] auto[0] auto[0] 552055 1 T2 638 T3 9366 T4 1
auto[0] auto[1] auto[1] auto[0] auto[1] 465240 1 T1 299 T2 2384 T3 5713
auto[0] auto[1] auto[1] auto[1] auto[0] 480505 1 T1 1351 T2 774 T3 6662
auto[0] auto[1] auto[1] auto[1] auto[1] 455198 1 T1 2 T3 5005 T8 50
auto[1] auto[0] auto[0] auto[0] auto[0] 1259 1 T49 5 T145 2 T158 5
auto[1] auto[0] auto[0] auto[0] auto[1] 565 1 T24 18 T25 36 T49 86
auto[1] auto[0] auto[0] auto[1] auto[0] 749 1 T49 34 T145 9 T159 8
auto[1] auto[0] auto[0] auto[1] auto[1] 257 1 T25 8 T19 34 T49 42
auto[1] auto[0] auto[1] auto[0] auto[0] 872 1 T19 32 T50 20 T159 8
auto[1] auto[0] auto[1] auto[0] auto[1] 321 1 T19 3 T50 2 T160 6
auto[1] auto[0] auto[1] auto[1] auto[0] 1170 1 T19 6 T145 12 T50 22
auto[1] auto[0] auto[1] auto[1] auto[1] 224 1 T49 1 T50 24 T161 42
auto[1] auto[1] auto[0] auto[0] auto[0] 418 1 T19 3 T49 8 T161 1
auto[1] auto[1] auto[0] auto[0] auto[1] 945 1 T25 128 T145 10 T162 8
auto[1] auto[1] auto[0] auto[1] auto[0] 77 1 T162 3 T163 1 T164 1
auto[1] auto[1] auto[0] auto[1] auto[1] 508 1 T146 27 T19 6 T145 7
auto[1] auto[1] auto[1] auto[0] auto[0] 2784 1 T145 45 T50 8 T162 6
auto[1] auto[1] auto[1] auto[0] auto[1] 596 1 T24 2 T50 69 T159 104
auto[1] auto[1] auto[1] auto[1] auto[0] 465 1 T145 72 T161 20 T160 14
auto[1] auto[1] auto[1] auto[1] auto[1] 2426 1 T19 59 T49 6 T158 8


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 155998 1 T1 397 T2 340 T8 98
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 175733 1 T1 1 T2 330 T12 2
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 190347 1 T1 1 T2 487 T4 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 160511 1 T1 385 T2 814 T4 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1660018 1 T1 652 T2 834 T8 31
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 178917 1 T1 290 T2 1065 T8 12
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 155760 1 T1 552 T2 576 T8 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 170598 1 T1 1656 T2 129 T8 59
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 438931 1 T1 174 T2 2493 T3 5865
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 426952 1 T1 565 T3 3404 T8 15
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 417538 1 T1 360 T2 557 T3 4085
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 431636 1 T1 938 T2 437 T3 4399
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 503663 1 T2 638 T3 7440 T4 1
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 432590 1 T1 299 T2 2122 T3 5155
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 438215 1 T1 1245 T2 641 T3 6251
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 422935 1 T1 2 T3 4833 T8 48
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3207 1 T8 1 T12 4 T22 31
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3286 1 T22 35 T51 18 T52 44
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3642 1 T2 30 T12 14 T22 16
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3012 1 T4 1 T12 15 T16 1
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 50310 1 T2 75 T12 6 T22 85
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3631 1 T1 9 T2 6 T16 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3045 1 T1 18 T2 21 T12 21
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3931 1 T1 58 T2 3 T22 6
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6016 1 T3 119 T8 1 T12 5
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5779 1 T1 31 T8 2 T12 6
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6017 1 T2 33 T3 201 T5 13
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6163 1 T1 43 T7 1 T51 22
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8412 1 T3 288 T7 2 T51 9
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5349 1 T2 30 T3 85 T5 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5482 1 T1 29 T2 28 T3 68
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5526 1 T3 28 T8 2 T12 11
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2518 1 T12 3 T22 19 T51 4
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2617 1 T22 20 T51 3 T52 22
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2553 1 T2 23 T12 7 T16 1
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2559 1 T12 6 T5 3 T16 1
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 37948 1 T2 74 T12 5 T22 33
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3018 1 T1 13 T2 5 T22 11
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2264 1 T1 26 T2 21 T12 10
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2966 1 T1 41 T2 5 T22 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5078 1 T3 114 T12 2 T52 8
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4940 1 T1 33 T12 6 T5 19
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5421 1 T2 28 T3 208 T5 12
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5299 1 T1 48 T7 1 T5 15
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6880 1 T3 300 T7 1 T51 1
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4450 1 T2 40 T3 88 T5 6
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4646 1 T1 34 T2 28 T3 66
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4525 1 T3 24 T12 3 T22 4
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1962 1 T12 1 T22 9 T51 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1737 1 T22 9 T52 5 T20 51
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1838 1 T2 29 T12 1 T16 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1774 1 T12 4 T16 1 T22 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 29225 1 T2 62 T22 7 T52 9
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2065 1 T1 5 T2 13 T16 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1658 1 T1 24 T2 23 T12 3
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2230 1 T1 17 T2 4 T22 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4208 1 T3 93 T52 1 T53 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4291 1 T1 43 T12 2 T5 18
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4165 1 T2 26 T3 189 T5 15
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4338 1 T1 47 T5 2 T52 4
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5898 1 T3 294 T7 4 T51 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3756 1 T2 41 T3 74 T22 2
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4153 1 T1 30 T2 20 T3 60
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3655 1 T3 28 T12 2 T22 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1929 1 T12 1 T22 1 T52 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1782 1 T22 1 T20 39 T59 4
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1984 1 T2 22 T16 1 T52 19
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2019 1 T7 2 T5 2 T16 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 22162 1 T2 57 T22 1 T51 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2370 1 T1 1 T2 9 T21 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1715 1 T1 13 T2 24 T12 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2265 1 T1 1 T2 11 T52 13
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4256 1 T3 104 T53 2 T20 29
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4047 1 T1 33 T5 16 T16 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4226 1 T2 18 T3 187 T5 10
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4264 1 T1 42 T7 1 T5 11
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5532 1 T3 290 T7 1 T52 48
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3672 1 T2 32 T3 70 T5 6
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4188 1 T1 12 T2 24 T3 68
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3463 1 T3 24 T12 1 T22 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1413 1 T52 2 T20 6 T27 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1248 1 T24 2 T20 30 T104 8
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1347 1 T2 19 T16 1 T52 13
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1202 1 T7 1 T5 1 T52 9
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 15112 1 T2 59 T52 3 T27 5
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1720 1 T2 5 T6 1 T16 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1232 1 T1 18 T2 20 T21 10
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1704 1 T2 5 T52 1 T20 32
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3505 1 T3 102 T53 1 T20 29
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3518 1 T1 16 T5 9 T23 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3298 1 T2 13 T3 142 T5 9
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3701 1 T1 38 T52 5 T20 10
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4621 1 T3 265 T7 2 T52 1
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3009 1 T2 35 T3 77 T52 3
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3612 1 T1 1 T2 20 T3 57
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2882 1 T3 14 T157 2 T27 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1146 1 T52 2 T20 5 T27 2
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1180 1 T20 17 T104 8 T89 10
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1223 1 T2 12 T16 1 T21 7
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1340 1 T7 1 T5 2 T16 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 11490 1 T2 35 T52 3 T27 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1692 1 T2 6 T21 1 T20 26
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1103 1 T1 11 T2 18 T20 13
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1290 1 T2 1 T20 27 T27 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2869 1 T3 83 T6 1 T53 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2807 1 T1 7 T5 13 T16 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2894 1 T2 5 T3 115 T5 8
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2928 1 T1 32 T7 1 T5 8
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3661 1 T3 200 T7 2 T52 11
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2439 1 T2 28 T3 65 T5 7
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3000 1 T2 9 T3 38 T5 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2252 1 T3 15 T157 2 T99 3
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 741 1 T52 1 T20 2 T27 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 715 1 T20 6 T104 5 T89 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 723 1 T2 2 T21 8 T104 7
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 549 1 T23 1 T104 8 T89 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 6624 1 T2 17 T52 1 T27 4
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1141 1 T2 4 T16 1 T21 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 665 1 T1 5 T2 27 T21 10
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 828 1 T2 2 T4 1 T20 17
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1972 1 T3 55 T53 1 T20 8
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1930 1 T1 5 T5 7 T16 1
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1872 1 T2 11 T3 74 T5 4
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2003 1 T1 20 T7 1 T52 4
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2413 1 T3 151 T23 1 T52 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1500 1 T2 22 T3 47 T5 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2102 1 T2 3 T3 22 T20 22
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1507 1 T3 20 T99 3 T104 19

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