Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17352656	1			T1	34201		T2	25739		T3	93160
all_pins[1]	17352656	1			T1	34201		T2	25739		T3	93160
all_pins[2]	17352656	1			T1	34201		T2	25739		T3	93160

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44361081	1			T1	81791		T2	64863		T3	238607
values[0x1]	7696887	1			T1	20812		T2	12354		T3	40873
transitions[0x0=>0x1]	7696748	1			T1	20812		T2	12354		T3	40873
transitions[0x1=>0x0]	7696760	1			T1	20812		T2	12354		T3	40873

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17332399	1			T1	34186		T2	25719		T3	93139
all_pins[0]	values[0x1]	20257	1			T1	15		T2	20		T3	21
all_pins[0]	transitions[0x0=>0x1]	20190	1			T1	15		T2	20		T3	21
all_pins[0]	transitions[0x1=>0x0]	7676257	1			T1	20797		T2	12334		T3	40852
all_pins[1]	values[0x0]	17352338	1			T1	34201		T2	25739		T3	93160
all_pins[1]	values[0x1]	318	1			T52	9		T24	2		T27	6
all_pins[1]	transitions[0x0=>0x1]	289	1			T52	8		T24	2		T27	5
all_pins[1]	transitions[0x1=>0x0]	20228	1			T1	15		T2	20		T3	21
all_pins[2]	values[0x0]	9676344	1			T1	13404		T2	13405		T3	52308
all_pins[2]	values[0x1]	7676312	1			T1	20797		T2	12334		T3	40852
all_pins[2]	transitions[0x0=>0x1]	7676269	1			T1	20797		T2	12334		T3	40852
all_pins[2]	transitions[0x1=>0x0]	275	1			T52	6		T24	2		T27	6