Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 817 1 T52 21 T27 20 T59 4
all_values[1] 817 1 T52 21 T27 20 T59 4
all_values[2] 817 1 T52 21 T27 20 T59 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1264 1 T52 29 T27 28 T59 7
auto[1] 1187 1 T52 34 T27 32 T59 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 875 1 T52 23 T27 13 T59 8
auto[1] 1576 1 T52 40 T27 47 T59 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1400 1 T52 35 T27 28 T59 9
auto[1] 1051 1 T52 28 T27 32 T59 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 160 1 T52 6 T27 5 T59 2
all_values[0] auto[0] auto[0] auto[1] 90 1 T52 2 T27 2 T90 1
all_values[0] auto[0] auto[1] auto[0] 166 1 T52 4 T27 5 T59 1
all_values[0] auto[0] auto[1] auto[1] 69 1 T52 2 T27 1 T89 1
all_values[0] auto[1] auto[0] auto[1] 171 1 T52 3 T27 2 T59 1
all_values[0] auto[1] auto[1] auto[1] 161 1 T52 4 T27 5 T90 1
all_values[1] auto[0] auto[0] auto[0] 121 1 T52 2 T59 3 T89 2
all_values[1] auto[0] auto[0] auto[1] 99 1 T27 3 T89 1 T90 1
all_values[1] auto[0] auto[1] auto[0] 116 1 T52 2 T27 2 T59 1
all_values[1] auto[0] auto[1] auto[1] 107 1 T52 4 T27 3 T89 4
all_values[1] auto[1] auto[0] auto[1] 205 1 T52 5 T27 5 T89 4
all_values[1] auto[1] auto[1] auto[1] 169 1 T52 8 T27 7 T89 2
all_values[2] auto[0] auto[0] auto[0] 170 1 T52 5 T59 1 T89 3
all_values[2] auto[0] auto[0] auto[1] 92 1 T52 2 T27 4 T89 2
all_values[2] auto[0] auto[1] auto[0] 142 1 T52 4 T27 1 T89 3
all_values[2] auto[0] auto[1] auto[1] 68 1 T52 2 T27 2 T59 1
all_values[2] auto[1] auto[0] auto[1] 156 1 T52 4 T27 7 T89 3
all_values[2] auto[1] auto[1] auto[1] 189 1 T52 4 T27 6 T59 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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