Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4024	1			T1	7		T2	5		T3	8
sha2_none	4027	1			T1	3		T2	10		T3	17
sha2_512	7322	1			T1	12		T2	5		T3	8
sha2_384	7249	1			T1	5		T2	5		T3	8
sha2_256	6146	1			T1	6		T2	10		T3	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18329

1

T1

16

T2

21

T3

27

auto[1]

10835

1

T1

18

T2

14

T3

22

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10809

1

T1

13

T2

16

T3

28

auto[1]

18355

1

T1

21

T2

19

T3

21

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14955

1

T1

19

T2

16

T3

49

disabled

14209

1

T1

15

T2

19

T4

6

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4381	1			T1	9		T2	6		T3	8
key_none	7754	1			T1	4		T2	6		T3	4
key_1024	4286	1			T1	2		T2	6		T3	8
key_512	3533	1			T1	7		T2	3		T3	4
key_384	3364	1			T1	5		T2	4		T3	11
key_256	2908	1			T1	3		T2	4		T3	6
key_128	2872	1			T1	4		T2	6		T3	8

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18319

1

T1

13

T2

19

T3

24

auto[1]

10845

1

T1

21

T2

16

T3

25

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28973

1

T1

32

T2

35

T3

49

disabled

191

1

T1

2

T52

2

T54

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1464

1

T1

1

T2

4

T3

6

enabled

auto[0]

auto[0]

auto[1]

1571

1

T1

4

T3

9

T8

3

enabled

auto[0]

auto[1]

auto[0]

1504

1

T1

1

T2

2

T3

5

enabled

auto[0]

auto[1]

auto[1]

1533

1

T1

3

T2

1

T3

8

enabled

auto[1]

auto[0]

auto[0]

4214

1

T1

1

T2

2

T3

8

enabled

auto[1]

auto[0]

auto[1]

1537

1

T1

6

T2

5

T3

4

enabled

auto[1]

auto[1]

auto[0]

1621

1

T1

3

T2

2

T3

5

enabled

auto[1]

auto[1]

auto[1]

1511

1

T3

4

T8

1

T12

2

disabled

auto[0]

auto[0]

auto[0]

1193

1

T1

1

T2

1

T8

3

disabled

auto[0]

auto[0]

auto[1]

1169

1

T2

1

T12

2

T7

2

disabled

auto[0]

auto[1]

auto[0]

1221

1

T1

1

T2

3

T4

1

disabled

auto[0]

auto[1]

auto[1]

1154

1

T1

2

T2

4

T4

2

disabled

auto[1]

auto[0]

auto[0]

5975

1

T1

1

T2

4

T8

2

disabled

auto[1]

auto[0]

auto[1]

1206

1

T1

2

T2

4

T8

1

disabled

auto[1]

auto[1]

auto[0]

1127

1

T1

4

T2

1

T4

1

disabled

auto[1]

auto[1]

auto[1]

1164

1

T1

4

T2

1

T4

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14879

1

T1

18

T2

16

T3

49

enabled

disabled

76

1

T1

1

T52

1

T99

1

disabled

disabled

115

1

T1

1

T52

1

T54

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14094

1

T1

14

T2

19

T4

6

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1035	1			T1	4		T6	2		T12	1
key_invalid	sha2_none	808	1			T1	1		T2	2		T3	6
key_invalid	sha2_512	791	1			T1	2		T2	2		T3	1
key_invalid	sha2_384	825	1			T8	3		T12	1		T7	1
key_invalid	sha2_256	824	1			T1	1		T2	2		T3	1
key_none	sha2_invalid	484	1			T2	1		T4	1		T5	1
key_none	sha2_none	534	1			T2	1		T3	1		T8	1
key_none	sha2_512	2517	1			T1	1		T4	2		T8	1
key_none	sha2_384	2570	1			T3	1		T6	2		T7	1
key_none	sha2_256	1606	1			T1	3		T2	4		T3	2
key_1024	sha2_invalid	504	1			T3	1		T8	1		T7	1
key_1024	sha2_none	534	1			T1	1		T2	2		T3	2
key_1024	sha2_512	1739	1			T1	1		T2	1		T3	3
key_1024	sha2_384	884	1			T2	2		T3	1		T12	1
key_512	sha2_invalid	470	1			T1	1		T12	1		T7	1
key_512	sha2_none	521	1			T1	1		T2	2		T3	2
key_512	sha2_512	541	1			T1	2		T22	1		T23	1
key_512	sha2_384	1187	1			T1	3		T2	1		T3	1
key_512	sha2_256	767	1			T3	1		T8	1		T7	1
key_384	sha2_invalid	518	1			T1	1		T2	2		T3	3
key_384	sha2_none	554	1			T2	1		T3	3		T8	2
key_384	sha2_512	555	1			T1	3		T3	2		T12	1
key_384	sha2_384	608	1			T3	2		T12	1		T16	2
key_384	sha2_256	1085	1			T1	1		T2	1		T3	1
key_256	sha2_invalid	503	1			T2	1		T6	3		T16	2
key_256	sha2_none	545	1			T3	2		T4	2		T8	1
key_256	sha2_512	586	1			T1	1		T2	1		T3	1
key_256	sha2_384	578	1			T1	2		T2	1		T3	2
key_256	sha2_256	639	1			T2	1		T12	1		T7	1
key_128	sha2_invalid	494	1			T1	1		T2	1		T3	4
key_128	sha2_none	519	1			T2	2		T3	1		T8	1
key_128	sha2_512	583	1			T1	2		T2	1		T3	1
key_128	sha2_384	585	1			T2	1		T3	1		T8	1
key_128	sha2_256	638	1			T1	1		T2	1		T3	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

573

1

T2

1

T3

1

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1035	1			T1	4		T6	2		T12	1
key_invalid	sha2_none	808	1			T1	1		T2	2		T3	6
key_invalid	sha2_512	791	1			T1	2		T2	2		T3	1
key_invalid	sha2_384	825	1			T8	3		T12	1		T7	1
key_invalid	sha2_256	824	1			T1	1		T2	2		T3	1
key_none	sha2_invalid	484	1			T2	1		T4	1		T5	1
key_none	sha2_none	534	1			T2	1		T3	1		T8	1
key_none	sha2_512	2517	1			T1	1		T4	2		T8	1
key_none	sha2_384	2570	1			T3	1		T6	2		T7	1
key_none	sha2_256	1606	1			T1	3		T2	4		T3	2
key_1024	sha2_invalid	504	1			T3	1		T8	1		T7	1
key_1024	sha2_none	534	1			T1	1		T2	2		T3	2
key_1024	sha2_512	1739	1			T1	1		T2	1		T3	3
key_1024	sha2_384	884	1			T2	2		T3	1		T12	1
key_1024	sha2_256	573	1			T2	1		T3	1		T7	1
key_512	sha2_invalid	470	1			T1	1		T12	1		T7	1
key_512	sha2_none	521	1			T1	1		T2	2		T3	2
key_512	sha2_512	541	1			T1	2		T22	1		T23	1
key_512	sha2_384	1187	1			T1	3		T2	1		T3	1
key_512	sha2_256	767	1			T3	1		T8	1		T7	1
key_384	sha2_invalid	518	1			T1	1		T2	2		T3	3
key_384	sha2_none	554	1			T2	1		T3	3		T8	2
key_384	sha2_512	555	1			T1	3		T3	2		T12	1
key_384	sha2_384	608	1			T3	2		T12	1		T16	2
key_384	sha2_256	1085	1			T1	1		T2	1		T3	1
key_256	sha2_invalid	503	1			T2	1		T6	3		T16	2
key_256	sha2_none	545	1			T3	2		T4	2		T8	1
key_256	sha2_512	586	1			T1	1		T2	1		T3	1
key_256	sha2_384	578	1			T1	2		T2	1		T3	2
key_256	sha2_256	639	1			T2	1		T12	1		T7	1
key_128	sha2_invalid	494	1			T1	1		T2	1		T3	4
key_128	sha2_none	519	1			T2	2		T3	1		T8	1
key_128	sha2_512	583	1			T1	2		T2	1		T3	1
key_128	sha2_384	585	1			T2	1		T3	1		T8	1
key_128	sha2_256	638	1			T1	1		T2	1		T3	1