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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85


Total test records in report: 653
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T539 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1959624548 Aug 14 04:46:42 PM PDT 24 Aug 14 04:46:43 PM PDT 24 49327270 ps
T77 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.191504491 Aug 14 04:46:44 PM PDT 24 Aug 14 04:46:47 PM PDT 24 47587386 ps
T540 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1249517680 Aug 14 04:46:52 PM PDT 24 Aug 14 04:46:53 PM PDT 24 19109202 ps
T78 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4266642436 Aug 14 04:46:32 PM PDT 24 Aug 14 04:46:33 PM PDT 24 140120964 ps
T79 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3099345083 Aug 14 04:46:35 PM PDT 24 Aug 14 04:46:37 PM PDT 24 66955052 ps
T120 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1486002895 Aug 14 04:46:23 PM PDT 24 Aug 14 04:46:24 PM PDT 24 17589549 ps
T105 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1476925590 Aug 14 04:46:57 PM PDT 24 Aug 14 04:46:59 PM PDT 24 196362053 ps
T106 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4144628984 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:42 PM PDT 24 109286392 ps
T541 /workspace/coverage/cover_reg_top/9.hmac_intr_test.46091044 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:37 PM PDT 24 14573258 ps
T137 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1788037598 Aug 14 04:46:27 PM PDT 24 Aug 14 04:46:28 PM PDT 24 16069128 ps
T138 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2091205088 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:26 PM PDT 24 229787122 ps
T542 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.829867360 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:44 PM PDT 24 320914369 ps
T121 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.107484104 Aug 14 04:46:35 PM PDT 24 Aug 14 04:46:36 PM PDT 24 17071025 ps
T543 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4281553463 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:46 PM PDT 24 223074523 ps
T122 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1826669747 Aug 14 04:46:34 PM PDT 24 Aug 14 04:46:35 PM PDT 24 153615659 ps
T544 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1352335378 Aug 14 04:46:57 PM PDT 24 Aug 14 04:46:58 PM PDT 24 11395976 ps
T123 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.454143147 Aug 14 04:46:24 PM PDT 24 Aug 14 04:46:25 PM PDT 24 100880641 ps
T139 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.492149852 Aug 14 04:46:45 PM PDT 24 Aug 14 04:46:47 PM PDT 24 86590484 ps
T124 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3273051401 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:26 PM PDT 24 73387910 ps
T545 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3561067032 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:32 PM PDT 24 13980311 ps
T546 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3750668431 Aug 14 04:46:33 PM PDT 24 Aug 14 04:46:35 PM PDT 24 255399654 ps
T547 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3822469103 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:44 PM PDT 24 41983522 ps
T140 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.962157182 Aug 14 04:46:30 PM PDT 24 Aug 14 04:46:31 PM PDT 24 54821679 ps
T548 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3214096583 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:42 PM PDT 24 76543241 ps
T549 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2785057947 Aug 14 04:47:02 PM PDT 24 Aug 14 04:47:03 PM PDT 24 16143325 ps
T141 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2299794920 Aug 14 04:46:20 PM PDT 24 Aug 14 04:46:22 PM PDT 24 106529629 ps
T550 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2033479551 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:44 PM PDT 24 41087743 ps
T142 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3848386678 Aug 14 04:46:41 PM PDT 24 Aug 14 04:46:42 PM PDT 24 31812634 ps
T129 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1512253693 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:30 PM PDT 24 453633893 ps
T551 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1760688607 Aug 14 04:46:37 PM PDT 24 Aug 14 04:46:40 PM PDT 24 238885255 ps
T552 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.445608080 Aug 14 04:47:07 PM PDT 24 Aug 14 04:47:08 PM PDT 24 21052569 ps
T553 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3714309041 Aug 14 04:46:34 PM PDT 24 Aug 14 04:46:38 PM PDT 24 260684807 ps
T554 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2974955774 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:31 PM PDT 24 152663931 ps
T555 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2590388874 Aug 14 04:46:33 PM PDT 24 Aug 14 04:46:36 PM PDT 24 130565483 ps
T556 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2171807306 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:49 PM PDT 24 78969986 ps
T557 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2624778115 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:49 PM PDT 24 44634958 ps
T72 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3257860707 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:48 PM PDT 24 85395874 ps
T558 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2457629084 Aug 14 04:46:53 PM PDT 24 Aug 14 04:46:54 PM PDT 24 37318478 ps
T125 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1514137926 Aug 14 04:46:28 PM PDT 24 Aug 14 04:46:29 PM PDT 24 106841140 ps
T559 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2629494627 Aug 14 04:46:13 PM PDT 24 Aug 14 04:46:18 PM PDT 24 887048100 ps
T147 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1711182231 Aug 14 04:46:23 PM PDT 24 Aug 14 04:46:25 PM PDT 24 1098850012 ps
T154 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2430088697 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:42 PM PDT 24 155993891 ps
T560 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3164132850 Aug 14 04:46:53 PM PDT 24 Aug 14 04:46:53 PM PDT 24 13611905 ps
T561 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3622521010 Aug 14 04:46:42 PM PDT 24 Aug 14 04:46:42 PM PDT 24 10216416 ps
T562 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2162284471 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:44 PM PDT 24 167391849 ps
T563 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1878372132 Aug 14 04:46:58 PM PDT 24 Aug 14 04:46:59 PM PDT 24 20662166 ps
T564 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1562336369 Aug 14 04:46:58 PM PDT 24 Aug 14 04:46:59 PM PDT 24 34305586 ps
T155 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3643420627 Aug 14 04:46:23 PM PDT 24 Aug 14 04:46:26 PM PDT 24 1266395567 ps
T565 /workspace/coverage/cover_reg_top/26.hmac_intr_test.615970345 Aug 14 04:46:54 PM PDT 24 Aug 14 04:46:54 PM PDT 24 63194504 ps
T566 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1389730095 Aug 14 04:47:00 PM PDT 24 Aug 14 05:07:11 PM PDT 24 254055766422 ps
T567 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4146639944 Aug 14 04:47:17 PM PDT 24 Aug 14 04:47:18 PM PDT 24 13424210 ps
T126 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3999399590 Aug 14 04:46:35 PM PDT 24 Aug 14 04:46:39 PM PDT 24 196591473 ps
T568 /workspace/coverage/cover_reg_top/28.hmac_intr_test.388823623 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:48 PM PDT 24 15937992 ps
T569 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2884859616 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:46 PM PDT 24 31169204 ps
T570 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2612739139 Aug 14 04:46:34 PM PDT 24 Aug 14 04:54:09 PM PDT 24 33792710645 ps
T571 /workspace/coverage/cover_reg_top/23.hmac_intr_test.478741951 Aug 14 04:46:45 PM PDT 24 Aug 14 04:46:45 PM PDT 24 76434390 ps
T572 /workspace/coverage/cover_reg_top/14.hmac_intr_test.159980046 Aug 14 04:46:58 PM PDT 24 Aug 14 04:46:59 PM PDT 24 13857603 ps
T573 /workspace/coverage/cover_reg_top/22.hmac_intr_test.723405806 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:48 PM PDT 24 128592382 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_intr_test.4045320061 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:41 PM PDT 24 14168407 ps
T575 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3358416574 Aug 14 04:46:52 PM PDT 24 Aug 14 04:46:53 PM PDT 24 163709880 ps
T576 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3806900204 Aug 14 04:46:49 PM PDT 24 Aug 14 04:46:50 PM PDT 24 294525769 ps
T577 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1337972378 Aug 14 04:46:51 PM PDT 24 Aug 14 04:46:53 PM PDT 24 171917866 ps
T578 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3963162832 Aug 14 04:46:41 PM PDT 24 Aug 14 04:46:43 PM PDT 24 183259429 ps
T579 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1578664808 Aug 14 04:46:26 PM PDT 24 Aug 14 04:46:26 PM PDT 24 16134782 ps
T580 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4148842886 Aug 14 04:46:34 PM PDT 24 Aug 14 04:46:35 PM PDT 24 51128250 ps
T581 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3151013463 Aug 14 04:46:52 PM PDT 24 Aug 14 04:46:53 PM PDT 24 209235109 ps
T151 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.254971503 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:51 PM PDT 24 1457385211 ps
T582 /workspace/coverage/cover_reg_top/16.hmac_intr_test.196998955 Aug 14 04:46:45 PM PDT 24 Aug 14 04:46:45 PM PDT 24 58350264 ps
T583 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1867809741 Aug 14 04:46:49 PM PDT 24 Aug 14 04:46:49 PM PDT 24 36965412 ps
T584 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3375704880 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:48 PM PDT 24 71623830 ps
T585 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1270430695 Aug 14 04:46:33 PM PDT 24 Aug 14 04:46:36 PM PDT 24 261289128 ps
T586 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1472350683 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:49 PM PDT 24 155793976 ps
T587 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.817962898 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:31 PM PDT 24 90477668 ps
T588 /workspace/coverage/cover_reg_top/47.hmac_intr_test.948416267 Aug 14 04:47:34 PM PDT 24 Aug 14 04:47:35 PM PDT 24 56720995 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2832002573 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:46 PM PDT 24 219688155 ps
T127 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.385835206 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:49 PM PDT 24 44717967 ps
T128 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.384123287 Aug 14 04:46:19 PM PDT 24 Aug 14 04:46:20 PM PDT 24 99330944 ps
T590 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2434018944 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:36 PM PDT 24 13046129 ps
T591 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3602331802 Aug 14 04:46:51 PM PDT 24 Aug 14 04:46:52 PM PDT 24 26222746 ps
T130 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2669336252 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:41 PM PDT 24 34264204 ps
T592 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3125972636 Aug 14 04:46:32 PM PDT 24 Aug 14 04:46:33 PM PDT 24 25234713 ps
T148 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1893103179 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:47 PM PDT 24 152881542 ps
T593 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2725793787 Aug 14 04:46:37 PM PDT 24 Aug 14 04:46:40 PM PDT 24 277539958 ps
T594 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1006837639 Aug 14 04:46:51 PM PDT 24 Aug 14 04:46:52 PM PDT 24 78632749 ps
T595 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3910619882 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:48 PM PDT 24 11833050 ps
T596 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2773578264 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:28 PM PDT 24 87244429 ps
T597 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2693035229 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:47 PM PDT 24 42050109 ps
T598 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1361774484 Aug 14 04:46:55 PM PDT 24 Aug 14 04:46:59 PM PDT 24 443441754 ps
T599 /workspace/coverage/cover_reg_top/11.hmac_intr_test.4240752759 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:37 PM PDT 24 11626642 ps
T600 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1674179516 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:49 PM PDT 24 12969849 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1915055022 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:39 PM PDT 24 550394119 ps
T152 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1077329908 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:45 PM PDT 24 100315094 ps
T131 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3909851481 Aug 14 04:46:45 PM PDT 24 Aug 14 04:46:46 PM PDT 24 56371997 ps
T602 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.493121444 Aug 14 04:46:34 PM PDT 24 Aug 14 04:46:37 PM PDT 24 713703623 ps
T603 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1485190349 Aug 14 04:46:32 PM PDT 24 Aug 14 04:46:38 PM PDT 24 303641412 ps
T604 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3681382393 Aug 14 04:46:35 PM PDT 24 Aug 14 04:46:38 PM PDT 24 344643991 ps
T605 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2741317848 Aug 14 04:46:40 PM PDT 24 Aug 14 04:46:43 PM PDT 24 651249420 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3958167740 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:32 PM PDT 24 21359174 ps
T607 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1017494480 Aug 14 04:46:41 PM PDT 24 Aug 14 04:46:41 PM PDT 24 12378731 ps
T608 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1546217645 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:48 PM PDT 24 24377066 ps
T609 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.577741885 Aug 14 04:46:51 PM PDT 24 Aug 14 04:46:53 PM PDT 24 1048123042 ps
T610 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3332798542 Aug 14 04:46:35 PM PDT 24 Aug 14 04:46:36 PM PDT 24 56314893 ps
T611 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.803163861 Aug 14 04:46:34 PM PDT 24 Aug 14 04:46:36 PM PDT 24 123774729 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3784590598 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:35 PM PDT 24 183329370 ps
T149 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.898229801 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:34 PM PDT 24 441056188 ps
T613 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.204596865 Aug 14 04:46:33 PM PDT 24 Aug 14 04:46:35 PM PDT 24 48522974 ps
T150 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.964966428 Aug 14 04:46:39 PM PDT 24 Aug 14 04:46:42 PM PDT 24 125356206 ps
T614 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3952827679 Aug 14 04:46:50 PM PDT 24 Aug 14 04:46:52 PM PDT 24 706000353 ps
T615 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2767269927 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:27 PM PDT 24 59229280 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.994366724 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:47 PM PDT 24 59258585 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.404391069 Aug 14 04:46:42 PM PDT 24 Aug 14 04:46:48 PM PDT 24 1085773426 ps
T618 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1434306973 Aug 14 04:46:32 PM PDT 24 Aug 14 04:46:34 PM PDT 24 130097161 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1844324637 Aug 14 04:46:44 PM PDT 24 Aug 14 04:46:47 PM PDT 24 305843769 ps
T156 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2990255283 Aug 14 04:46:54 PM PDT 24 Aug 14 04:46:58 PM PDT 24 1171870336 ps
T620 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4232453145 Aug 14 04:46:49 PM PDT 24 Aug 14 04:46:50 PM PDT 24 14709656 ps
T621 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2969769072 Aug 14 04:46:30 PM PDT 24 Aug 14 04:46:31 PM PDT 24 65630962 ps
T132 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2782042535 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:37 PM PDT 24 50983176 ps
T622 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.935045361 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:50 PM PDT 24 119699563 ps
T623 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2068279214 Aug 14 04:46:25 PM PDT 24 Aug 14 04:46:41 PM PDT 24 1411270798 ps
T624 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.296076854 Aug 14 04:46:48 PM PDT 24 Aug 14 04:46:53 PM PDT 24 1461761684 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3720574053 Aug 14 04:46:23 PM PDT 24 Aug 14 04:46:26 PM PDT 24 633626491 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1877296062 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:32 PM PDT 24 11085509 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1850783191 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:31 PM PDT 24 149747065 ps
T628 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3027971722 Aug 14 04:46:31 PM PDT 24 Aug 14 04:46:37 PM PDT 24 120616692 ps
T133 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1863138399 Aug 14 04:46:39 PM PDT 24 Aug 14 04:46:45 PM PDT 24 759588985 ps
T629 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1755498600 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:30 PM PDT 24 24100605 ps
T134 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1588361704 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:44 PM PDT 24 48986486 ps
T630 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1537996033 Aug 14 04:46:56 PM PDT 24 Aug 14 04:46:57 PM PDT 24 20888929 ps
T631 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1647578153 Aug 14 04:46:55 PM PDT 24 Aug 14 04:46:56 PM PDT 24 12061438 ps
T632 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1838803767 Aug 14 04:46:59 PM PDT 24 Aug 14 04:47:00 PM PDT 24 46580290 ps
T633 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3671333988 Aug 14 04:46:51 PM PDT 24 Aug 14 04:46:52 PM PDT 24 27200769 ps
T153 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.152327811 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:48 PM PDT 24 332417521 ps
T634 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1090165583 Aug 14 04:46:33 PM PDT 24 Aug 14 04:46:34 PM PDT 24 50325061 ps
T635 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3514617816 Aug 14 04:46:52 PM PDT 24 Aug 14 04:46:53 PM PDT 24 13544946 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.236550713 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:50 PM PDT 24 825811055 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2299213124 Aug 14 04:46:30 PM PDT 24 Aug 14 04:46:32 PM PDT 24 113043304 ps
T638 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1057555919 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:33 PM PDT 24 128460235 ps
T639 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3668555786 Aug 14 04:46:37 PM PDT 24 Aug 14 04:46:38 PM PDT 24 15781347 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1336540430 Aug 14 04:46:49 PM PDT 24 Aug 14 04:46:50 PM PDT 24 141770816 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3643568761 Aug 14 04:46:37 PM PDT 24 Aug 14 04:46:39 PM PDT 24 108361247 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.978339087 Aug 14 04:46:20 PM PDT 24 Aug 14 04:46:22 PM PDT 24 366245638 ps
T643 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2464317208 Aug 14 04:46:30 PM PDT 24 Aug 14 04:46:33 PM PDT 24 84764981 ps
T644 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2427245350 Aug 14 04:46:47 PM PDT 24 Aug 14 04:46:49 PM PDT 24 49401260 ps
T645 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1669369430 Aug 14 04:46:24 PM PDT 24 Aug 14 04:46:26 PM PDT 24 430377963 ps
T646 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3585527053 Aug 14 04:46:29 PM PDT 24 Aug 14 04:46:30 PM PDT 24 54963443 ps
T647 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2891881249 Aug 14 04:46:55 PM PDT 24 Aug 14 04:46:56 PM PDT 24 11559928 ps
T648 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3072308727 Aug 14 04:46:49 PM PDT 24 Aug 14 04:46:50 PM PDT 24 20272924 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1763477997 Aug 14 04:46:43 PM PDT 24 Aug 14 04:46:46 PM PDT 24 133421303 ps
T650 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1149887897 Aug 14 04:46:36 PM PDT 24 Aug 14 04:46:38 PM PDT 24 97019258 ps
T651 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2088026237 Aug 14 04:46:28 PM PDT 24 Aug 14 04:46:30 PM PDT 24 81857935 ps
T652 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2223270269 Aug 14 04:46:39 PM PDT 24 Aug 14 04:46:41 PM PDT 24 262986099 ps
T653 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.853912235 Aug 14 04:46:16 PM PDT 24 Aug 14 04:46:18 PM PDT 24 212025306 ps
T74 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2139390065 Aug 14 04:46:46 PM PDT 24 Aug 14 04:46:50 PM PDT 24 951014226 ps

Test location /workspace/coverage/default/16.hmac_long_msg.925400869
Short name T2
Test name
Test status
Simulation time 23803203512 ps
CPU time 125.47 seconds
Started Aug 14 05:15:39 PM PDT 24
Finished Aug 14 05:17:44 PM PDT 24
Peak memory 200704 kb
Host smart-b1fcb5a1-957b-417b-8afd-d24fc055a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925400869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.925400869
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1637180323
Short name T22
Test name
Test status
Simulation time 48635652099 ps
CPU time 210.72 seconds
Started Aug 14 05:15:40 PM PDT 24
Finished Aug 14 05:19:11 PM PDT 24
Peak memory 217120 kb
Host smart-3086ee1c-f05b-4cbc-a2b5-2f6fa4de6f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637180323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1637180323
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2957351024
Short name T10
Test name
Test status
Simulation time 109739213868 ps
CPU time 978.4 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:31:32 PM PDT 24
Peak memory 715388 kb
Host smart-4c66c437-4173-4274-a36b-58e98bee0d80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957351024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2957351024
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2798899239
Short name T52
Test name
Test status
Simulation time 54343857179 ps
CPU time 461.1 seconds
Started Aug 14 05:15:50 PM PDT 24
Finished Aug 14 05:23:31 PM PDT 24
Peak memory 209288 kb
Host smart-a1d0fe2f-c38a-4c61-85ee-c85462afca63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798899239 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2798899239
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1564312975
Short name T19
Test name
Test status
Simulation time 83106435764 ps
CPU time 1878.33 seconds
Started Aug 14 05:15:18 PM PDT 24
Finished Aug 14 05:46:36 PM PDT 24
Peak memory 769680 kb
Host smart-008b9e39-b771-4c2f-8ce9-0f0b9c3dfd91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564312975 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1564312975
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.969158871
Short name T71
Test name
Test status
Simulation time 467033791 ps
CPU time 4.46 seconds
Started Aug 14 04:46:30 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 200308 kb
Host smart-fef2b806-ce36-4ba6-b0cd-f17291ec5ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969158871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.969158871
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.624936765
Short name T60
Test name
Test status
Simulation time 387307499 ps
CPU time 1.01 seconds
Started Aug 14 05:15:07 PM PDT 24
Finished Aug 14 05:15:08 PM PDT 24
Peak memory 220136 kb
Host smart-484b3464-911f-4ce6-9a5e-4c4623c824c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624936765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.624936765
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2321147095
Short name T89
Test name
Test status
Simulation time 744692392761 ps
CPU time 846.27 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:30:24 PM PDT 24
Peak memory 208980 kb
Host smart-c09533e6-3f33-41c9-9fdc-e04ab88a02eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321147095 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2321147095
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2088471905
Short name T29
Test name
Test status
Simulation time 35182545497 ps
CPU time 930.91 seconds
Started Aug 14 05:15:27 PM PDT 24
Finished Aug 14 05:30:58 PM PDT 24
Peak memory 217104 kb
Host smart-853908a6-bd4b-443b-827b-f565182b7e34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088471905 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2088471905
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.107484104
Short name T121
Test name
Test status
Simulation time 17071025 ps
CPU time 0.83 seconds
Started Aug 14 04:46:35 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 200092 kb
Host smart-3ba586fd-6ffa-4b4c-a811-edd2d4ad1188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107484104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.107484104
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3063701279
Short name T295
Test name
Test status
Simulation time 16288373882 ps
CPU time 1073.73 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:33:30 PM PDT 24
Peak memory 643612 kb
Host smart-1bc0d09c-1bf8-4df1-9c8b-3c53de881ba4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063701279 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3063701279
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3307648866
Short name T57
Test name
Test status
Simulation time 14921167 ps
CPU time 0.59 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:14:58 PM PDT 24
Peak memory 197440 kb
Host smart-a4c14278-e3e6-4f06-b0bf-44541373710b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307648866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3307648866
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2139390065
Short name T74
Test name
Test status
Simulation time 951014226 ps
CPU time 3.95 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 200196 kb
Host smart-d94fd8c0-c209-4dd7-8442-c3caaf881129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139390065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2139390065
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.898229801
Short name T149
Test name
Test status
Simulation time 441056188 ps
CPU time 2.8 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:34 PM PDT 24
Peak memory 200304 kb
Host smart-505ac54e-ed79-4aeb-9a9a-fc1c4361c7ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898229801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.898229801
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3870598484
Short name T3
Test name
Test status
Simulation time 11300565100 ps
CPU time 1471.53 seconds
Started Aug 14 05:15:40 PM PDT 24
Finished Aug 14 05:40:12 PM PDT 24
Peak memory 778720 kb
Host smart-04c1efe1-3ae2-4ce7-b157-b5be258e1503
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3870598484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3870598484
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1863138399
Short name T133
Test name
Test status
Simulation time 759588985 ps
CPU time 6.01 seconds
Started Aug 14 04:46:39 PM PDT 24
Finished Aug 14 04:46:45 PM PDT 24
Peak memory 200260 kb
Host smart-a2baf226-152f-4620-a452-e6554b7f49d0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863138399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1863138399
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3776239665
Short name T114
Test name
Test status
Simulation time 25148701862 ps
CPU time 151.79 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:17:33 PM PDT 24
Peak memory 200736 kb
Host smart-968a974b-c3b5-4066-88d7-f6b0cc00bec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776239665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3776239665
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2984053702
Short name T158
Test name
Test status
Simulation time 221504820 ps
CPU time 11.96 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:15:48 PM PDT 24
Peak memory 200700 kb
Host smart-a630532f-7c2c-41dc-9a22-c8afd7436a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984053702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2984053702
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2832002573
Short name T589
Test name
Test status
Simulation time 219688155 ps
CPU time 3.29 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:46 PM PDT 24
Peak memory 200284 kb
Host smart-c8fa1dfc-f9d1-4441-a607-03dacec1677a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832002573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2832002573
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3027971722
Short name T628
Test name
Test status
Simulation time 120616692 ps
CPU time 5.11 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 200268 kb
Host smart-72c07578-52de-4f24-8ac8-c83a8155e2ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027971722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3027971722
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3958167740
Short name T606
Test name
Test status
Simulation time 21359174 ps
CPU time 0.75 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:32 PM PDT 24
Peak memory 198420 kb
Host smart-d0cd95e4-c3d7-41b4-9bde-032d732fd1ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958167740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3958167740
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2612739139
Short name T570
Test name
Test status
Simulation time 33792710645 ps
CPU time 454.77 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:54:09 PM PDT 24
Peak memory 216844 kb
Host smart-f5ae0de0-a3c6-433f-ba36-469bc970a8cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612739139 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2612739139
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3848386678
Short name T142
Test name
Test status
Simulation time 31812634 ps
CPU time 0.99 seconds
Started Aug 14 04:46:41 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 200020 kb
Host smart-3cff7e2f-412e-4f40-b675-43866f40a6bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848386678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3848386678
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1755498600
Short name T629
Test name
Test status
Simulation time 24100605 ps
CPU time 0.61 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:30 PM PDT 24
Peak memory 195268 kb
Host smart-f244f4e1-95ba-4bb6-b0ad-94c849d1a2dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755498600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1755498600
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2299794920
Short name T141
Test name
Test status
Simulation time 106529629 ps
CPU time 1.76 seconds
Started Aug 14 04:46:20 PM PDT 24
Finished Aug 14 04:46:22 PM PDT 24
Peak memory 200224 kb
Host smart-ebdd26d8-f00a-4893-a8af-40a1571b3871
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299794920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2299794920
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3784590598
Short name T612
Test name
Test status
Simulation time 183329370 ps
CPU time 3.91 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 200288 kb
Host smart-3f9ea957-8274-4e6b-a25f-75f74fa8794f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784590598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3784590598
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1057555919
Short name T638
Test name
Test status
Simulation time 128460235 ps
CPU time 4.2 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 200168 kb
Host smart-17c8323e-8637-492a-97d1-16d85b48f73c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057555919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1057555919
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1485190349
Short name T603
Test name
Test status
Simulation time 303641412 ps
CPU time 5.86 seconds
Started Aug 14 04:46:32 PM PDT 24
Finished Aug 14 04:46:38 PM PDT 24
Peak memory 200100 kb
Host smart-efac9a7e-7553-4e97-8bea-e55968981822
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485190349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1485190349
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2299213124
Short name T637
Test name
Test status
Simulation time 113043304 ps
CPU time 0.87 seconds
Started Aug 14 04:46:30 PM PDT 24
Finished Aug 14 04:46:32 PM PDT 24
Peak memory 199804 kb
Host smart-7f201718-3e93-4191-876e-19340fa921cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299213124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2299213124
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2969769072
Short name T621
Test name
Test status
Simulation time 65630962 ps
CPU time 1.03 seconds
Started Aug 14 04:46:30 PM PDT 24
Finished Aug 14 04:46:31 PM PDT 24
Peak memory 200032 kb
Host smart-e3823eb9-0b0b-4ad6-9cda-85a5400d3f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969769072 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2969769072
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1090165583
Short name T634
Test name
Test status
Simulation time 50325061 ps
CPU time 0.98 seconds
Started Aug 14 04:46:33 PM PDT 24
Finished Aug 14 04:46:34 PM PDT 24
Peak memory 200024 kb
Host smart-0f4ea589-a2b1-483b-a849-f1e861813842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090165583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1090165583
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.4045320061
Short name T574
Test name
Test status
Simulation time 14168407 ps
CPU time 0.65 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 195356 kb
Host smart-773bbcb4-eeeb-4b82-99d8-aaf518a6cf28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045320061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.4045320061
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2015797585
Short name T136
Test name
Test status
Simulation time 45456323 ps
CPU time 1.12 seconds
Started Aug 14 04:46:24 PM PDT 24
Finished Aug 14 04:46:25 PM PDT 24
Peak memory 200288 kb
Host smart-bfb3e950-7103-4ddd-9130-ffb8210fa9ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015797585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2015797585
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1850783191
Short name T627
Test name
Test status
Simulation time 149747065 ps
CPU time 1.69 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:31 PM PDT 24
Peak memory 200284 kb
Host smart-06927dec-eaa6-4d7a-8e14-d7e78e906c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850783191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1850783191
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1711182231
Short name T147
Test name
Test status
Simulation time 1098850012 ps
CPU time 1.87 seconds
Started Aug 14 04:46:23 PM PDT 24
Finished Aug 14 04:46:25 PM PDT 24
Peak memory 200296 kb
Host smart-83309012-2ca2-4089-b639-ae73a6e95e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711182231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1711182231
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3375704880
Short name T584
Test name
Test status
Simulation time 71623830 ps
CPU time 2.35 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 200344 kb
Host smart-05abc951-c179-4b5b-9148-71dd42c69475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375704880 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3375704880
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3088924218
Short name T536
Test name
Test status
Simulation time 44746609 ps
CPU time 0.61 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 195272 kb
Host smart-751d93e1-95bc-4d2a-abc5-a517b7ed0585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088924218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3088924218
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1546217645
Short name T608
Test name
Test status
Simulation time 24377066 ps
CPU time 1.15 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 198936 kb
Host smart-d1d6b7d5-6410-4bce-95f0-4e7377d86715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546217645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1546217645
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3643568761
Short name T641
Test name
Test status
Simulation time 108361247 ps
CPU time 1.67 seconds
Started Aug 14 04:46:37 PM PDT 24
Finished Aug 14 04:46:39 PM PDT 24
Peak memory 200224 kb
Host smart-90984ff3-9d1a-45fb-ab5f-aecaea6a8cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643568761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3643568761
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1077329908
Short name T152
Test name
Test status
Simulation time 100315094 ps
CPU time 1.82 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:45 PM PDT 24
Peak memory 200252 kb
Host smart-158c2929-45b8-4fa7-9b45-1f9dbb954cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077329908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1077329908
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2464317208
Short name T643
Test name
Test status
Simulation time 84764981 ps
CPU time 3.06 seconds
Started Aug 14 04:46:30 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 208560 kb
Host smart-1e6e7cd9-8fe8-4911-9ef6-fc0fc4c0ca8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464317208 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2464317208
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1514137926
Short name T125
Test name
Test status
Simulation time 106841140 ps
CPU time 0.82 seconds
Started Aug 14 04:46:28 PM PDT 24
Finished Aug 14 04:46:29 PM PDT 24
Peak memory 200096 kb
Host smart-9ee978ac-fe83-4576-aab5-ac76bf86df68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514137926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1514137926
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.4240752759
Short name T599
Test name
Test status
Simulation time 11626642 ps
CPU time 0.59 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 195248 kb
Host smart-f94f7f51-c28e-40f2-bbbb-116629bd6a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240752759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.4240752759
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2223270269
Short name T652
Test name
Test status
Simulation time 262986099 ps
CPU time 2.25 seconds
Started Aug 14 04:46:39 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 200204 kb
Host smart-77640b24-b6c0-4dd0-9599-bd35efa9bed9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223270269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2223270269
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2162284471
Short name T562
Test name
Test status
Simulation time 167391849 ps
CPU time 3.49 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 200272 kb
Host smart-84d1de76-eb1d-41a7-88cf-6bfad74d0a78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162284471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2162284471
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1149887897
Short name T650
Test name
Test status
Simulation time 97019258 ps
CPU time 1.89 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:38 PM PDT 24
Peak memory 200256 kb
Host smart-286dbd69-06fa-4f08-9750-ea3d2050670f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149887897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1149887897
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.4266642436
Short name T78
Test name
Test status
Simulation time 140120964 ps
CPU time 1.29 seconds
Started Aug 14 04:46:32 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 200248 kb
Host smart-46b0ef62-2853-407b-85a6-996f60126e2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266642436 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.4266642436
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3585527053
Short name T646
Test name
Test status
Simulation time 54963443 ps
CPU time 0.75 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:30 PM PDT 24
Peak memory 197936 kb
Host smart-f878ebbb-52f4-482f-b5d4-7249d1f3931c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585527053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3585527053
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3332798542
Short name T610
Test name
Test status
Simulation time 56314893 ps
CPU time 0.63 seconds
Started Aug 14 04:46:35 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 195356 kb
Host smart-26098e96-bfcd-4d26-a8ea-3dfc11c2e96c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332798542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3332798542
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2974955774
Short name T554
Test name
Test status
Simulation time 152663931 ps
CPU time 1.71 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:31 PM PDT 24
Peak memory 200184 kb
Host smart-f9859cb2-3b49-4515-b133-8fc7035dab57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974955774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2974955774
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2725793787
Short name T593
Test name
Test status
Simulation time 277539958 ps
CPU time 2.68 seconds
Started Aug 14 04:46:37 PM PDT 24
Finished Aug 14 04:46:40 PM PDT 24
Peak memory 200256 kb
Host smart-28013b3d-8ffc-46e5-b557-07ff8d685d7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725793787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2725793787
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2430088697
Short name T154
Test name
Test status
Simulation time 155993891 ps
CPU time 1.91 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 200288 kb
Host smart-23ffa7d3-bff7-4df1-92c4-cf9b7ad2d902
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430088697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2430088697
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2741317848
Short name T605
Test name
Test status
Simulation time 651249420 ps
CPU time 2.77 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:43 PM PDT 24
Peak memory 215700 kb
Host smart-db31e83d-0e19-435f-b029-0df0695ad74b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741317848 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2741317848
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1788037598
Short name T137
Test name
Test status
Simulation time 16069128 ps
CPU time 0.79 seconds
Started Aug 14 04:46:27 PM PDT 24
Finished Aug 14 04:46:28 PM PDT 24
Peak memory 199236 kb
Host smart-002569ea-a32f-44ca-ae60-f4cf30c9cd21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788037598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1788037598
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4148842886
Short name T580
Test name
Test status
Simulation time 51128250 ps
CPU time 0.56 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 195244 kb
Host smart-2a9c410c-0f14-4ff0-ad82-e8c71b6080c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148842886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4148842886
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1337972378
Short name T577
Test name
Test status
Simulation time 171917866 ps
CPU time 2.01 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 200228 kb
Host smart-800d6abb-b82d-45f1-a962-d365c8367b7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337972378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1337972378
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1270430695
Short name T585
Test name
Test status
Simulation time 261289128 ps
CPU time 3.14 seconds
Started Aug 14 04:46:33 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 200160 kb
Host smart-992bea06-7275-442c-8d86-458225e29d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270430695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1270430695
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.152327811
Short name T153
Test name
Test status
Simulation time 332417521 ps
CPU time 1.91 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 200212 kb
Host smart-8375bf87-6323-4743-abd2-4e7a9d0d0242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152327811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.152327811
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1389730095
Short name T566
Test name
Test status
Simulation time 254055766422 ps
CPU time 1210.38 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 05:07:11 PM PDT 24
Peak memory 217088 kb
Host smart-94f50d7c-e59e-44e7-aa8f-a938db301b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389730095 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1389730095
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2669336252
Short name T130
Test name
Test status
Simulation time 34264204 ps
CPU time 0.72 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 198464 kb
Host smart-22977d15-468e-4cbc-8650-a5939f64ae7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669336252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2669336252
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.159980046
Short name T572
Test name
Test status
Simulation time 13857603 ps
CPU time 0.59 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 195188 kb
Host smart-81228bc5-76a8-4f67-9f62-76113e1d43ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159980046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.159980046
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.935045361
Short name T622
Test name
Test status
Simulation time 119699563 ps
CPU time 1.72 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 200280 kb
Host smart-979cb99e-2408-4102-b357-e5320728d47a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935045361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.935045361
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1760688607
Short name T551
Test name
Test status
Simulation time 238885255 ps
CPU time 2.97 seconds
Started Aug 14 04:46:37 PM PDT 24
Finished Aug 14 04:46:40 PM PDT 24
Peak memory 200216 kb
Host smart-15eff687-b080-4c7b-a26a-2be245c5e7bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760688607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1760688607
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.254971503
Short name T151
Test name
Test status
Simulation time 1457385211 ps
CPU time 3.96 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:51 PM PDT 24
Peak memory 200316 kb
Host smart-8b4779a7-9215-4fac-886a-fd9ef87e86ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254971503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.254971503
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1361774484
Short name T598
Test name
Test status
Simulation time 443441754 ps
CPU time 4.01 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 215860 kb
Host smart-abb48d53-f1c1-494f-a1b4-ca7e54d79168
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361774484 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1361774484
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.385835206
Short name T127
Test name
Test status
Simulation time 44717967 ps
CPU time 0.81 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 199980 kb
Host smart-d97a1dab-2189-449e-bcf4-9b2926ec8f99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385835206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.385835206
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1959624548
Short name T539
Test name
Test status
Simulation time 49327270 ps
CPU time 0.59 seconds
Started Aug 14 04:46:42 PM PDT 24
Finished Aug 14 04:46:43 PM PDT 24
Peak memory 195280 kb
Host smart-744f456a-341a-46d6-af0e-edb95b0f1f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959624548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1959624548
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3963162832
Short name T578
Test name
Test status
Simulation time 183259429 ps
CPU time 2.15 seconds
Started Aug 14 04:46:41 PM PDT 24
Finished Aug 14 04:46:43 PM PDT 24
Peak memory 200272 kb
Host smart-1a79ecee-f730-409d-8e9b-0d00e8e6f32f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963162832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3963162832
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.191504491
Short name T77
Test name
Test status
Simulation time 47587386 ps
CPU time 2.53 seconds
Started Aug 14 04:46:44 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 200348 kb
Host smart-00c82592-de34-4396-a8aa-31f108fd110f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191504491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.191504491
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2364429607
Short name T76
Test name
Test status
Simulation time 35826816 ps
CPU time 1.11 seconds
Started Aug 14 04:46:42 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 200000 kb
Host smart-e13a420e-8ec8-49e3-aeb1-b839e7129271
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364429607 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2364429607
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2171807306
Short name T556
Test name
Test status
Simulation time 78969986 ps
CPU time 0.8 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 199784 kb
Host smart-7478ed22-2eba-43be-9a49-fa47826579c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171807306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2171807306
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.196998955
Short name T582
Test name
Test status
Simulation time 58350264 ps
CPU time 0.6 seconds
Started Aug 14 04:46:45 PM PDT 24
Finished Aug 14 04:46:45 PM PDT 24
Peak memory 195144 kb
Host smart-29c449d7-4e85-4612-97a8-cda281b74df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196998955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.196998955
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.236550713
Short name T636
Test name
Test status
Simulation time 825811055 ps
CPU time 2.44 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 200292 kb
Host smart-e9bd9f98-f983-435a-b201-5f87a7b06bd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236550713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.236550713
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.577741885
Short name T609
Test name
Test status
Simulation time 1048123042 ps
CPU time 1.95 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 200200 kb
Host smart-e6912fce-47b0-4d8a-9cba-7f0cb37a5269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577741885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.577741885
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1893103179
Short name T148
Test name
Test status
Simulation time 152881542 ps
CPU time 3.19 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 200364 kb
Host smart-cc1c53ca-6263-4e6f-87bf-157177608de1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893103179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1893103179
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1472350683
Short name T586
Test name
Test status
Simulation time 155793976 ps
CPU time 1.31 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 200000 kb
Host smart-1b5e1d2e-dd4a-41a4-9d67-57c31673a4ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472350683 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1472350683
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3213108479
Short name T535
Test name
Test status
Simulation time 20099292 ps
CPU time 0.71 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 198164 kb
Host smart-238231cc-e83f-4e1e-b897-07c75051e70b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213108479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3213108479
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1006837639
Short name T594
Test name
Test status
Simulation time 78632749 ps
CPU time 0.59 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:52 PM PDT 24
Peak memory 195220 kb
Host smart-496e950f-fad4-42e4-bc79-b79c48f011dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006837639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1006837639
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1336540430
Short name T640
Test name
Test status
Simulation time 141770816 ps
CPU time 1.74 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 200360 kb
Host smart-306f2836-e609-4ba2-b15d-5c25ccdb8eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336540430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1336540430
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1476925590
Short name T105
Test name
Test status
Simulation time 196362053 ps
CPU time 2.11 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 200336 kb
Host smart-135b23c2-7e55-48cb-8a98-b1ca03293a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476925590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1476925590
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2990255283
Short name T156
Test name
Test status
Simulation time 1171870336 ps
CPU time 4.84 seconds
Started Aug 14 04:46:54 PM PDT 24
Finished Aug 14 04:46:58 PM PDT 24
Peak memory 200264 kb
Host smart-8ed26914-a215-4b8b-b64e-8bd35a074f47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990255283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2990255283
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4144628984
Short name T106
Test name
Test status
Simulation time 109286392 ps
CPU time 1.09 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 199968 kb
Host smart-fd227921-e785-4c39-bdb1-b953ef5ff600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144628984 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.4144628984
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1588361704
Short name T134
Test name
Test status
Simulation time 48986486 ps
CPU time 0.83 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 199648 kb
Host smart-1175d985-afba-4b94-8a68-1a7dce42e8ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588361704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1588361704
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1562336369
Short name T564
Test name
Test status
Simulation time 34305586 ps
CPU time 0.61 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 195336 kb
Host smart-502e7ad4-4c00-4b2d-97f5-2d23cc54387f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562336369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1562336369
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.492149852
Short name T139
Test name
Test status
Simulation time 86590484 ps
CPU time 1.2 seconds
Started Aug 14 04:46:45 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 200076 kb
Host smart-4324724e-e477-4d62-abba-c335476e7e40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492149852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.492149852
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.829867360
Short name T542
Test name
Test status
Simulation time 320914369 ps
CPU time 3.65 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 200160 kb
Host smart-6f497aad-aa5f-472c-a01f-f0def1126f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829867360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.829867360
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.296076854
Short name T624
Test name
Test status
Simulation time 1461761684 ps
CPU time 4.27 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 200216 kb
Host smart-0aae60b0-a51c-4489-aee7-fe9301d9a1ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296076854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.296076854
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.4281553463
Short name T543
Test name
Test status
Simulation time 223074523 ps
CPU time 2.72 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:46 PM PDT 24
Peak memory 208548 kb
Host smart-a12cb223-3087-42e8-acc1-fe913beb95bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281553463 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.4281553463
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.445608080
Short name T552
Test name
Test status
Simulation time 21052569 ps
CPU time 0.74 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:08 PM PDT 24
Peak memory 198684 kb
Host smart-940130e4-4ca3-49b7-9e0b-413da0e685e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445608080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.445608080
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1017494480
Short name T607
Test name
Test status
Simulation time 12378731 ps
CPU time 0.6 seconds
Started Aug 14 04:46:41 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 195284 kb
Host smart-3f2a934f-9075-4f0e-8581-694033cb2097
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017494480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1017494480
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3151013463
Short name T581
Test name
Test status
Simulation time 209235109 ps
CPU time 1.15 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 200228 kb
Host smart-af8a8fc5-5fa2-43e0-bd6d-6f8be45a19f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151013463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3151013463
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1412595929
Short name T75
Test name
Test status
Simulation time 175441627 ps
CPU time 1.68 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:46:57 PM PDT 24
Peak memory 200208 kb
Host smart-ac5a526c-5576-4006-b2d5-017c41c17b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412595929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1412595929
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3556028640
Short name T70
Test name
Test status
Simulation time 736878850 ps
CPU time 3.41 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:47:03 PM PDT 24
Peak memory 200212 kb
Host smart-7f5af575-4a23-4c95-a4a2-071d5da53a66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556028640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3556028640
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3720574053
Short name T625
Test name
Test status
Simulation time 633626491 ps
CPU time 3.26 seconds
Started Aug 14 04:46:23 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 199216 kb
Host smart-4e05c9c2-a474-4255-a927-ea87390b5546
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720574053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3720574053
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1512253693
Short name T129
Test name
Test status
Simulation time 453633893 ps
CPU time 5.09 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:30 PM PDT 24
Peak memory 200236 kb
Host smart-ed64186a-5df7-4ec3-8428-9022f8ee62e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512253693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1512253693
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1826669747
Short name T122
Test name
Test status
Simulation time 153615659 ps
CPU time 0.99 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 199928 kb
Host smart-b35431c3-e90f-4e06-ab93-285cf6410a13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826669747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1826669747
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3681382393
Short name T604
Test name
Test status
Simulation time 344643991 ps
CPU time 2.72 seconds
Started Aug 14 04:46:35 PM PDT 24
Finished Aug 14 04:46:38 PM PDT 24
Peak memory 208548 kb
Host smart-f0983369-d1b9-411d-81be-55db67b18909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681382393 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3681382393
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1486002895
Short name T120
Test name
Test status
Simulation time 17589549 ps
CPU time 0.91 seconds
Started Aug 14 04:46:23 PM PDT 24
Finished Aug 14 04:46:24 PM PDT 24
Peak memory 200072 kb
Host smart-5762aa4d-8a1a-439c-98d1-887bc77dbeb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486002895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1486002895
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3125972636
Short name T592
Test name
Test status
Simulation time 25234713 ps
CPU time 0.59 seconds
Started Aug 14 04:46:32 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 195284 kb
Host smart-39698915-efc5-48c0-a2f8-3ca76e246cd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125972636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3125972636
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.853912235
Short name T653
Test name
Test status
Simulation time 212025306 ps
CPU time 1.83 seconds
Started Aug 14 04:46:16 PM PDT 24
Finished Aug 14 04:46:18 PM PDT 24
Peak memory 200328 kb
Host smart-26e8bef5-215c-4f82-a299-d21fde2976db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853912235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.853912235
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2629494627
Short name T559
Test name
Test status
Simulation time 887048100 ps
CPU time 4.17 seconds
Started Aug 14 04:46:13 PM PDT 24
Finished Aug 14 04:46:18 PM PDT 24
Peak memory 200284 kb
Host smart-bd026c89-3340-404b-b037-bc2fca82a7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629494627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2629494627
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2767269927
Short name T615
Test name
Test status
Simulation time 59229280 ps
CPU time 1.62 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:27 PM PDT 24
Peak memory 200284 kb
Host smart-9b6e4050-cc46-47ab-a992-48b1dca2abd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767269927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2767269927
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2884859616
Short name T569
Test name
Test status
Simulation time 31169204 ps
CPU time 0.57 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:46 PM PDT 24
Peak memory 195444 kb
Host smart-e9c537d9-242b-4bfe-a77f-fee0b2f6c2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884859616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2884859616
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3622521010
Short name T561
Test name
Test status
Simulation time 10216416 ps
CPU time 0.58 seconds
Started Aug 14 04:46:42 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 195240 kb
Host smart-c969e974-8ed9-4228-a3ba-d9ee2d17e9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622521010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3622521010
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.723405806
Short name T573
Test name
Test status
Simulation time 128592382 ps
CPU time 0.59 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 195176 kb
Host smart-faf9dd41-e2ed-4d65-8dfc-4f379bd3853e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723405806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.723405806
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.478741951
Short name T571
Test name
Test status
Simulation time 76434390 ps
CPU time 0.63 seconds
Started Aug 14 04:46:45 PM PDT 24
Finished Aug 14 04:46:45 PM PDT 24
Peak memory 195480 kb
Host smart-7d5e5bbc-7f18-4b2c-90c9-f48c01d703fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478741951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.478741951
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3602331802
Short name T591
Test name
Test status
Simulation time 26222746 ps
CPU time 0.59 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:52 PM PDT 24
Peak memory 195212 kb
Host smart-f469f66a-4140-487c-80bf-13c463c58119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602331802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3602331802
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2624778115
Short name T557
Test name
Test status
Simulation time 44634958 ps
CPU time 0.59 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 195260 kb
Host smart-bdc9a5ec-97aa-4e54-84a3-40e0e40304be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624778115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2624778115
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.615970345
Short name T565
Test name
Test status
Simulation time 63194504 ps
CPU time 0.61 seconds
Started Aug 14 04:46:54 PM PDT 24
Finished Aug 14 04:46:54 PM PDT 24
Peak memory 195236 kb
Host smart-0adca93b-3077-4c23-bfeb-a6dc15a18ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615970345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.615970345
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3910619882
Short name T595
Test name
Test status
Simulation time 11833050 ps
CPU time 0.57 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 195160 kb
Host smart-a6a52991-63a6-4f2e-b4a6-7a9fa2fbce05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910619882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3910619882
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.388823623
Short name T568
Test name
Test status
Simulation time 15937992 ps
CPU time 0.61 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 195340 kb
Host smart-85520a6f-d7a6-4fb1-8d4c-ac28fbdcc390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388823623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.388823623
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2033479551
Short name T550
Test name
Test status
Simulation time 41087743 ps
CPU time 0.64 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 195304 kb
Host smart-342dbc1d-89e2-437a-86a2-2a0b4ee1f3f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033479551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2033479551
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.493121444
Short name T602
Test name
Test status
Simulation time 713703623 ps
CPU time 3.23 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 200268 kb
Host smart-98134521-0b80-43fa-b7d1-ac2dfd473a39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493121444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.493121444
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.404391069
Short name T617
Test name
Test status
Simulation time 1085773426 ps
CPU time 5.84 seconds
Started Aug 14 04:46:42 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 200272 kb
Host smart-64704da8-3382-4790-bc15-fcfcc82674ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404391069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.404391069
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3273051401
Short name T124
Test name
Test status
Simulation time 73387910 ps
CPU time 0.75 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 198372 kb
Host smart-ea18d942-167b-4fe1-8493-e13ae85a1f11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273051401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3273051401
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1669369430
Short name T645
Test name
Test status
Simulation time 430377963 ps
CPU time 1.55 seconds
Started Aug 14 04:46:24 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 200320 kb
Host smart-6948fd7e-e08d-4cea-a234-470fc3b8dab3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669369430 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1669369430
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.454143147
Short name T123
Test name
Test status
Simulation time 100880641 ps
CPU time 0.83 seconds
Started Aug 14 04:46:24 PM PDT 24
Finished Aug 14 04:46:25 PM PDT 24
Peak memory 199380 kb
Host smart-ce0ecb19-f09d-4d02-9a90-009f46d0a6ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454143147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.454143147
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2434018944
Short name T590
Test name
Test status
Simulation time 13046129 ps
CPU time 0.59 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 195232 kb
Host smart-3ea461ff-62b3-463d-b7c6-d6e243650830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434018944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2434018944
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2091205088
Short name T138
Test name
Test status
Simulation time 229787122 ps
CPU time 1.18 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 198864 kb
Host smart-a7f6bf10-0395-448d-be7e-6bba25d96a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091205088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2091205088
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2590388874
Short name T555
Test name
Test status
Simulation time 130565483 ps
CPU time 3.46 seconds
Started Aug 14 04:46:33 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 200360 kb
Host smart-de045a62-3575-4e8b-af68-f4faebb41ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590388874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2590388874
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.964966428
Short name T150
Test name
Test status
Simulation time 125356206 ps
CPU time 2.85 seconds
Started Aug 14 04:46:39 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 200340 kb
Host smart-d63da068-7bf9-4b3b-80c5-e6db4c08bb42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964966428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.964966428
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3822469103
Short name T547
Test name
Test status
Simulation time 41983522 ps
CPU time 0.6 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:44 PM PDT 24
Peak memory 195184 kb
Host smart-fe1614d7-25a5-4bc0-a477-814519edc728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822469103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3822469103
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3164132850
Short name T560
Test name
Test status
Simulation time 13611905 ps
CPU time 0.6 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 195256 kb
Host smart-f7c90663-bfac-4f1c-bcd8-0a4c75dc22b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164132850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3164132850
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1537996033
Short name T630
Test name
Test status
Simulation time 20888929 ps
CPU time 0.56 seconds
Started Aug 14 04:46:56 PM PDT 24
Finished Aug 14 04:46:57 PM PDT 24
Peak memory 195140 kb
Host smart-a47b8ff3-80a1-4c66-90f0-bbd456c9bfda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537996033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1537996033
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1878372132
Short name T563
Test name
Test status
Simulation time 20662166 ps
CPU time 0.62 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 195416 kb
Host smart-f8029bd2-3b85-42bf-bf8b-3117f3a4ae0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878372132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1878372132
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1352335378
Short name T544
Test name
Test status
Simulation time 11395976 ps
CPU time 0.57 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:46:58 PM PDT 24
Peak memory 195168 kb
Host smart-036c2325-987c-4f9b-ade2-8fedfa4358c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352335378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1352335378
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2457629084
Short name T558
Test name
Test status
Simulation time 37318478 ps
CPU time 0.62 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:46:54 PM PDT 24
Peak memory 195348 kb
Host smart-3e52111f-50b4-42fb-9423-3cb176a52b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457629084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2457629084
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1674179516
Short name T600
Test name
Test status
Simulation time 12969849 ps
CPU time 0.59 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 195272 kb
Host smart-036344c1-ce69-432f-bbca-b242db5da6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674179516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1674179516
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1647578153
Short name T631
Test name
Test status
Simulation time 12061438 ps
CPU time 0.59 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:46:56 PM PDT 24
Peak memory 195260 kb
Host smart-703d0500-1352-44c3-83a8-8597744f354a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647578153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1647578153
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2693035229
Short name T597
Test name
Test status
Simulation time 42050109 ps
CPU time 0.59 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 195060 kb
Host smart-01526434-e160-4ef6-b481-3bd5ab7becdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693035229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2693035229
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2633480598
Short name T534
Test name
Test status
Simulation time 34974545 ps
CPU time 0.65 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:46:59 PM PDT 24
Peak memory 195452 kb
Host smart-4a3fa26a-9b4a-4298-a730-8026e1fb15b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633480598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2633480598
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3999399590
Short name T126
Test name
Test status
Simulation time 196591473 ps
CPU time 3.49 seconds
Started Aug 14 04:46:35 PM PDT 24
Finished Aug 14 04:46:39 PM PDT 24
Peak memory 200120 kb
Host smart-28952d06-bee2-44ec-9419-b3cf5f9c607b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999399590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3999399590
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2068279214
Short name T623
Test name
Test status
Simulation time 1411270798 ps
CPU time 15.54 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:41 PM PDT 24
Peak memory 200156 kb
Host smart-159104d1-eb3f-402f-8dbf-9ed68c5d3d3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068279214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2068279214
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3881128501
Short name T119
Test name
Test status
Simulation time 146274600 ps
CPU time 1 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 199916 kb
Host smart-aa6b04df-d3d8-4d18-814f-d9ecf97b0d23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881128501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3881128501
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.978339087
Short name T642
Test name
Test status
Simulation time 366245638 ps
CPU time 2.3 seconds
Started Aug 14 04:46:20 PM PDT 24
Finished Aug 14 04:46:22 PM PDT 24
Peak memory 200356 kb
Host smart-c0e3d998-6dcf-478b-bdcb-41c650284596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978339087 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.978339087
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.994366724
Short name T616
Test name
Test status
Simulation time 59258585 ps
CPU time 0.93 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 199992 kb
Host smart-dbc86d4f-65c9-4b6c-add0-17f0196dd18b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994366724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.994366724
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3041257331
Short name T538
Test name
Test status
Simulation time 55684993 ps
CPU time 0.65 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 195276 kb
Host smart-a081a2f9-c90c-437f-b3b3-8175b1a8fdf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041257331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3041257331
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.204596865
Short name T613
Test name
Test status
Simulation time 48522974 ps
CPU time 2.15 seconds
Started Aug 14 04:46:33 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 200368 kb
Host smart-af20789b-2797-4c2f-b2a9-2ce0e6ea3e28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204596865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.204596865
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1915055022
Short name T601
Test name
Test status
Simulation time 550394119 ps
CPU time 2.68 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:39 PM PDT 24
Peak memory 200100 kb
Host smart-07997a6a-1a27-412b-a4da-07a6d090084a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915055022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1915055022
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3643420627
Short name T155
Test name
Test status
Simulation time 1266395567 ps
CPU time 3.04 seconds
Started Aug 14 04:46:23 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 200364 kb
Host smart-cbdf1746-3e51-4588-a1f5-210d4a6a043c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643420627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3643420627
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3514617816
Short name T635
Test name
Test status
Simulation time 13544946 ps
CPU time 0.64 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 195304 kb
Host smart-f1ddda47-8eff-45e8-967f-c8648c257261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514617816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3514617816
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3072308727
Short name T648
Test name
Test status
Simulation time 20272924 ps
CPU time 0.58 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 195188 kb
Host smart-c8e329f8-6106-463c-8298-6d2fda053254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072308727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3072308727
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1249517680
Short name T540
Test name
Test status
Simulation time 19109202 ps
CPU time 0.62 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 195396 kb
Host smart-2d6d79c7-a535-406b-8ea7-400435dfcf68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249517680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1249517680
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4146639944
Short name T567
Test name
Test status
Simulation time 13424210 ps
CPU time 0.61 seconds
Started Aug 14 04:47:17 PM PDT 24
Finished Aug 14 04:47:18 PM PDT 24
Peak memory 195132 kb
Host smart-050f9c80-68c5-4cec-b48e-d6014780b429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146639944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4146639944
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3671333988
Short name T633
Test name
Test status
Simulation time 27200769 ps
CPU time 0.57 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:52 PM PDT 24
Peak memory 195320 kb
Host smart-8bb9e5c6-f5e1-4325-bb5e-3510f64a71b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671333988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3671333988
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2785057947
Short name T549
Test name
Test status
Simulation time 16143325 ps
CPU time 0.62 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 04:47:03 PM PDT 24
Peak memory 195248 kb
Host smart-2be35b4b-0ea1-4481-9613-825a2c11560d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785057947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2785057947
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1838803767
Short name T632
Test name
Test status
Simulation time 46580290 ps
CPU time 0.59 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:00 PM PDT 24
Peak memory 195160 kb
Host smart-894cd139-301d-4f46-ac19-a7a422422cda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838803767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1838803767
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.948416267
Short name T588
Test name
Test status
Simulation time 56720995 ps
CPU time 0.63 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:47:35 PM PDT 24
Peak memory 195348 kb
Host smart-68bd7628-c1cd-4e13-8e13-d77b83173679
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948416267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.948416267
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4232453145
Short name T620
Test name
Test status
Simulation time 14709656 ps
CPU time 0.63 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 195036 kb
Host smart-d6c9bf3c-9125-4543-8abf-790b6f36773e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232453145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4232453145
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2891881249
Short name T647
Test name
Test status
Simulation time 11559928 ps
CPU time 0.61 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:46:56 PM PDT 24
Peak memory 195136 kb
Host smart-be392faf-7c73-4fd2-996e-3520df78f9d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891881249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2891881249
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.817962898
Short name T587
Test name
Test status
Simulation time 90477668 ps
CPU time 2.39 seconds
Started Aug 14 04:46:29 PM PDT 24
Finished Aug 14 04:46:31 PM PDT 24
Peak memory 200352 kb
Host smart-7207e41e-72f9-48bc-8f55-d691fab70e6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817962898 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.817962898
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2782042535
Short name T132
Test name
Test status
Simulation time 50983176 ps
CPU time 0.93 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 200004 kb
Host smart-8bffc1da-039a-47a9-ab16-c74d4d179435
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782042535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2782042535
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1578664808
Short name T579
Test name
Test status
Simulation time 16134782 ps
CPU time 0.64 seconds
Started Aug 14 04:46:26 PM PDT 24
Finished Aug 14 04:46:26 PM PDT 24
Peak memory 195392 kb
Host smart-926a53c0-a42c-44bb-8e9b-e44d6d477f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578664808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1578664808
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2088026237
Short name T651
Test name
Test status
Simulation time 81857935 ps
CPU time 2.17 seconds
Started Aug 14 04:46:28 PM PDT 24
Finished Aug 14 04:46:30 PM PDT 24
Peak memory 200184 kb
Host smart-55b4b40c-7a3f-40b6-a095-9a63f6227f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088026237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2088026237
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3714309041
Short name T553
Test name
Test status
Simulation time 260684807 ps
CPU time 3.66 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:38 PM PDT 24
Peak memory 200320 kb
Host smart-0c8b08c9-2531-42fe-b79a-fbc405f89cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714309041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3714309041
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3257860707
Short name T72
Test name
Test status
Simulation time 85395874 ps
CPU time 1.93 seconds
Started Aug 14 04:46:46 PM PDT 24
Finished Aug 14 04:46:48 PM PDT 24
Peak memory 200340 kb
Host smart-54d91cb7-2599-4af7-9462-141f2f609db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257860707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3257860707
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3750668431
Short name T546
Test name
Test status
Simulation time 255399654 ps
CPU time 1.73 seconds
Started Aug 14 04:46:33 PM PDT 24
Finished Aug 14 04:46:35 PM PDT 24
Peak memory 200248 kb
Host smart-c67101a1-0d59-4fbf-a5c8-f63eae1bd7fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750668431 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3750668431
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.384123287
Short name T128
Test name
Test status
Simulation time 99330944 ps
CPU time 0.86 seconds
Started Aug 14 04:46:19 PM PDT 24
Finished Aug 14 04:46:20 PM PDT 24
Peak memory 199972 kb
Host smart-1da7bcc9-a339-4a22-b25a-8f936f4ef69d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384123287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.384123287
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1877296062
Short name T626
Test name
Test status
Simulation time 11085509 ps
CPU time 0.62 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:32 PM PDT 24
Peak memory 195136 kb
Host smart-9a89de17-46ee-4138-b57e-12ffa9982ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877296062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1877296062
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.803163861
Short name T611
Test name
Test status
Simulation time 123774729 ps
CPU time 1.7 seconds
Started Aug 14 04:46:34 PM PDT 24
Finished Aug 14 04:46:36 PM PDT 24
Peak memory 200292 kb
Host smart-f40177d5-a473-4582-906a-e8e77b77d884
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803163861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.803163861
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1434306973
Short name T618
Test name
Test status
Simulation time 130097161 ps
CPU time 1.78 seconds
Started Aug 14 04:46:32 PM PDT 24
Finished Aug 14 04:46:34 PM PDT 24
Peak memory 200156 kb
Host smart-f3ac598f-545f-4bbb-8b0c-49c4c2792f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434306973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1434306973
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3214096583
Short name T548
Test name
Test status
Simulation time 76543241 ps
CPU time 2.03 seconds
Started Aug 14 04:46:40 PM PDT 24
Finished Aug 14 04:46:42 PM PDT 24
Peak memory 200316 kb
Host smart-cd4d4bbd-6a1a-40a7-bdd1-1b90101befdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214096583 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3214096583
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.533981712
Short name T537
Test name
Test status
Simulation time 22705199 ps
CPU time 0.77 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 198600 kb
Host smart-da70c533-c44d-46f5-a97a-7901bc64efc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533981712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.533981712
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3561067032
Short name T545
Test name
Test status
Simulation time 13980311 ps
CPU time 0.57 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:32 PM PDT 24
Peak memory 195176 kb
Host smart-42d903ed-859e-4799-9b12-235db75b23d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561067032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3561067032
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.962157182
Short name T140
Test name
Test status
Simulation time 54821679 ps
CPU time 1.21 seconds
Started Aug 14 04:46:30 PM PDT 24
Finished Aug 14 04:46:31 PM PDT 24
Peak memory 199144 kb
Host smart-a46b1c56-3a01-4b8b-a8d7-4bc2a3e41baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962157182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.962157182
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2427245350
Short name T644
Test name
Test status
Simulation time 49401260 ps
CPU time 1.6 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 200332 kb
Host smart-5af0fcaf-2ddf-4c92-af9a-f669de2dfaec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427245350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2427245350
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3806900204
Short name T576
Test name
Test status
Simulation time 294525769 ps
CPU time 1.82 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:50 PM PDT 24
Peak memory 200292 kb
Host smart-d2a79cd6-097d-4e48-a054-66eea29fba36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806900204 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3806900204
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3909851481
Short name T131
Test name
Test status
Simulation time 56371997 ps
CPU time 0.68 seconds
Started Aug 14 04:46:45 PM PDT 24
Finished Aug 14 04:46:46 PM PDT 24
Peak memory 198320 kb
Host smart-edd046b7-dfbf-44c8-99cb-f5ed57c9b25f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909851481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3909851481
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3668555786
Short name T639
Test name
Test status
Simulation time 15781347 ps
CPU time 0.6 seconds
Started Aug 14 04:46:37 PM PDT 24
Finished Aug 14 04:46:38 PM PDT 24
Peak memory 195220 kb
Host smart-940d6b19-6a98-4317-aa1b-bccebe2b31c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668555786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3668555786
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.509226426
Short name T135
Test name
Test status
Simulation time 2163038481 ps
CPU time 2.13 seconds
Started Aug 14 04:46:31 PM PDT 24
Finished Aug 14 04:46:33 PM PDT 24
Peak memory 200488 kb
Host smart-2a9d7e1a-70ee-44a9-abc7-c78547e63853
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509226426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.509226426
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3099345083
Short name T79
Test name
Test status
Simulation time 66955052 ps
CPU time 1.6 seconds
Started Aug 14 04:46:35 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 200208 kb
Host smart-1595b46a-dbbb-4f51-90de-29c190fc35dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099345083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3099345083
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1844324637
Short name T619
Test name
Test status
Simulation time 305843769 ps
CPU time 2.78 seconds
Started Aug 14 04:46:44 PM PDT 24
Finished Aug 14 04:46:47 PM PDT 24
Peak memory 200284 kb
Host smart-b9cf69b9-5716-42f2-b385-1fb1c4b62e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844324637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1844324637
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3358416574
Short name T575
Test name
Test status
Simulation time 163709880 ps
CPU time 1.28 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:46:53 PM PDT 24
Peak memory 200396 kb
Host smart-9d14ac36-db4e-4407-ac8d-2f2824c4986e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358416574 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3358416574
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1867809741
Short name T583
Test name
Test status
Simulation time 36965412 ps
CPU time 0.7 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:46:49 PM PDT 24
Peak memory 198644 kb
Host smart-8dd95eb9-392e-481a-9099-a124bb51675d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867809741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1867809741
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.46091044
Short name T541
Test name
Test status
Simulation time 14573258 ps
CPU time 0.65 seconds
Started Aug 14 04:46:36 PM PDT 24
Finished Aug 14 04:46:37 PM PDT 24
Peak memory 195260 kb
Host smart-701deb63-ac8c-46be-bb49-a30cbd381eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46091044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.46091044
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3952827679
Short name T614
Test name
Test status
Simulation time 706000353 ps
CPU time 2.19 seconds
Started Aug 14 04:46:50 PM PDT 24
Finished Aug 14 04:46:52 PM PDT 24
Peak memory 200284 kb
Host smart-64c586cf-be02-4151-bdd3-d7ac26c98b6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952827679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3952827679
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1763477997
Short name T649
Test name
Test status
Simulation time 133421303 ps
CPU time 2.85 seconds
Started Aug 14 04:46:43 PM PDT 24
Finished Aug 14 04:46:46 PM PDT 24
Peak memory 200268 kb
Host smart-3fca5f5e-8136-4334-ba36-dc50f9767153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763477997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1763477997
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2773578264
Short name T596
Test name
Test status
Simulation time 87244429 ps
CPU time 2.8 seconds
Started Aug 14 04:46:25 PM PDT 24
Finished Aug 14 04:46:28 PM PDT 24
Peak memory 200192 kb
Host smart-984d1ca5-cd12-495e-bc4a-2395949fd027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773578264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2773578264
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.661074787
Short name T361
Test name
Test status
Simulation time 30258036 ps
CPU time 0.59 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:01 PM PDT 24
Peak memory 195692 kb
Host smart-ca9ad822-d40a-4bfa-a1ab-0be19a46cd92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661074787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.661074787
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2531070937
Short name T166
Test name
Test status
Simulation time 942319700 ps
CPU time 48.28 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:48 PM PDT 24
Peak memory 200608 kb
Host smart-8d38364d-29ff-44a3-ac5b-542c92991b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531070937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2531070937
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1937917828
Short name T346
Test name
Test status
Simulation time 3152709183 ps
CPU time 51.22 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 200780 kb
Host smart-8a9a0541-7539-475b-b77e-8974d9f1ce69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937917828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1937917828
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.888806646
Short name T360
Test name
Test status
Simulation time 2521058611 ps
CPU time 319.42 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:20:17 PM PDT 24
Peak memory 604060 kb
Host smart-2d185670-0da5-472e-9f54-c8d34534e533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888806646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.888806646
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4288702518
Short name T188
Test name
Test status
Simulation time 14558470713 ps
CPU time 244.49 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:19:02 PM PDT 24
Peak memory 200796 kb
Host smart-2725cb5b-80db-4ff6-8e9e-fa8117e3ff89
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288702518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4288702518
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1309982608
Short name T236
Test name
Test status
Simulation time 3268146971 ps
CPU time 29.98 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 200760 kb
Host smart-776b9e2b-02a3-4ba3-b14a-d4ad80394d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309982608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1309982608
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1115830962
Short name T61
Test name
Test status
Simulation time 82230187 ps
CPU time 0.97 seconds
Started Aug 14 05:14:56 PM PDT 24
Finished Aug 14 05:14:57 PM PDT 24
Peak memory 220056 kb
Host smart-7ea33637-5b78-47a6-8fcd-566555f01c5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115830962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1115830962
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3701449668
Short name T508
Test name
Test status
Simulation time 418780385 ps
CPU time 9.91 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:10 PM PDT 24
Peak memory 200684 kb
Host smart-3402eed8-1609-4109-9257-32b3f0a13954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701449668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3701449668
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3387659791
Short name T527
Test name
Test status
Simulation time 222393747728 ps
CPU time 1018.66 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:31:57 PM PDT 24
Peak memory 504800 kb
Host smart-500ab6f4-659b-413e-86f8-5b9e31133fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387659791 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3387659791
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.623052425
Short name T189
Test name
Test status
Simulation time 16541286028 ps
CPU time 70.78 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 200760 kb
Host smart-6c2c7d06-5318-4564-9bd7-c5150443e1c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=623052425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.623052425
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3330483203
Short name T289
Test name
Test status
Simulation time 10297319799 ps
CPU time 63.64 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:03 PM PDT 24
Peak memory 200768 kb
Host smart-6024cbe9-4f20-434b-a092-1050a01d0d20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3330483203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3330483203
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2392352052
Short name T204
Test name
Test status
Simulation time 79211644196 ps
CPU time 89.77 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:29 PM PDT 24
Peak memory 200748 kb
Host smart-6c1f6465-aab7-4d2c-92f8-b998411ad623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2392352052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2392352052
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2325750351
Short name T473
Test name
Test status
Simulation time 105013518693 ps
CPU time 649.11 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 200684 kb
Host smart-26980aca-ccda-46ff-81b5-47fca5a9eded
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2325750351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2325750351
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3088603026
Short name T178
Test name
Test status
Simulation time 78704070154 ps
CPU time 2229.59 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:52:11 PM PDT 24
Peak memory 216236 kb
Host smart-a6298023-cc13-4667-832f-eac365e367e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3088603026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3088603026
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3857130474
Short name T277
Test name
Test status
Simulation time 172126564218 ps
CPU time 2279.38 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:53:01 PM PDT 24
Peak memory 216232 kb
Host smart-d43a53f4-224a-4314-a12b-7f6b882157c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3857130474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3857130474
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1978600974
Short name T241
Test name
Test status
Simulation time 10189583158 ps
CPU time 72.56 seconds
Started Aug 14 05:14:56 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 200880 kb
Host smart-e3098fce-0186-4c3e-ac08-bfb5a134fccd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978600974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1978600974
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.844728259
Short name T164
Test name
Test status
Simulation time 602981905 ps
CPU time 29.97 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:29 PM PDT 24
Peak memory 200604 kb
Host smart-d4c1606d-a28e-43c3-91db-dc0bb30f5cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844728259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.844728259
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3203907107
Short name T176
Test name
Test status
Simulation time 1079422718 ps
CPU time 196.22 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:18:14 PM PDT 24
Peak memory 611648 kb
Host smart-ed2f7bd7-2351-42d5-adb5-7806ddd12f42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3203907107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3203907107
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3180383260
Short name T425
Test name
Test status
Simulation time 598519821 ps
CPU time 10.55 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:10 PM PDT 24
Peak memory 200584 kb
Host smart-8e27ca7f-3789-45f7-ba8c-2673df84f192
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180383260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3180383260
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3809537858
Short name T422
Test name
Test status
Simulation time 399559971 ps
CPU time 5.84 seconds
Started Aug 14 05:14:57 PM PDT 24
Finished Aug 14 05:15:03 PM PDT 24
Peak memory 200680 kb
Host smart-d10b87dd-a3ce-459e-b185-2414fe6ea7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809537858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3809537858
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2296089741
Short name T63
Test name
Test status
Simulation time 457435901 ps
CPU time 1.03 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:01 PM PDT 24
Peak memory 220032 kb
Host smart-ceca8cec-16b6-4dfa-bdd0-87ab04835257
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296089741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2296089741
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2607890171
Short name T333
Test name
Test status
Simulation time 3350079434 ps
CPU time 10.32 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:10 PM PDT 24
Peak memory 200748 kb
Host smart-88dda157-5221-4880-8cae-cc0d1fd75acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607890171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2607890171
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.471881436
Short name T190
Test name
Test status
Simulation time 238214756395 ps
CPU time 1554.79 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:40:55 PM PDT 24
Peak memory 696952 kb
Host smart-b7368869-7ddd-4478-b342-770b398e9c62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471881436 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.471881436
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.295414343
Short name T11
Test name
Test status
Simulation time 3683180248 ps
CPU time 198.59 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:18:17 PM PDT 24
Peak memory 209020 kb
Host smart-9fc86da9-ad64-4d64-8d63-6aa3e049f2f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295414343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.295414343
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.312855310
Short name T401
Test name
Test status
Simulation time 25980878213 ps
CPU time 71.71 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:16:10 PM PDT 24
Peak memory 200748 kb
Host smart-3acaea35-c2dd-42b3-b69d-2f1823a70d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=312855310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.312855310
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.4115171033
Short name T423
Test name
Test status
Simulation time 5010075418 ps
CPU time 92.56 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:16:31 PM PDT 24
Peak memory 200768 kb
Host smart-4eacb8f1-0f80-4e26-b9c5-0e3a9c6c9084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4115171033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.4115171033
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.758840451
Short name T31
Test name
Test status
Simulation time 2883111956 ps
CPU time 107.01 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:47 PM PDT 24
Peak memory 200808 kb
Host smart-66b0a4da-478a-499c-8408-6c033636c14f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=758840451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.758840451
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1319412724
Short name T239
Test name
Test status
Simulation time 11296886645 ps
CPU time 594.44 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:24:52 PM PDT 24
Peak memory 200716 kb
Host smart-1cc5711e-ea78-4620-a516-da81830ce9d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1319412724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1319412724
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.345770296
Short name T311
Test name
Test status
Simulation time 291251602702 ps
CPU time 2500.9 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:56:41 PM PDT 24
Peak memory 216172 kb
Host smart-0fed8067-43f3-47c6-a2a4-3fdb45302207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=345770296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.345770296
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.812058021
Short name T524
Test name
Test status
Simulation time 796205321116 ps
CPU time 2494.69 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:56:36 PM PDT 24
Peak memory 216144 kb
Host smart-a038255b-9668-4435-9c0b-e2ede12aa631
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=812058021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.812058021
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1748319628
Short name T491
Test name
Test status
Simulation time 4157717742 ps
CPU time 61.06 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:16:02 PM PDT 24
Peak memory 200724 kb
Host smart-b58600bd-ea42-40ff-a6d1-18db9b6d4cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748319628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1748319628
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.402838055
Short name T370
Test name
Test status
Simulation time 54075544 ps
CPU time 0.58 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 197336 kb
Host smart-4bece0e8-a24c-4893-8baf-2de8429049a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402838055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.402838055
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.598226014
Short name T23
Test name
Test status
Simulation time 1622215987 ps
CPU time 47.66 seconds
Started Aug 14 05:15:25 PM PDT 24
Finished Aug 14 05:16:13 PM PDT 24
Peak memory 200668 kb
Host smart-d78f2754-b69e-404c-8aa2-abbfeed2cafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=598226014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.598226014
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.452408638
Short name T193
Test name
Test status
Simulation time 1891046560 ps
CPU time 31.33 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:15:57 PM PDT 24
Peak memory 200692 kb
Host smart-916bbb25-d97e-4f74-b553-e10512159dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452408638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.452408638
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1864688172
Short name T84
Test name
Test status
Simulation time 1864991260 ps
CPU time 348.86 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:21:15 PM PDT 24
Peak memory 593948 kb
Host smart-1239684c-fdcd-4cb8-b996-2ad3bde637f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864688172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1864688172
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.44006781
Short name T209
Test name
Test status
Simulation time 1245368892 ps
CPU time 51.27 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:16:17 PM PDT 24
Peak memory 200740 kb
Host smart-8a463945-dbca-4a0c-95be-4963a96c64fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44006781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.44006781
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.857809244
Short name T429
Test name
Test status
Simulation time 29556030238 ps
CPU time 142.63 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:17:49 PM PDT 24
Peak memory 200892 kb
Host smart-72ae2559-10c3-4672-a16c-0dc39d0f195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857809244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.857809244
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1445965727
Short name T407
Test name
Test status
Simulation time 2369579500 ps
CPU time 13.66 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:15:40 PM PDT 24
Peak memory 200756 kb
Host smart-cd9db1df-569d-4ebe-a0c1-8347a60181ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445965727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1445965727
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2863344188
Short name T118
Test name
Test status
Simulation time 3576151660 ps
CPU time 47.22 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:16:14 PM PDT 24
Peak memory 200960 kb
Host smart-23ba488c-5efd-4e9c-b111-f9721182bb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863344188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2863344188
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1094079949
Short name T449
Test name
Test status
Simulation time 34464215 ps
CPU time 0.57 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:37 PM PDT 24
Peak memory 196756 kb
Host smart-4723ae66-003c-4e5e-90cc-f134ab58db4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094079949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1094079949
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1677295674
Short name T15
Test name
Test status
Simulation time 5487822860 ps
CPU time 74.42 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200660 kb
Host smart-f7dff8d9-d8a4-4582-95ab-5d31e4b78339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1677295674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1677295674
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.312283032
Short name T389
Test name
Test status
Simulation time 5824180453 ps
CPU time 32.18 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 200744 kb
Host smart-e2fce595-d9b1-480e-a720-50fe9cfdc720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312283032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.312283032
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2043325402
Short name T40
Test name
Test status
Simulation time 11710154872 ps
CPU time 570.99 seconds
Started Aug 14 05:15:40 PM PDT 24
Finished Aug 14 05:25:11 PM PDT 24
Peak memory 674484 kb
Host smart-b9034924-3015-4996-82ee-aca285c3f083
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043325402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2043325402
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.527815572
Short name T516
Test name
Test status
Simulation time 45464788846 ps
CPU time 200.25 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:18:58 PM PDT 24
Peak memory 200768 kb
Host smart-dd20a00b-575b-4cce-8f81-eee92b38407b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527815572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.527815572
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1631405947
Short name T232
Test name
Test status
Simulation time 1456591481 ps
CPU time 39.35 seconds
Started Aug 14 05:15:46 PM PDT 24
Finished Aug 14 05:16:26 PM PDT 24
Peak memory 200728 kb
Host smart-40a26bb6-cdaa-42cd-8f6f-f72505e3fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631405947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1631405947
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3240945123
Short name T268
Test name
Test status
Simulation time 780448131 ps
CPU time 13.65 seconds
Started Aug 14 05:15:25 PM PDT 24
Finished Aug 14 05:15:39 PM PDT 24
Peak memory 200604 kb
Host smart-fa374311-6f3d-44db-8d8a-096ff3073e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240945123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3240945123
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2181656315
Short name T250
Test name
Test status
Simulation time 578030426828 ps
CPU time 2416.48 seconds
Started Aug 14 05:15:35 PM PDT 24
Finished Aug 14 05:55:52 PM PDT 24
Peak memory 778392 kb
Host smart-91e939fd-52ea-4cf9-83de-efa843e3040e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181656315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2181656315
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1560948801
Short name T260
Test name
Test status
Simulation time 3744543031 ps
CPU time 140.13 seconds
Started Aug 14 05:15:40 PM PDT 24
Finished Aug 14 05:18:00 PM PDT 24
Peak memory 200696 kb
Host smart-b44d6088-7bfa-4d0e-afd5-83d8e2036dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560948801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1560948801
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2557162547
Short name T221
Test name
Test status
Simulation time 18646068 ps
CPU time 0.55 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:38 PM PDT 24
Peak memory 196340 kb
Host smart-07047d91-4580-4097-8a6f-0474d98d6b80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557162547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2557162547
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3345247313
Short name T261
Test name
Test status
Simulation time 826360594 ps
CPU time 46.52 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:16:22 PM PDT 24
Peak memory 200696 kb
Host smart-1babdea9-42f9-4e03-8f5c-bbf30937512e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345247313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3345247313
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3274066313
Short name T88
Test name
Test status
Simulation time 14908407413 ps
CPU time 50.87 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:30 PM PDT 24
Peak memory 200728 kb
Host smart-1af4412c-7e38-4a68-995e-488c91a11acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274066313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3274066313
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.568888332
Short name T169
Test name
Test status
Simulation time 1765280390 ps
CPU time 294.81 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:20:32 PM PDT 24
Peak memory 656532 kb
Host smart-25e6c038-e2f7-4bec-8e57-987220cbbfb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568888332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.568888332
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.784105768
Short name T54
Test name
Test status
Simulation time 13005520176 ps
CPU time 87.19 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:17:03 PM PDT 24
Peak memory 200740 kb
Host smart-36cd2fb9-a73b-46b9-a492-121de1566d06
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784105768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.784105768
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_smoke.430342830
Short name T532
Test name
Test status
Simulation time 148617039 ps
CPU time 1.82 seconds
Started Aug 14 05:15:34 PM PDT 24
Finished Aug 14 05:15:36 PM PDT 24
Peak memory 200572 kb
Host smart-c7ecf46c-e104-4a8c-a5d0-250e7e75a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430342830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.430342830
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3298697491
Short name T117
Test name
Test status
Simulation time 813815567 ps
CPU time 45.13 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:16:21 PM PDT 24
Peak memory 200684 kb
Host smart-a54bb350-ea64-4ba1-8833-c4e80de89eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298697491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3298697491
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3830508098
Short name T318
Test name
Test status
Simulation time 21054504 ps
CPU time 0.57 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 195744 kb
Host smart-b03faa56-b527-41a4-89df-88461886c7a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830508098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3830508098
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2198173319
Short name T434
Test name
Test status
Simulation time 7351417408 ps
CPU time 85.58 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:17:03 PM PDT 24
Peak memory 200724 kb
Host smart-c675c369-50af-4fe9-bcad-1a3e6bef5248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198173319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2198173319
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2357829159
Short name T253
Test name
Test status
Simulation time 8048855864 ps
CPU time 648.07 seconds
Started Aug 14 05:15:41 PM PDT 24
Finished Aug 14 05:26:29 PM PDT 24
Peak memory 738164 kb
Host smart-7459cb3d-f12e-4c9c-b3fd-5ea83c11271a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2357829159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2357829159
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3208613127
Short name T396
Test name
Test status
Simulation time 8069549319 ps
CPU time 128.21 seconds
Started Aug 14 05:15:43 PM PDT 24
Finished Aug 14 05:17:51 PM PDT 24
Peak memory 200764 kb
Host smart-369f9151-55f4-4414-9b34-e6eedd75e7ef
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208613127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3208613127
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2876545834
Short name T64
Test name
Test status
Simulation time 4719953075 ps
CPU time 138.91 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:18:09 PM PDT 24
Peak memory 208952 kb
Host smart-62240687-c438-4b9f-8eba-e539da03a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876545834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2876545834
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2629230315
Short name T270
Test name
Test status
Simulation time 258520547 ps
CPU time 11.98 seconds
Started Aug 14 05:15:35 PM PDT 24
Finished Aug 14 05:15:47 PM PDT 24
Peak memory 200700 kb
Host smart-dc45d1a0-4942-426f-bdc0-e03c8bde0971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629230315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2629230315
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1406305025
Short name T279
Test name
Test status
Simulation time 157353539586 ps
CPU time 5071.02 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 06:40:08 PM PDT 24
Peak memory 882640 kb
Host smart-0b386268-d73b-485b-8471-315c1dfa77d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406305025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1406305025
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1888293532
Short name T317
Test name
Test status
Simulation time 4120490444 ps
CPU time 35.63 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:14 PM PDT 24
Peak memory 200732 kb
Host smart-876e5560-e3b6-4c57-9ab8-99a95bfca788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888293532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1888293532
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3420242926
Short name T280
Test name
Test status
Simulation time 26373950 ps
CPU time 0.6 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:15:38 PM PDT 24
Peak memory 196776 kb
Host smart-80b4e7f5-2200-4d51-8a2a-f85d8813d0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420242926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3420242926
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.806801338
Short name T488
Test name
Test status
Simulation time 718676140 ps
CPU time 40.4 seconds
Started Aug 14 05:15:51 PM PDT 24
Finished Aug 14 05:16:32 PM PDT 24
Peak memory 200708 kb
Host smart-45aca338-e664-4a00-9653-d3f28920ca0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=806801338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.806801338
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.603126444
Short name T21
Test name
Test status
Simulation time 865176906 ps
CPU time 12.38 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 200708 kb
Host smart-a2fddb3b-63a7-4dc8-bf3d-d72bd2aefc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603126444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.603126444
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1605946138
Short name T329
Test name
Test status
Simulation time 12767707941 ps
CPU time 1160.92 seconds
Started Aug 14 05:15:34 PM PDT 24
Finished Aug 14 05:34:55 PM PDT 24
Peak memory 754092 kb
Host smart-4b5e6039-7659-4314-a445-4a699f4114ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1605946138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1605946138
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3854249148
Short name T226
Test name
Test status
Simulation time 5544196792 ps
CPU time 100.42 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:17:22 PM PDT 24
Peak memory 200752 kb
Host smart-9e9b4bd7-4d13-406e-b765-9b29fa039a97
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854249148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3854249148
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1277114607
Short name T316
Test name
Test status
Simulation time 87362464781 ps
CPU time 144.12 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:18:02 PM PDT 24
Peak memory 200812 kb
Host smart-5d2f11f0-7ef4-4ab3-bfff-bbd6cd600d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277114607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1277114607
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2188291882
Short name T431
Test name
Test status
Simulation time 113383271 ps
CPU time 5.44 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 200748 kb
Host smart-5cb411c9-8f32-4e69-b9e8-586c4fc01417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188291882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2188291882
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3649223043
Short name T41
Test name
Test status
Simulation time 2991850005 ps
CPU time 241.93 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:19:39 PM PDT 24
Peak memory 451788 kb
Host smart-547dfe64-1992-4478-9758-16bc110feb32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649223043 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3649223043
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.474505877
Short name T323
Test name
Test status
Simulation time 5613011881 ps
CPU time 74.39 seconds
Started Aug 14 05:15:35 PM PDT 24
Finished Aug 14 05:16:50 PM PDT 24
Peak memory 200736 kb
Host smart-fd5a4470-2aca-4343-b690-5ca8f3aaf50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474505877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.474505877
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3999433206
Short name T265
Test name
Test status
Simulation time 17852140 ps
CPU time 0.56 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:15:39 PM PDT 24
Peak memory 195604 kb
Host smart-ec3d5757-cc94-495f-98d4-8c7ff5fe616c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999433206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3999433206
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3576557745
Short name T293
Test name
Test status
Simulation time 2683174154 ps
CPU time 79.92 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:17:02 PM PDT 24
Peak memory 200740 kb
Host smart-fd1e260b-ffcf-4c26-ac75-d01131b8dafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576557745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3576557745
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1380919289
Short name T210
Test name
Test status
Simulation time 5396781593 ps
CPU time 19.36 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:57 PM PDT 24
Peak memory 200660 kb
Host smart-32c6cce0-ee71-4958-b555-a2da8504ba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380919289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1380919289
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1154944914
Short name T480
Test name
Test status
Simulation time 4450160679 ps
CPU time 937.22 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:31:16 PM PDT 24
Peak memory 708316 kb
Host smart-63c78b85-7cc6-4fc3-9582-185e8fd55b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1154944914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1154944914
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1086135984
Short name T102
Test name
Test status
Simulation time 513255701 ps
CPU time 31.08 seconds
Started Aug 14 05:15:36 PM PDT 24
Finished Aug 14 05:16:07 PM PDT 24
Peak memory 200660 kb
Host smart-b0cbe9ce-6a48-4242-ac2c-b56068d0c231
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086135984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1086135984
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.58318957
Short name T168
Test name
Test status
Simulation time 10733703632 ps
CPU time 25.02 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:03 PM PDT 24
Peak memory 200752 kb
Host smart-7ece2edc-bacd-464b-800e-69c7f0f86cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58318957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.58318957
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2991494870
Short name T338
Test name
Test status
Simulation time 3616673676 ps
CPU time 15.61 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:52 PM PDT 24
Peak memory 200740 kb
Host smart-11cd88db-4ac7-42b8-a457-ce848ae84d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991494870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2991494870
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.789361304
Short name T287
Test name
Test status
Simulation time 48676690223 ps
CPU time 471.83 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:23:29 PM PDT 24
Peak memory 217136 kb
Host smart-6ea5982e-2391-49b7-b3b8-c0312dcc1b66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789361304 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.789361304
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.831317845
Short name T345
Test name
Test status
Simulation time 5118695400 ps
CPU time 131.32 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:17:54 PM PDT 24
Peak memory 200748 kb
Host smart-2d215070-3295-4b5f-9b44-42e03111fb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831317845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.831317845
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3518951384
Short name T520
Test name
Test status
Simulation time 29850867 ps
CPU time 0.59 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:15:39 PM PDT 24
Peak memory 196768 kb
Host smart-1dafdd37-9bc8-4e4c-adf1-9d271bccb369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518951384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3518951384
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.429370390
Short name T315
Test name
Test status
Simulation time 1831226248 ps
CPU time 63.27 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:16:45 PM PDT 24
Peak memory 200680 kb
Host smart-4eab27e0-3d64-46e7-9090-c04a0940cc0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=429370390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.429370390
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1189784915
Short name T384
Test name
Test status
Simulation time 21459841875 ps
CPU time 41.63 seconds
Started Aug 14 05:15:39 PM PDT 24
Finished Aug 14 05:16:21 PM PDT 24
Peak memory 200632 kb
Host smart-2d3dd474-76e0-481b-8724-f9174d28fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189784915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1189784915
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4209018955
Short name T456
Test name
Test status
Simulation time 782565713 ps
CPU time 57.39 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:36 PM PDT 24
Peak memory 252600 kb
Host smart-888baef3-f356-4bf8-a48e-8c20b83371e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209018955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4209018955
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2437281937
Short name T248
Test name
Test status
Simulation time 2051556120 ps
CPU time 104.63 seconds
Started Aug 14 05:15:41 PM PDT 24
Finished Aug 14 05:17:25 PM PDT 24
Peak memory 200660 kb
Host smart-91f83141-2975-4815-8490-fcc365a66621
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437281937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2437281937
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_smoke.1166715394
Short name T231
Test name
Test status
Simulation time 822072487 ps
CPU time 7.85 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 200692 kb
Host smart-f2be131f-cf52-491c-b079-d43fd7dcd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166715394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1166715394
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1073407549
Short name T519
Test name
Test status
Simulation time 66765548722 ps
CPU time 2695.47 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 06:00:34 PM PDT 24
Peak memory 815276 kb
Host smart-fbbd7575-a8da-42be-a4db-772aad76d1bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073407549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1073407549
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1173864232
Short name T465
Test name
Test status
Simulation time 1948632201 ps
CPU time 99.04 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:17:16 PM PDT 24
Peak memory 200676 kb
Host smart-b84769c0-2b08-48c9-b0ad-b02393fd947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173864232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1173864232
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3234310959
Short name T413
Test name
Test status
Simulation time 12983758 ps
CPU time 0.61 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:15:38 PM PDT 24
Peak memory 197436 kb
Host smart-8381d379-ceac-46ac-83b3-12f95407aa10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234310959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3234310959
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2465942421
Short name T207
Test name
Test status
Simulation time 1041204086 ps
CPU time 46.93 seconds
Started Aug 14 05:15:41 PM PDT 24
Finished Aug 14 05:16:28 PM PDT 24
Peak memory 200632 kb
Host smart-3470a70f-a8e2-441d-a536-05ddc393da3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465942421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2465942421
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3386628747
Short name T461
Test name
Test status
Simulation time 801823507 ps
CPU time 43.09 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:21 PM PDT 24
Peak memory 200700 kb
Host smart-7b820163-6868-4b43-88b9-a644c5ece113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386628747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3386628747
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1001841294
Short name T69
Test name
Test status
Simulation time 2154791673 ps
CPU time 78.36 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:57 PM PDT 24
Peak memory 268048 kb
Host smart-16aba071-e7d2-47ca-b99f-ac2cf5330267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001841294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1001841294
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3387688058
Short name T80
Test name
Test status
Simulation time 363862129 ps
CPU time 18.19 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:16:00 PM PDT 24
Peak memory 200680 kb
Host smart-fbee3b5f-5977-4eea-9c16-f6579b760d81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387688058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3387688058
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.193637090
Short name T418
Test name
Test status
Simulation time 1251266798 ps
CPU time 67.16 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:16:45 PM PDT 24
Peak memory 200580 kb
Host smart-984bfa70-ca88-43c8-a27b-4af1e5432fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193637090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.193637090
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.805863736
Short name T405
Test name
Test status
Simulation time 367322678 ps
CPU time 4.71 seconds
Started Aug 14 05:15:38 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 200696 kb
Host smart-541eb216-6209-4b75-b281-9437adb060ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805863736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.805863736
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2434361806
Short name T59
Test name
Test status
Simulation time 25658812917 ps
CPU time 718.22 seconds
Started Aug 14 05:15:37 PM PDT 24
Finished Aug 14 05:27:35 PM PDT 24
Peak memory 667344 kb
Host smart-3cb0210e-2074-4219-8ad1-3bd157bb2887
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434361806 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2434361806
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2944793961
Short name T452
Test name
Test status
Simulation time 3360501865 ps
CPU time 60.53 seconds
Started Aug 14 05:15:39 PM PDT 24
Finished Aug 14 05:16:40 PM PDT 24
Peak memory 200756 kb
Host smart-6582371e-2645-47b6-8625-f553ac886363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944793961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2944793961
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3698500354
Short name T339
Test name
Test status
Simulation time 42634400 ps
CPU time 0.6 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 197428 kb
Host smart-224ef577-f8ef-43bc-b19b-68b68c9e4e5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698500354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3698500354
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2249217790
Short name T374
Test name
Test status
Simulation time 289089900 ps
CPU time 7.92 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 200644 kb
Host smart-48cb9572-2ee6-4cb1-ba81-070c99141d6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249217790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2249217790
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4144666445
Short name T327
Test name
Test status
Simulation time 6144727960 ps
CPU time 30.85 seconds
Started Aug 14 05:15:42 PM PDT 24
Finished Aug 14 05:16:13 PM PDT 24
Peak memory 208948 kb
Host smart-b0fe9822-0900-4405-a5b7-83a4a643ce8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144666445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4144666445
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_error.2240877019
Short name T489
Test name
Test status
Simulation time 38412287197 ps
CPU time 173.54 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:18:40 PM PDT 24
Peak memory 200712 kb
Host smart-e276244c-dfc0-43e6-a972-e69ad0b66f36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240877019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2240877019
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3571697781
Short name T523
Test name
Test status
Simulation time 58302070 ps
CPU time 3.59 seconds
Started Aug 14 05:15:39 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 200640 kb
Host smart-bc97ed6c-c4c6-4ac7-9662-627f492d47ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571697781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3571697781
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.382196662
Short name T184
Test name
Test status
Simulation time 475210471 ps
CPU time 9 seconds
Started Aug 14 05:15:35 PM PDT 24
Finished Aug 14 05:15:44 PM PDT 24
Peak memory 200696 kb
Host smart-86bf5526-2d5e-44d2-9fa1-6bb5cdc8ecb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382196662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.382196662
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3631456967
Short name T367
Test name
Test status
Simulation time 22905176813 ps
CPU time 300.86 seconds
Started Aug 14 05:15:46 PM PDT 24
Finished Aug 14 05:20:47 PM PDT 24
Peak memory 217100 kb
Host smart-d32f0d7e-d5f8-4514-8826-057a3dd1dc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631456967 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3631456967
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1912300301
Short name T455
Test name
Test status
Simulation time 6199322473 ps
CPU time 37.27 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:16:25 PM PDT 24
Peak memory 200756 kb
Host smart-6df26142-c40a-4fd9-a828-f0c3b4e5199d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912300301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1912300301
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1324974400
Short name T403
Test name
Test status
Simulation time 14353719 ps
CPU time 0.6 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 196408 kb
Host smart-d4a451b1-211d-4280-83c3-9901f8330d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324974400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1324974400
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.824645485
Short name T208
Test name
Test status
Simulation time 945074950 ps
CPU time 52.17 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:16:39 PM PDT 24
Peak memory 200704 kb
Host smart-967a04f6-73df-4003-851c-33c49942ba5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824645485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.824645485
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1965803633
Short name T50
Test name
Test status
Simulation time 2762149675 ps
CPU time 38.64 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:16:26 PM PDT 24
Peak memory 200732 kb
Host smart-709b9166-122e-4dc7-9b3d-0c6fe91f03c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965803633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1965803633
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3914282841
Short name T492
Test name
Test status
Simulation time 1493194914 ps
CPU time 124.21 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:17:52 PM PDT 24
Peak memory 346696 kb
Host smart-08f41091-efb8-4dda-aa77-6720b3567159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914282841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3914282841
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.139097665
Short name T513
Test name
Test status
Simulation time 15245174810 ps
CPU time 60 seconds
Started Aug 14 05:15:46 PM PDT 24
Finished Aug 14 05:16:46 PM PDT 24
Peak memory 200652 kb
Host smart-08415fd0-e3f0-4b9d-b109-aa124714025c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139097665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.139097665
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.848890217
Short name T522
Test name
Test status
Simulation time 43362999948 ps
CPU time 98.74 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:17:28 PM PDT 24
Peak memory 216940 kb
Host smart-a6a561b4-acd5-4a2a-8f0d-4b5eb621e867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848890217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.848890217
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1569062006
Short name T464
Test name
Test status
Simulation time 163915040 ps
CPU time 5.28 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:54 PM PDT 24
Peak memory 200672 kb
Host smart-214c704d-7522-4234-b0e9-f2555aa8649b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569062006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1569062006
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3662900393
Short name T203
Test name
Test status
Simulation time 160773571763 ps
CPU time 493.27 seconds
Started Aug 14 05:15:46 PM PDT 24
Finished Aug 14 05:24:00 PM PDT 24
Peak memory 217144 kb
Host smart-c0182a3c-020a-48a0-939c-f5ef18b70858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662900393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3662900393
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2556064661
Short name T26
Test name
Test status
Simulation time 2735850725 ps
CPU time 49.91 seconds
Started Aug 14 05:15:48 PM PDT 24
Finished Aug 14 05:16:38 PM PDT 24
Peak memory 200824 kb
Host smart-cf4eaaea-2443-4fca-8f71-04234751cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556064661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2556064661
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1727080568
Short name T437
Test name
Test status
Simulation time 11657646 ps
CPU time 0.61 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:15:02 PM PDT 24
Peak memory 197436 kb
Host smart-e69fec04-7ea8-4a72-82da-9bed7d2f9a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727080568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1727080568
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1862078279
Short name T266
Test name
Test status
Simulation time 2774752203 ps
CPU time 81.9 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 200764 kb
Host smart-6683dcd9-dd88-49d9-8162-5b53c3488497
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1862078279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1862078279
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3344169213
Short name T356
Test name
Test status
Simulation time 2995882698 ps
CPU time 15.89 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:15:14 PM PDT 24
Peak memory 200708 kb
Host smart-abff0144-9ab5-460d-989d-f1e6f37948d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344169213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3344169213
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.522328680
Short name T351
Test name
Test status
Simulation time 1122427043 ps
CPU time 40.97 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:41 PM PDT 24
Peak memory 322408 kb
Host smart-06fc7db8-cec5-4824-8307-391aa02c554a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522328680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.522328680
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1227445661
Short name T450
Test name
Test status
Simulation time 3576905241 ps
CPU time 67.08 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:06 PM PDT 24
Peak memory 200732 kb
Host smart-a11ef83e-8a0d-4dd0-b0e4-3c29eb083227
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227445661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1227445661
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.280810389
Short name T198
Test name
Test status
Simulation time 28773875295 ps
CPU time 182.02 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:18:00 PM PDT 24
Peak memory 217200 kb
Host smart-844b9d68-5993-4dd0-8eab-1482fe4f2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280810389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.280810389
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4082601978
Short name T62
Test name
Test status
Simulation time 96010158 ps
CPU time 0.93 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:15:02 PM PDT 24
Peak memory 218964 kb
Host smart-b12da610-e572-416b-8489-55bc0d6a6712
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082601978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4082601978
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.237740445
Short name T271
Test name
Test status
Simulation time 166434918 ps
CPU time 3.06 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:03 PM PDT 24
Peak memory 200768 kb
Host smart-b6d8610c-2e35-4dfa-8aa4-6f275b07b8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237740445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.237740445
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1427634793
Short name T445
Test name
Test status
Simulation time 45274469491 ps
CPU time 448.56 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:22:29 PM PDT 24
Peak memory 357976 kb
Host smart-c31e7812-5224-4662-9545-98599c09cd97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427634793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1427634793
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2773010827
Short name T110
Test name
Test status
Simulation time 2668952966 ps
CPU time 42.38 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:42 PM PDT 24
Peak memory 200720 kb
Host smart-dbcfbb99-1cf6-4905-ae50-e6be5a047551
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2773010827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2773010827
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1683206308
Short name T439
Test name
Test status
Simulation time 8288215194 ps
CPU time 104.84 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:44 PM PDT 24
Peak memory 200648 kb
Host smart-72b333ca-adb5-402d-9749-c483ecc78882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683206308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1683206308
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1359732240
Short name T485
Test name
Test status
Simulation time 21035341478 ps
CPU time 71 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:16:13 PM PDT 24
Peak memory 200804 kb
Host smart-f1792f15-7f1f-47f1-82e6-7fa5e06e8113
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1359732240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1359732240
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3450680574
Short name T103
Test name
Test status
Simulation time 46463190939 ps
CPU time 604.24 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:25:03 PM PDT 24
Peak memory 200704 kb
Host smart-8bad2d64-7758-44dc-8b9f-726816f81580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3450680574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3450680574
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3487404083
Short name T502
Test name
Test status
Simulation time 278443190468 ps
CPU time 2524.18 seconds
Started Aug 14 05:14:58 PM PDT 24
Finished Aug 14 05:57:03 PM PDT 24
Peak memory 216344 kb
Host smart-16ca7c23-c6cf-4da2-be84-5f84c144809c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3487404083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3487404083
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2692479942
Short name T300
Test name
Test status
Simulation time 142518199762 ps
CPU time 2421.41 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:55:22 PM PDT 24
Peak memory 216776 kb
Host smart-9954fd11-b0ed-4c8a-8c2a-e7b8e44efde9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2692479942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2692479942
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.626405930
Short name T484
Test name
Test status
Simulation time 5380218028 ps
CPU time 69 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 200656 kb
Host smart-7dce13c3-6d9f-45fb-9456-da4471bdbb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626405930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.626405930
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1303522328
Short name T247
Test name
Test status
Simulation time 16913379 ps
CPU time 0.57 seconds
Started Aug 14 05:15:56 PM PDT 24
Finished Aug 14 05:15:56 PM PDT 24
Peak memory 196392 kb
Host smart-ac0b103a-1a2d-4fcf-a0d1-9e417acbf834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303522328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1303522328
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.852330602
Short name T402
Test name
Test status
Simulation time 105469315 ps
CPU time 6.11 seconds
Started Aug 14 05:15:47 PM PDT 24
Finished Aug 14 05:15:53 PM PDT 24
Peak memory 200564 kb
Host smart-fa4bf38f-6290-496a-90fd-71297baa4cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852330602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.852330602
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3461186549
Short name T481
Test name
Test status
Simulation time 2650190701 ps
CPU time 33.32 seconds
Started Aug 14 05:15:48 PM PDT 24
Finished Aug 14 05:16:21 PM PDT 24
Peak memory 200760 kb
Host smart-ed930fcc-0448-42cb-8dbb-1a9b34d1e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461186549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3461186549
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.834811264
Short name T281
Test name
Test status
Simulation time 2073474626 ps
CPU time 111.27 seconds
Started Aug 14 05:15:48 PM PDT 24
Finished Aug 14 05:17:39 PM PDT 24
Peak memory 555344 kb
Host smart-6406d3b4-6806-4eb3-95c8-ed0efe7a717d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834811264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.834811264
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1719475992
Short name T500
Test name
Test status
Simulation time 2221703068 ps
CPU time 40.97 seconds
Started Aug 14 05:15:46 PM PDT 24
Finished Aug 14 05:16:27 PM PDT 24
Peak memory 200680 kb
Host smart-0673b7bd-71eb-4db9-8293-dea4fc5ef514
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719475992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1719475992
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2864173142
Short name T340
Test name
Test status
Simulation time 22351823038 ps
CPU time 112.09 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:17:42 PM PDT 24
Peak memory 200684 kb
Host smart-7f57c3c2-7bc8-48fd-807a-2b36ac19f422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864173142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2864173142
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4229825742
Short name T172
Test name
Test status
Simulation time 833989265 ps
CPU time 9.23 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:58 PM PDT 24
Peak memory 200692 kb
Host smart-d9b4fdf1-c7b4-469c-85bc-ecd10c2f3969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229825742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4229825742
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.147301640
Short name T27
Test name
Test status
Simulation time 78806408355 ps
CPU time 1897.62 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:47:27 PM PDT 24
Peak memory 738740 kb
Host smart-ab410d3a-036e-47d1-987b-e138ac653975
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147301640 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.147301640
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1407165455
Short name T175
Test name
Test status
Simulation time 48340443017 ps
CPU time 143.28 seconds
Started Aug 14 05:15:48 PM PDT 24
Finished Aug 14 05:18:12 PM PDT 24
Peak memory 200780 kb
Host smart-e593e264-0789-46c6-a072-4884f842ca0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407165455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1407165455
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.603136237
Short name T220
Test name
Test status
Simulation time 12745617 ps
CPU time 0.6 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 196756 kb
Host smart-8ad1bb1c-c835-4724-afd4-08e84f6b4da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603136237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.603136237
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3376854211
Short name T306
Test name
Test status
Simulation time 1617421534 ps
CPU time 85.98 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:17:15 PM PDT 24
Peak memory 200688 kb
Host smart-9a0fa19a-dba1-4313-badc-fd5c90191e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376854211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3376854211
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3807823957
Short name T362
Test name
Test status
Simulation time 571528650 ps
CPU time 5.79 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:55 PM PDT 24
Peak memory 200592 kb
Host smart-e925d7a2-95cc-4ae2-bdfa-06568e654ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807823957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3807823957
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4210338912
Short name T515
Test name
Test status
Simulation time 16785106419 ps
CPU time 636.59 seconds
Started Aug 14 05:15:57 PM PDT 24
Finished Aug 14 05:26:34 PM PDT 24
Peak memory 701496 kb
Host smart-e960ca05-d117-49e4-b68b-a017392c02b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210338912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4210338912
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.843564487
Short name T173
Test name
Test status
Simulation time 258073902 ps
CPU time 4.05 seconds
Started Aug 14 05:15:50 PM PDT 24
Finished Aug 14 05:15:55 PM PDT 24
Peak memory 200544 kb
Host smart-a4dd959d-3674-4ea2-8c61-d9e14049ed3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843564487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.843564487
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2867018422
Short name T382
Test name
Test status
Simulation time 2266739148 ps
CPU time 33.2 seconds
Started Aug 14 05:15:48 PM PDT 24
Finished Aug 14 05:16:22 PM PDT 24
Peak memory 200748 kb
Host smart-05fc1538-99ce-41d7-86c7-e21ba1c34950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867018422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2867018422
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3788643123
Short name T7
Test name
Test status
Simulation time 257066475 ps
CPU time 6.26 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:15:56 PM PDT 24
Peak memory 200684 kb
Host smart-2eb241a4-c77a-4c25-8b90-bcc8137c58c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788643123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3788643123
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1158743737
Short name T30
Test name
Test status
Simulation time 7233907374 ps
CPU time 107.08 seconds
Started Aug 14 05:15:50 PM PDT 24
Finished Aug 14 05:17:38 PM PDT 24
Peak memory 200772 kb
Host smart-c60c76b1-00e7-47a8-bd62-b6dfb57d22f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158743737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1158743737
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.92909817
Short name T426
Test name
Test status
Simulation time 4591188093 ps
CPU time 14.6 seconds
Started Aug 14 05:15:50 PM PDT 24
Finished Aug 14 05:16:05 PM PDT 24
Peak memory 200780 kb
Host smart-7b04dba0-0bce-4de7-a1eb-2c04e54b98d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92909817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.92909817
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2948000919
Short name T310
Test name
Test status
Simulation time 48615899 ps
CPU time 0.61 seconds
Started Aug 14 05:15:52 PM PDT 24
Finished Aug 14 05:15:53 PM PDT 24
Peak memory 197428 kb
Host smart-30bff4c8-243b-4954-8cef-fabccc62c5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948000919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2948000919
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3157637248
Short name T6
Test name
Test status
Simulation time 5987750390 ps
CPU time 20.88 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:16:24 PM PDT 24
Peak memory 200732 kb
Host smart-43544b79-90d1-4f1f-a975-24a6811051cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157637248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3157637248
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.223644924
Short name T113
Test name
Test status
Simulation time 619900714 ps
CPU time 6.27 seconds
Started Aug 14 05:15:50 PM PDT 24
Finished Aug 14 05:15:57 PM PDT 24
Peak memory 200644 kb
Host smart-1603a5e9-f682-4ba7-9a30-5dd6da8c168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223644924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.223644924
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3627974783
Short name T476
Test name
Test status
Simulation time 25048729608 ps
CPU time 1104.11 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:34:13 PM PDT 24
Peak memory 748540 kb
Host smart-92f8419f-a822-4479-a9d8-c0781d857995
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627974783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3627974783
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.21197010
Short name T282
Test name
Test status
Simulation time 670340911 ps
CPU time 37.13 seconds
Started Aug 14 05:15:52 PM PDT 24
Finished Aug 14 05:16:29 PM PDT 24
Peak memory 200676 kb
Host smart-a70a0901-32bd-435a-9a73-4183bd8d60cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21197010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.21197010
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1006059999
Short name T376
Test name
Test status
Simulation time 2105631987 ps
CPU time 64.23 seconds
Started Aug 14 05:15:56 PM PDT 24
Finished Aug 14 05:17:00 PM PDT 24
Peak memory 200728 kb
Host smart-475d12ea-f8da-4e41-bc39-628f8b70d7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006059999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1006059999
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4260851558
Short name T341
Test name
Test status
Simulation time 482357259 ps
CPU time 8.53 seconds
Started Aug 14 05:15:57 PM PDT 24
Finished Aug 14 05:16:06 PM PDT 24
Peak memory 200700 kb
Host smart-439ff979-8b29-415a-8793-28ada0bef75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260851558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4260851558
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.591564058
Short name T457
Test name
Test status
Simulation time 37305022138 ps
CPU time 93.52 seconds
Started Aug 14 05:15:52 PM PDT 24
Finished Aug 14 05:17:26 PM PDT 24
Peak memory 200756 kb
Host smart-a7d49ae8-3fa8-498e-8fcb-955b7c1e6056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591564058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.591564058
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2709160054
Short name T192
Test name
Test status
Simulation time 14567427 ps
CPU time 0.61 seconds
Started Aug 14 05:16:01 PM PDT 24
Finished Aug 14 05:16:01 PM PDT 24
Peak memory 196388 kb
Host smart-475535aa-f4eb-4a99-9ebe-113ba6bf2eb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709160054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2709160054
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3072024343
Short name T322
Test name
Test status
Simulation time 6237858265 ps
CPU time 100.52 seconds
Started Aug 14 05:15:49 PM PDT 24
Finished Aug 14 05:17:30 PM PDT 24
Peak memory 209012 kb
Host smart-31d90839-42fa-4d4b-bf5f-7b7b74357d2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072024343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3072024343
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1076865720
Short name T160
Test name
Test status
Simulation time 2301026583 ps
CPU time 58.17 seconds
Started Aug 14 05:16:01 PM PDT 24
Finished Aug 14 05:16:59 PM PDT 24
Peak memory 200752 kb
Host smart-5e25a7c2-22bb-40b9-bcbe-0d1d9d7c6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076865720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1076865720
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.44910200
Short name T157
Test name
Test status
Simulation time 21201298115 ps
CPU time 739.02 seconds
Started Aug 14 05:16:01 PM PDT 24
Finished Aug 14 05:28:20 PM PDT 24
Peak memory 741080 kb
Host smart-546f5a82-cb4e-4444-aba9-964fbf434f0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=44910200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.44910200
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3579310977
Short name T391
Test name
Test status
Simulation time 8999875818 ps
CPU time 117.44 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:17:57 PM PDT 24
Peak memory 200784 kb
Host smart-01aec3af-059d-4f39-b25a-bc3f0a23afad
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579310977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3579310977
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2198878128
Short name T460
Test name
Test status
Simulation time 32091233427 ps
CPU time 52.4 seconds
Started Aug 14 05:15:56 PM PDT 24
Finished Aug 14 05:16:49 PM PDT 24
Peak memory 200716 kb
Host smart-0145cc87-2d4d-4fdf-8a7c-2eae274a3ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198878128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2198878128
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1795007027
Short name T512
Test name
Test status
Simulation time 3514645171 ps
CPU time 5.93 seconds
Started Aug 14 05:15:52 PM PDT 24
Finished Aug 14 05:15:58 PM PDT 24
Peak memory 200732 kb
Host smart-ca845714-f57f-4ae3-ae92-ebeb6b8f68ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795007027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1795007027
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2016487307
Short name T245
Test name
Test status
Simulation time 87079460424 ps
CPU time 7153.7 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 07:15:15 PM PDT 24
Peak memory 844512 kb
Host smart-6b86ded0-94f6-490f-bdab-ee37daeaca18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016487307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2016487307
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2103053034
Short name T115
Test name
Test status
Simulation time 10543960884 ps
CPU time 86.27 seconds
Started Aug 14 05:15:59 PM PDT 24
Finished Aug 14 05:17:25 PM PDT 24
Peak memory 200736 kb
Host smart-093514ad-4e47-4d1e-9887-050b31be625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103053034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2103053034
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.252526762
Short name T42
Test name
Test status
Simulation time 13967278 ps
CPU time 0.64 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:16:04 PM PDT 24
Peak memory 195732 kb
Host smart-59194b9c-1fb6-410f-a4f4-eb97888098ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252526762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.252526762
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3095244831
Short name T36
Test name
Test status
Simulation time 3514642964 ps
CPU time 54.58 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:16:55 PM PDT 24
Peak memory 200748 kb
Host smart-924dfb53-ee4a-44be-898e-9d6bde7c8332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095244831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3095244831
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1502121880
Short name T255
Test name
Test status
Simulation time 4539938373 ps
CPU time 63.06 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:17:03 PM PDT 24
Peak memory 209040 kb
Host smart-38a4abe6-e570-470d-bfea-8f1948eee425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502121880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1502121880
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2866600240
Short name T509
Test name
Test status
Simulation time 5272864718 ps
CPU time 920.76 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:31:21 PM PDT 24
Peak memory 734896 kb
Host smart-ef906c6c-24d7-4362-9bff-2d365d6a8522
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866600240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2866600240
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2006875506
Short name T258
Test name
Test status
Simulation time 4958194126 ps
CPU time 103.53 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:17:44 PM PDT 24
Peak memory 200736 kb
Host smart-e61aeeee-199e-4c92-a0db-8fbc3f0ff2a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006875506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2006875506
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.334119534
Short name T229
Test name
Test status
Simulation time 5359537054 ps
CPU time 71.97 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:17:12 PM PDT 24
Peak memory 200856 kb
Host smart-707f82bb-5ca9-4e2d-9f7a-0feaa001069f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334119534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.334119534
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2041763471
Short name T108
Test name
Test status
Simulation time 885280246 ps
CPU time 6.76 seconds
Started Aug 14 05:16:01 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 200744 kb
Host smart-a3b03a62-46cb-43a7-8679-8e28c7d2fb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041763471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2041763471
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1897552181
Short name T39
Test name
Test status
Simulation time 37146785737 ps
CPU time 622.98 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:26:24 PM PDT 24
Peak memory 477488 kb
Host smart-95a54ee9-497b-4af6-8120-6ca01806a1e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897552181 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1897552181
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.4030599956
Short name T350
Test name
Test status
Simulation time 8492894946 ps
CPU time 103.54 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:17:44 PM PDT 24
Peak memory 200748 kb
Host smart-2fdfa591-8d2b-4bef-8bf1-4428c34fcfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030599956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.4030599956
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2929917222
Short name T486
Test name
Test status
Simulation time 45371728 ps
CPU time 0.6 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:16:04 PM PDT 24
Peak memory 196776 kb
Host smart-40887c15-fbc4-474c-8ab2-9bf9b2168123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929917222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2929917222
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.345667289
Short name T17
Test name
Test status
Simulation time 283637996 ps
CPU time 17.75 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 200672 kb
Host smart-ca156af5-08a2-4e20-8f10-c18c9a3911d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=345667289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.345667289
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1639109893
Short name T243
Test name
Test status
Simulation time 175290235 ps
CPU time 5.14 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:16:07 PM PDT 24
Peak memory 200704 kb
Host smart-18ed8d48-e527-4288-95a7-db115904e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639109893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1639109893
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.199361957
Short name T372
Test name
Test status
Simulation time 4486875439 ps
CPU time 153.57 seconds
Started Aug 14 05:16:00 PM PDT 24
Finished Aug 14 05:18:34 PM PDT 24
Peak memory 421412 kb
Host smart-3d5a3d65-c744-468b-b5b2-e0accd22f12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199361957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.199361957
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1040783788
Short name T259
Test name
Test status
Simulation time 2494602871 ps
CPU time 45.76 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:16:48 PM PDT 24
Peak memory 200716 kb
Host smart-bc21d43a-acaf-4ae2-9986-0d0db855eae9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040783788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1040783788
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.574319960
Short name T314
Test name
Test status
Simulation time 16018856015 ps
CPU time 102.38 seconds
Started Aug 14 05:16:01 PM PDT 24
Finished Aug 14 05:17:43 PM PDT 24
Peak memory 200816 kb
Host smart-16d0edf7-1d0e-437c-9952-efed215b6f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574319960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.574319960
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3008936510
Short name T495
Test name
Test status
Simulation time 97725166 ps
CPU time 1.34 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:17 PM PDT 24
Peak memory 200688 kb
Host smart-365fc2ae-a76e-483a-b1a3-2babb8e3d528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008936510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3008936510
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1502311616
Short name T90
Test name
Test status
Simulation time 666059289 ps
CPU time 9.33 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:16:12 PM PDT 24
Peak memory 200700 kb
Host smart-bd7de62c-3593-46b6-894d-5650ce8cc4ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502311616 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1502311616
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3307594229
Short name T116
Test name
Test status
Simulation time 9638799396 ps
CPU time 130.11 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:18:12 PM PDT 24
Peak memory 200756 kb
Host smart-63fdc013-6728-42c4-b107-7fbecc95cf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307594229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3307594229
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3956524366
Short name T263
Test name
Test status
Simulation time 12922035 ps
CPU time 0.6 seconds
Started Aug 14 05:16:04 PM PDT 24
Finished Aug 14 05:16:04 PM PDT 24
Peak memory 197404 kb
Host smart-7da42d8b-472f-4b6c-9619-02d683a28cb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956524366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3956524366
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.386810977
Short name T274
Test name
Test status
Simulation time 10499101957 ps
CPU time 61.09 seconds
Started Aug 14 05:16:04 PM PDT 24
Finished Aug 14 05:17:05 PM PDT 24
Peak memory 200768 kb
Host smart-007cc442-72ce-48f0-9a8d-5a3178e743da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386810977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.386810977
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2382079493
Short name T454
Test name
Test status
Simulation time 12270451549 ps
CPU time 52.15 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:16:55 PM PDT 24
Peak memory 200900 kb
Host smart-59ec8e47-8969-4849-aec7-9c610a3bf2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382079493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2382079493
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1174500897
Short name T82
Test name
Test status
Simulation time 2323651420 ps
CPU time 130.58 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:18:13 PM PDT 24
Peak memory 607968 kb
Host smart-db751ac2-2f0d-4072-bb3c-09b26a9758ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174500897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1174500897
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2257286065
Short name T55
Test name
Test status
Simulation time 39898281259 ps
CPU time 140.35 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:18:24 PM PDT 24
Peak memory 200788 kb
Host smart-9992a6e6-49ed-4c51-a620-e990ea13cdae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257286065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2257286065
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3238347710
Short name T313
Test name
Test status
Simulation time 33671424482 ps
CPU time 131.24 seconds
Started Aug 14 05:16:02 PM PDT 24
Finished Aug 14 05:18:14 PM PDT 24
Peak memory 200612 kb
Host smart-d4e05d43-4d1a-4a6c-9385-211e6f1da818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238347710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3238347710
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3652046283
Short name T35
Test name
Test status
Simulation time 1221227586 ps
CPU time 8.23 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:16:12 PM PDT 24
Peak memory 200696 kb
Host smart-57cda234-d23f-4995-8e79-91bd9fc960b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652046283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3652046283
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1578891772
Short name T510
Test name
Test status
Simulation time 77233760888 ps
CPU time 1310.43 seconds
Started Aug 14 05:16:04 PM PDT 24
Finished Aug 14 05:37:54 PM PDT 24
Peak memory 759944 kb
Host smart-fa187d0e-bd2e-458d-988b-f73e13629709
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578891772 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1578891772
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.794349121
Short name T409
Test name
Test status
Simulation time 3224494756 ps
CPU time 62.96 seconds
Started Aug 14 05:16:03 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 200756 kb
Host smart-e5b79aa4-f8e6-4e85-8ce0-2fabe3c8418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794349121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.794349121
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2747621385
Short name T335
Test name
Test status
Simulation time 53759059 ps
CPU time 0.54 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 195736 kb
Host smart-a04279ff-667f-4db8-b8cc-26c81e66132d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747621385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2747621385
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2643850235
Short name T201
Test name
Test status
Simulation time 2030210538 ps
CPU time 58.36 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:17:05 PM PDT 24
Peak memory 200812 kb
Host smart-177fb2e3-7b7a-4471-8e54-9c0ee2de2cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643850235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2643850235
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3652037608
Short name T493
Test name
Test status
Simulation time 312989860 ps
CPU time 16.24 seconds
Started Aug 14 05:16:19 PM PDT 24
Finished Aug 14 05:16:35 PM PDT 24
Peak memory 200712 kb
Host smart-7d45a371-e10a-4fe2-9d89-7d4445df82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652037608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3652037608
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1446607572
Short name T234
Test name
Test status
Simulation time 1800449620 ps
CPU time 60.97 seconds
Started Aug 14 05:16:10 PM PDT 24
Finished Aug 14 05:17:11 PM PDT 24
Peak memory 322792 kb
Host smart-21e48883-dfcd-487f-bfb7-8101f8256361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1446607572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1446607572
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.793406649
Short name T273
Test name
Test status
Simulation time 21782223801 ps
CPU time 134.15 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:18:35 PM PDT 24
Peak memory 200632 kb
Host smart-bb355a45-6020-4313-84c2-5115557a4054
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793406649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.793406649
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4227488268
Short name T497
Test name
Test status
Simulation time 36516276907 ps
CPU time 119.58 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:18:06 PM PDT 24
Peak memory 200732 kb
Host smart-0d5e8220-4de8-4dce-9746-028cb37b466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227488268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4227488268
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.548477308
Short name T16
Test name
Test status
Simulation time 137681174 ps
CPU time 6.39 seconds
Started Aug 14 05:16:04 PM PDT 24
Finished Aug 14 05:16:11 PM PDT 24
Peak memory 200688 kb
Host smart-8049667c-cb69-4797-a734-5df629b5fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548477308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.548477308
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.552586650
Short name T200
Test name
Test status
Simulation time 131004425205 ps
CPU time 390.18 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:22:40 PM PDT 24
Peak memory 200796 kb
Host smart-26230e4c-b8da-4777-9ee2-e4c5e40d5a90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552586650 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.552586650
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.4232835589
Short name T506
Test name
Test status
Simulation time 5275299383 ps
CPU time 90.5 seconds
Started Aug 14 05:16:07 PM PDT 24
Finished Aug 14 05:17:37 PM PDT 24
Peak memory 200756 kb
Host smart-c9aeea2e-b07e-46af-86f8-3aec7e7ecacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232835589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.4232835589
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.23541249
Short name T414
Test name
Test status
Simulation time 36386849 ps
CPU time 0.59 seconds
Started Aug 14 05:16:07 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 195748 kb
Host smart-cf041790-1dfd-4621-b0f3-e3ec4758ad9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23541249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.23541249
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4230756821
Short name T228
Test name
Test status
Simulation time 2900411755 ps
CPU time 41.67 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:16:48 PM PDT 24
Peak memory 200844 kb
Host smart-6257d54d-9842-45a7-b1fd-7e0604fd7c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4230756821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4230756821
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.812953896
Short name T420
Test name
Test status
Simulation time 1151372266 ps
CPU time 11.02 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 200696 kb
Host smart-1b6f561b-3b3c-458f-a3bb-fa0add4a4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812953896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.812953896
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.386282288
Short name T197
Test name
Test status
Simulation time 962027939 ps
CPU time 70.21 seconds
Started Aug 14 05:16:05 PM PDT 24
Finished Aug 14 05:17:15 PM PDT 24
Peak memory 338256 kb
Host smart-261c764a-569a-4dc6-a7d0-2538c04dd805
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386282288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.386282288
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.4254952113
Short name T290
Test name
Test status
Simulation time 9392841895 ps
CPU time 125.86 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:18:15 PM PDT 24
Peak memory 200796 kb
Host smart-bfe428d5-599d-4ec9-a25a-825351759315
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254952113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.4254952113
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1227657469
Short name T451
Test name
Test status
Simulation time 24623963268 ps
CPU time 87.53 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:17:34 PM PDT 24
Peak memory 200812 kb
Host smart-0b9a5b4a-ec2f-4d9d-8cc4-d1f0af713cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227657469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1227657469
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3361550834
Short name T385
Test name
Test status
Simulation time 746618076 ps
CPU time 10.72 seconds
Started Aug 14 05:16:08 PM PDT 24
Finished Aug 14 05:16:18 PM PDT 24
Peak memory 200636 kb
Host smart-5f6b3a6d-f500-49e7-ab44-fcb90a4058cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361550834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3361550834
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2863585519
Short name T417
Test name
Test status
Simulation time 144598064275 ps
CPU time 2827.73 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 06:03:15 PM PDT 24
Peak memory 768664 kb
Host smart-2b2272e4-58bd-467c-a73c-48dfac973eba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863585519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2863585519
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4167463462
Short name T298
Test name
Test status
Simulation time 13644824021 ps
CPU time 114.94 seconds
Started Aug 14 05:16:19 PM PDT 24
Finished Aug 14 05:18:14 PM PDT 24
Peak memory 200740 kb
Host smart-1701a929-547b-4ade-9ed0-4f8a2ed6a849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167463462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4167463462
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1657095299
Short name T468
Test name
Test status
Simulation time 27620215 ps
CPU time 0.57 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 195736 kb
Host smart-b7a8bec0-8fc6-4738-b754-65c8ca9382d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657095299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1657095299
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3726761756
Short name T264
Test name
Test status
Simulation time 152157046 ps
CPU time 8.35 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:16:15 PM PDT 24
Peak memory 200580 kb
Host smart-e4af1f1d-3678-4890-84e6-0b3f08064305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3726761756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3726761756
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1171533993
Short name T353
Test name
Test status
Simulation time 6383616100 ps
CPU time 29.87 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:16:39 PM PDT 24
Peak memory 200684 kb
Host smart-760b5894-4004-41f5-8583-910a9dc5df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171533993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1171533993
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2239174620
Short name T170
Test name
Test status
Simulation time 750449397 ps
CPU time 125.94 seconds
Started Aug 14 05:16:08 PM PDT 24
Finished Aug 14 05:18:14 PM PDT 24
Peak memory 417696 kb
Host smart-adb1b855-c176-4c1e-a0d7-e7561538410e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239174620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2239174620
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1029334526
Short name T67
Test name
Test status
Simulation time 19564728650 ps
CPU time 193.6 seconds
Started Aug 14 05:16:07 PM PDT 24
Finished Aug 14 05:19:21 PM PDT 24
Peak memory 200752 kb
Host smart-10e259af-78a4-43d7-aae1-09cfb29bd1e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029334526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1029334526
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2279380847
Short name T252
Test name
Test status
Simulation time 5949141787 ps
CPU time 94.68 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:17:41 PM PDT 24
Peak memory 217224 kb
Host smart-93d98bfd-270c-48d4-af79-65b80a7e9943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279380847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2279380847
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4004082145
Short name T53
Test name
Test status
Simulation time 136884532 ps
CPU time 3.78 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:16:13 PM PDT 24
Peak memory 200676 kb
Host smart-d78175c1-6eb7-4754-8f8a-b5315c4700c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004082145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4004082145
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3282588757
Short name T14
Test name
Test status
Simulation time 21234018594 ps
CPU time 1221.65 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:36:42 PM PDT 24
Peak memory 618996 kb
Host smart-cef66649-a87e-4757-bbed-9765c7aea50c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282588757 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3282588757
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2511547948
Short name T383
Test name
Test status
Simulation time 2414013261 ps
CPU time 43.34 seconds
Started Aug 14 05:16:19 PM PDT 24
Finished Aug 14 05:17:02 PM PDT 24
Peak memory 200756 kb
Host smart-7b76d3b7-914c-4ae0-84f9-723733b753aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511547948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2511547948
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3620903820
Short name T215
Test name
Test status
Simulation time 23203227 ps
CPU time 0.61 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:15:06 PM PDT 24
Peak memory 197456 kb
Host smart-e97b79e3-c896-4287-b9b2-a89ef3062987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620903820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3620903820
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2914456420
Short name T196
Test name
Test status
Simulation time 4177503480 ps
CPU time 59 seconds
Started Aug 14 05:15:01 PM PDT 24
Finished Aug 14 05:16:01 PM PDT 24
Peak memory 200744 kb
Host smart-f0f75ecf-3f6a-4318-869c-27f3351f08b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2914456420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2914456420
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2681831605
Short name T387
Test name
Test status
Simulation time 783231203 ps
CPU time 43.88 seconds
Started Aug 14 05:15:06 PM PDT 24
Finished Aug 14 05:15:50 PM PDT 24
Peak memory 200896 kb
Host smart-f6f6229d-9f69-4f6b-aacd-c5a4b62f3d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681831605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2681831605
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.612181875
Short name T187
Test name
Test status
Simulation time 20311065928 ps
CPU time 912.34 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:30:18 PM PDT 24
Peak memory 715376 kb
Host smart-546d5cd3-d415-403b-aa86-38c8c3716c3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=612181875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.612181875
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3833891999
Short name T1
Test name
Test status
Simulation time 10450573146 ps
CPU time 170.46 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:17:54 PM PDT 24
Peak memory 200744 kb
Host smart-23557873-9ca4-473a-90d4-eda8714bbed0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833891999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3833891999
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.678203132
Short name T305
Test name
Test status
Simulation time 342116589 ps
CPU time 20 seconds
Started Aug 14 05:14:59 PM PDT 24
Finished Aug 14 05:15:19 PM PDT 24
Peak memory 200672 kb
Host smart-8b526675-8b06-481d-9090-c71e6a3f213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678203132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.678203132
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1618418803
Short name T38
Test name
Test status
Simulation time 82325615 ps
CPU time 0.8 seconds
Started Aug 14 05:15:03 PM PDT 24
Finished Aug 14 05:15:04 PM PDT 24
Peak memory 219100 kb
Host smart-6bfb8af6-1223-459a-8a38-71974775b518
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618418803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1618418803
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4105653127
Short name T408
Test name
Test status
Simulation time 253039985 ps
CPU time 1.27 seconds
Started Aug 14 05:15:00 PM PDT 24
Finished Aug 14 05:15:02 PM PDT 24
Peak memory 200620 kb
Host smart-83379701-0102-4606-8454-758b8c9c4a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105653127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4105653127
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1100530103
Short name T472
Test name
Test status
Simulation time 11701514426 ps
CPU time 2126.77 seconds
Started Aug 14 05:15:07 PM PDT 24
Finished Aug 14 05:50:35 PM PDT 24
Peak memory 749308 kb
Host smart-0c7be5d2-77e6-4dda-a3ca-3154511dee33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100530103 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1100530103
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3982030210
Short name T9
Test name
Test status
Simulation time 8509540689 ps
CPU time 254.64 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:19:20 PM PDT 24
Peak memory 612560 kb
Host smart-d501fd86-15a6-481d-94a0-4f686e6160c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982030210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3982030210
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2862958045
Short name T98
Test name
Test status
Simulation time 9413822245 ps
CPU time 78.24 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:22 PM PDT 24
Peak memory 200756 kb
Host smart-45cab4c8-888c-4111-b33d-8b81f8dc7053
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2862958045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2862958045
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1772914591
Short name T324
Test name
Test status
Simulation time 24074133838 ps
CPU time 101.85 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:46 PM PDT 24
Peak memory 200772 kb
Host smart-a20ac81d-80ab-4f0f-8c0f-4e2010a6049e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1772914591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1772914591
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3667117201
Short name T410
Test name
Test status
Simulation time 11914069060 ps
CPU time 131.67 seconds
Started Aug 14 05:15:07 PM PDT 24
Finished Aug 14 05:17:18 PM PDT 24
Peak memory 200680 kb
Host smart-f13cc40e-3e9c-49bd-9909-c645294404f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3667117201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3667117201
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2587799606
Short name T474
Test name
Test status
Simulation time 10294212084 ps
CPU time 542.28 seconds
Started Aug 14 05:15:06 PM PDT 24
Finished Aug 14 05:24:09 PM PDT 24
Peak memory 200636 kb
Host smart-31677aa2-89bf-46fe-9bb2-400b9051f365
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2587799606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2587799606
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.289807999
Short name T319
Test name
Test status
Simulation time 136813048331 ps
CPU time 2447.79 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:55:54 PM PDT 24
Peak memory 216456 kb
Host smart-419ecd7b-d39e-43d3-8861-50837456c645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289807999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.289807999
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1443094423
Short name T498
Test name
Test status
Simulation time 94005234612 ps
CPU time 2270.79 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:52:57 PM PDT 24
Peak memory 216164 kb
Host smart-746dd006-7ca8-44e9-b35e-1e1eca0a3efe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1443094423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1443094423
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.4214606309
Short name T390
Test name
Test status
Simulation time 7171460038 ps
CPU time 101.7 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:16:47 PM PDT 24
Peak memory 200756 kb
Host smart-00a3e7ba-8fd7-44a9-98eb-f53251e8968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214606309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.4214606309
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3212468572
Short name T299
Test name
Test status
Simulation time 41348795 ps
CPU time 0.59 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:16:18 PM PDT 24
Peak memory 196772 kb
Host smart-1d61516c-9a5e-4ee3-a945-1666f1bc4ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212468572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3212468572
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4061033957
Short name T363
Test name
Test status
Simulation time 7196214184 ps
CPU time 109.34 seconds
Started Aug 14 05:16:07 PM PDT 24
Finished Aug 14 05:17:56 PM PDT 24
Peak memory 200756 kb
Host smart-f8c27a71-f825-402e-af6a-cb4356e8b29f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061033957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4061033957
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.243217887
Short name T225
Test name
Test status
Simulation time 2079445417 ps
CPU time 25.96 seconds
Started Aug 14 05:16:06 PM PDT 24
Finished Aug 14 05:16:32 PM PDT 24
Peak memory 200672 kb
Host smart-6308ec3d-718b-4e9b-881c-5f8d86296bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243217887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.243217887
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1158297865
Short name T399
Test name
Test status
Simulation time 25589862383 ps
CPU time 867.35 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 745024 kb
Host smart-0d044c2e-a395-4988-b907-f227d321523f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1158297865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1158297865
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.804779073
Short name T46
Test name
Test status
Simulation time 35337256464 ps
CPU time 38.72 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:55 PM PDT 24
Peak memory 200736 kb
Host smart-e4bbf657-445c-45fd-99dc-c54ba06ac66a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804779073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.804779073
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1732503596
Short name T463
Test name
Test status
Simulation time 2739051249 ps
CPU time 160.69 seconds
Started Aug 14 05:16:07 PM PDT 24
Finished Aug 14 05:18:48 PM PDT 24
Peak memory 200652 kb
Host smart-2488a1d3-22fb-4daa-98a1-450edee4287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732503596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1732503596
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2961541191
Short name T526
Test name
Test status
Simulation time 716285600 ps
CPU time 10.77 seconds
Started Aug 14 05:16:09 PM PDT 24
Finished Aug 14 05:16:20 PM PDT 24
Peak memory 200684 kb
Host smart-fc073748-9003-4e82-97d5-f521a784b6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961541191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2961541191
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2726178361
Short name T92
Test name
Test status
Simulation time 239727140411 ps
CPU time 632.43 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:26:50 PM PDT 24
Peak memory 216488 kb
Host smart-55fe8662-a8ba-46cf-b764-3f051825e33d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726178361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2726178361
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.133420668
Short name T143
Test name
Test status
Simulation time 1480826769 ps
CPU time 29.52 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:16:48 PM PDT 24
Peak memory 200716 kb
Host smart-28dc0524-7e1f-42c3-8428-c54fa64e1cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133420668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.133420668
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.4155358845
Short name T349
Test name
Test status
Simulation time 16195276 ps
CPU time 0.65 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:17 PM PDT 24
Peak memory 196756 kb
Host smart-d205e728-04b4-4562-8ca1-45860e198fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155358845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4155358845
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.811917103
Short name T181
Test name
Test status
Simulation time 290471860 ps
CPU time 15.42 seconds
Started Aug 14 05:16:26 PM PDT 24
Finished Aug 14 05:16:41 PM PDT 24
Peak memory 200688 kb
Host smart-4e2ee9fe-f90b-43e9-975c-3afdc218286b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811917103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.811917103
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.934491397
Short name T381
Test name
Test status
Simulation time 713158553 ps
CPU time 21.96 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:38 PM PDT 24
Peak memory 200640 kb
Host smart-549ec0dd-d2cb-40f9-acb2-97e0813c385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934491397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.934491397
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2978871425
Short name T66
Test name
Test status
Simulation time 2050006202 ps
CPU time 313.75 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:21:32 PM PDT 24
Peak memory 495396 kb
Host smart-9fedccb6-6154-4a4d-9a34-c0f326ab9cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2978871425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2978871425
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2106368200
Short name T471
Test name
Test status
Simulation time 12086712150 ps
CPU time 203.96 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:19:44 PM PDT 24
Peak memory 200712 kb
Host smart-2d208a09-b03a-4083-9cf4-2c5ada485c1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106368200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2106368200
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2382806445
Short name T326
Test name
Test status
Simulation time 14037971686 ps
CPU time 197.74 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:19:36 PM PDT 24
Peak memory 200852 kb
Host smart-9e643752-f6a4-4b5c-9e87-88d8a37981aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382806445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2382806445
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1182874615
Short name T223
Test name
Test status
Simulation time 527962852 ps
CPU time 11.99 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:16:32 PM PDT 24
Peak memory 200656 kb
Host smart-2f5dec31-bad9-405e-91d0-cc9156ee05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182874615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1182874615
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.926372885
Short name T145
Test name
Test status
Simulation time 77658116429 ps
CPU time 1956.49 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:48:54 PM PDT 24
Peak memory 790792 kb
Host smart-6948cece-47b9-47ee-81bd-b765ba0f70dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926372885 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.926372885
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1928467161
Short name T470
Test name
Test status
Simulation time 10135395950 ps
CPU time 65.81 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:17:22 PM PDT 24
Peak memory 200744 kb
Host smart-eb224ee6-fb2b-4dab-b9ab-a13590ede071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928467161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1928467161
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2059136831
Short name T235
Test name
Test status
Simulation time 15459084 ps
CPU time 0.57 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:16:18 PM PDT 24
Peak memory 197452 kb
Host smart-65931fce-837e-4570-955b-fa4ba8a388a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059136831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2059136831
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2427853694
Short name T504
Test name
Test status
Simulation time 1873457598 ps
CPU time 53.74 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:17:11 PM PDT 24
Peak memory 200748 kb
Host smart-1d21653c-c9d0-4adc-9535-c53e93c1e48b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427853694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2427853694
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1606255883
Short name T163
Test name
Test status
Simulation time 1815245284 ps
CPU time 62.06 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:17:23 PM PDT 24
Peak memory 200720 kb
Host smart-d4643b4d-aa26-43cf-beaf-aa74d1b08542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606255883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1606255883
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1432853295
Short name T377
Test name
Test status
Simulation time 49979243896 ps
CPU time 1234.09 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:36:51 PM PDT 24
Peak memory 750148 kb
Host smart-f44d0648-3c37-4132-9a2b-33f18f0d4a14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432853295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1432853295
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.97836374
Short name T224
Test name
Test status
Simulation time 660391757 ps
CPU time 37.49 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:16:56 PM PDT 24
Peak memory 200660 kb
Host smart-f2345661-aa89-4240-91c7-5876ab09bb44
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97836374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.97836374
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2352616066
Short name T51
Test name
Test status
Simulation time 87475548521 ps
CPU time 128.71 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:18:25 PM PDT 24
Peak memory 217216 kb
Host smart-294aec8a-53de-42c4-aa3b-0293a1d1f447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352616066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2352616066
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1761712991
Short name T294
Test name
Test status
Simulation time 512822104 ps
CPU time 6.76 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:23 PM PDT 24
Peak memory 200752 kb
Host smart-b8b7b7d3-93d3-4c71-9663-6de45c976eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761712991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1761712991
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.4196422509
Short name T496
Test name
Test status
Simulation time 1912643652 ps
CPU time 42.92 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:59 PM PDT 24
Peak memory 200672 kb
Host smart-bdefea1c-f18e-40ee-86ad-89b1d6ada66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196422509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4196422509
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3452474694
Short name T490
Test name
Test status
Simulation time 11811774 ps
CPU time 0.61 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:16:19 PM PDT 24
Peak memory 196752 kb
Host smart-fb29df91-7029-4d1b-9abd-3742000e32f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452474694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3452474694
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3343293435
Short name T364
Test name
Test status
Simulation time 1135408616 ps
CPU time 34.34 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:51 PM PDT 24
Peak memory 200652 kb
Host smart-fa83f21a-3b5e-412a-a816-c917eb959b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343293435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3343293435
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1809632080
Short name T501
Test name
Test status
Simulation time 13928362449 ps
CPU time 42.86 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:17:01 PM PDT 24
Peak memory 200748 kb
Host smart-ad9574c1-5c72-45db-8ffb-62c130cd65b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809632080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1809632080
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.670682390
Short name T415
Test name
Test status
Simulation time 6605263630 ps
CPU time 1143.28 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:35:20 PM PDT 24
Peak memory 774328 kb
Host smart-ec5892d2-2571-4f96-992f-9d22973b64b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=670682390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.670682390
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1688577738
Short name T325
Test name
Test status
Simulation time 1695351047 ps
CPU time 6.29 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:16:22 PM PDT 24
Peak memory 200716 kb
Host smart-306b879b-3a78-4ed0-9610-68dc7dcea61b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688577738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1688577738
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2095978248
Short name T296
Test name
Test status
Simulation time 3965841474 ps
CPU time 58.74 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:17:15 PM PDT 24
Peak memory 200736 kb
Host smart-ae5f117d-d97e-4f72-95e0-3654f2b454e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095978248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2095978248
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4224758376
Short name T478
Test name
Test status
Simulation time 815399204 ps
CPU time 7.67 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:16:24 PM PDT 24
Peak memory 200652 kb
Host smart-5a7b9010-82b6-43b6-b5e2-592dac80a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224758376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4224758376
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2846015717
Short name T33
Test name
Test status
Simulation time 74613799470 ps
CPU time 816.33 seconds
Started Aug 14 05:16:20 PM PDT 24
Finished Aug 14 05:29:57 PM PDT 24
Peak memory 738680 kb
Host smart-ac33ef47-015f-44a6-a565-85f396dbe6a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846015717 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2846015717
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2453765396
Short name T186
Test name
Test status
Simulation time 6596070126 ps
CPU time 82.69 seconds
Started Aug 14 05:16:18 PM PDT 24
Finished Aug 14 05:17:41 PM PDT 24
Peak memory 200740 kb
Host smart-b8bea3ef-190e-4cc1-8245-b5ff95c46e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453765396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2453765396
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3858330027
Short name T424
Test name
Test status
Simulation time 13599383 ps
CPU time 0.59 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:34 PM PDT 24
Peak memory 196420 kb
Host smart-6f4d7998-bc8d-44ba-92fd-1a05d8b2d14b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858330027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3858330027
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3515143940
Short name T446
Test name
Test status
Simulation time 3596596382 ps
CPU time 46.82 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:17:22 PM PDT 24
Peak memory 200788 kb
Host smart-5cdd963e-ac2c-4830-970f-f14c3db44c88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515143940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3515143940
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2663844267
Short name T477
Test name
Test status
Simulation time 1102725190 ps
CPU time 20.79 seconds
Started Aug 14 05:16:36 PM PDT 24
Finished Aug 14 05:16:57 PM PDT 24
Peak memory 216200 kb
Host smart-36d034ee-982b-498b-8536-3ded7a145e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663844267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2663844267
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2158382869
Short name T518
Test name
Test status
Simulation time 23928300784 ps
CPU time 1053.39 seconds
Started Aug 14 05:16:31 PM PDT 24
Finished Aug 14 05:34:05 PM PDT 24
Peak memory 737004 kb
Host smart-720835ed-1b15-4221-b26f-ff8416283b9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2158382869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2158382869
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.87979275
Short name T494
Test name
Test status
Simulation time 1190940348 ps
CPU time 6.06 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:16:41 PM PDT 24
Peak memory 200524 kb
Host smart-7b3f09d0-9c28-44ad-abb0-1616623cab25
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87979275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.87979275
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.432549004
Short name T416
Test name
Test status
Simulation time 1758223618 ps
CPU time 98.27 seconds
Started Aug 14 05:16:16 PM PDT 24
Finished Aug 14 05:17:54 PM PDT 24
Peak memory 200704 kb
Host smart-b0202c3f-cfb8-4b19-8129-c52d2a7df949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432549004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.432549004
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2239830822
Short name T441
Test name
Test status
Simulation time 847898965 ps
CPU time 15.1 seconds
Started Aug 14 05:16:17 PM PDT 24
Finished Aug 14 05:16:32 PM PDT 24
Peak memory 200532 kb
Host smart-d3f40763-5990-422a-8de1-5c35a2b45f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239830822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2239830822
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2765063090
Short name T442
Test name
Test status
Simulation time 121292415267 ps
CPU time 657.86 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:27:30 PM PDT 24
Peak memory 472700 kb
Host smart-a7738fff-e4aa-4b11-9c0c-6d8b804bdf4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765063090 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2765063090
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1969743727
Short name T459
Test name
Test status
Simulation time 35068825018 ps
CPU time 116.52 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:18:30 PM PDT 24
Peak memory 200740 kb
Host smart-1a6d74f3-d794-4901-a3fd-b324b1124217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969743727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1969743727
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3364139559
Short name T448
Test name
Test status
Simulation time 63924969 ps
CPU time 0.6 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:34 PM PDT 24
Peak memory 196728 kb
Host smart-0de52a7c-885a-4944-bd1b-6bab7dceb41b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364139559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3364139559
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1076740716
Short name T202
Test name
Test status
Simulation time 4166616189 ps
CPU time 66.27 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:17:41 PM PDT 24
Peak memory 200788 kb
Host smart-8b754167-3f25-4f90-8ecb-bc1be1f3dbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1076740716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1076740716
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3709072983
Short name T146
Test name
Test status
Simulation time 558133862 ps
CPU time 7.87 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:16:43 PM PDT 24
Peak memory 200676 kb
Host smart-f4b30d43-d079-4027-b29e-71fcf4286772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709072983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3709072983
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.271580743
Short name T214
Test name
Test status
Simulation time 59267087006 ps
CPU time 933.8 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:32:06 PM PDT 24
Peak memory 706744 kb
Host smart-cfd275ee-b89f-409c-b4a5-582c0f48a7a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271580743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.271580743
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2808332473
Short name T475
Test name
Test status
Simulation time 3362924759 ps
CPU time 190.59 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:19:43 PM PDT 24
Peak memory 200728 kb
Host smart-8d26dc4b-6ca6-44b4-8b92-5a32a6cff69c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808332473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2808332473
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2417889809
Short name T20
Test name
Test status
Simulation time 5929043504 ps
CPU time 87.47 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:59 PM PDT 24
Peak memory 200756 kb
Host smart-59e0e822-743f-4a34-897a-6272b691869d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417889809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2417889809
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2994878538
Short name T199
Test name
Test status
Simulation time 815557673 ps
CPU time 11.9 seconds
Started Aug 14 05:16:31 PM PDT 24
Finished Aug 14 05:16:43 PM PDT 24
Peak memory 200684 kb
Host smart-425c02b1-c8e4-4e32-809e-12f26c8a4bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994878538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2994878538
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.930727239
Short name T97
Test name
Test status
Simulation time 173799839401 ps
CPU time 541.3 seconds
Started Aug 14 05:16:31 PM PDT 24
Finished Aug 14 05:25:32 PM PDT 24
Peak memory 200764 kb
Host smart-4aacfbdb-b12b-4e0c-a12a-6fbafab568e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930727239 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.930727239
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.538107965
Short name T394
Test name
Test status
Simulation time 5974107165 ps
CPU time 53.23 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:25 PM PDT 24
Peak memory 200804 kb
Host smart-a492a25e-b92c-4cb8-ba73-a8b62edc4071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538107965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.538107965
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2539179971
Short name T56
Test name
Test status
Simulation time 40217303 ps
CPU time 0.59 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:16:34 PM PDT 24
Peak memory 196756 kb
Host smart-f8c9b3d6-02a7-48b6-a9a4-0c89ed75aee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539179971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2539179971
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2949632910
Short name T412
Test name
Test status
Simulation time 6128484450 ps
CPU time 89.76 seconds
Started Aug 14 05:16:48 PM PDT 24
Finished Aug 14 05:18:18 PM PDT 24
Peak memory 217136 kb
Host smart-01b0eff0-d893-46ef-bbe9-b7bd0d2169d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2949632910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2949632910
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.96424863
Short name T25
Test name
Test status
Simulation time 723056141 ps
CPU time 10.52 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:16:43 PM PDT 24
Peak memory 200700 kb
Host smart-6f79735c-95a5-4dd7-82a8-4314e163ae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96424863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.96424863
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3816786425
Short name T421
Test name
Test status
Simulation time 3744443334 ps
CPU time 686.49 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:28:00 PM PDT 24
Peak memory 750512 kb
Host smart-98844b62-e584-4588-8e96-6666ee4c0899
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3816786425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3816786425
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1656205370
Short name T358
Test name
Test status
Simulation time 1612630181 ps
CPU time 6.65 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:16:38 PM PDT 24
Peak memory 200600 kb
Host smart-a64515e6-a44d-4ee2-98df-fa9cd9bd6257
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656205370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1656205370
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1695611357
Short name T37
Test name
Test status
Simulation time 58704248695 ps
CPU time 186.73 seconds
Started Aug 14 05:16:31 PM PDT 24
Finished Aug 14 05:19:38 PM PDT 24
Peak memory 200928 kb
Host smart-432d069c-b16e-4f01-9738-3f5958e0f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695611357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1695611357
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3512505277
Short name T379
Test name
Test status
Simulation time 1294442085 ps
CPU time 5.6 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:16:38 PM PDT 24
Peak memory 200700 kb
Host smart-69081899-b8cb-4aec-a521-1d30d87a3e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512505277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3512505277
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.884451240
Short name T185
Test name
Test status
Simulation time 71053577754 ps
CPU time 2352.58 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:55:46 PM PDT 24
Peak memory 759976 kb
Host smart-7575a8c4-f3ad-4be4-97a5-e896c89665ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884451240 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.884451240
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3184187621
Short name T447
Test name
Test status
Simulation time 1075324165 ps
CPU time 15.91 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:16:49 PM PDT 24
Peak memory 200656 kb
Host smart-5ecfd852-d810-43fe-ae9c-11cc4f30dcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184187621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3184187621
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.318967521
Short name T242
Test name
Test status
Simulation time 11160507 ps
CPU time 0.6 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:35 PM PDT 24
Peak memory 195584 kb
Host smart-dd18e123-3a59-4c8b-ab08-f96c60a32e26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318967521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.318967521
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3962196898
Short name T246
Test name
Test status
Simulation time 2421410653 ps
CPU time 33.46 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 200748 kb
Host smart-0d09eac8-58fc-409c-b89d-e38477a6235b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3962196898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3962196898
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4037683466
Short name T159
Test name
Test status
Simulation time 3187147415 ps
CPU time 64.83 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:37 PM PDT 24
Peak memory 200756 kb
Host smart-d3b306f9-a705-436c-8560-b343f379568a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037683466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4037683466
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3832483398
Short name T182
Test name
Test status
Simulation time 54028984992 ps
CPU time 851.76 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:30:44 PM PDT 24
Peak memory 707056 kb
Host smart-af528491-f591-4232-8ff8-229ff72bb50a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3832483398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3832483398
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3517325251
Short name T529
Test name
Test status
Simulation time 9703203036 ps
CPU time 112.84 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:18:25 PM PDT 24
Peak memory 200744 kb
Host smart-b6c83841-68f0-49c7-a287-c21273d3a4a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517325251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3517325251
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1252383473
Short name T34
Test name
Test status
Simulation time 9581967575 ps
CPU time 110.06 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:18:23 PM PDT 24
Peak memory 200784 kb
Host smart-2d65f6e2-e2fe-4684-9a3f-7d3c81ef92d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252383473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1252383473
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3592592143
Short name T291
Test name
Test status
Simulation time 1285949087 ps
CPU time 6.56 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:16:39 PM PDT 24
Peak memory 200684 kb
Host smart-a036be4f-8293-4444-b1ee-225ea93470b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592592143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3592592143
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.352614920
Short name T347
Test name
Test status
Simulation time 110253546687 ps
CPU time 1008.3 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:33:22 PM PDT 24
Peak memory 726892 kb
Host smart-c8c1bcdb-4b8a-49da-9800-6eff29b11440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352614920 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.352614920
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3017163539
Short name T284
Test name
Test status
Simulation time 1276661938 ps
CPU time 13.45 seconds
Started Aug 14 05:16:31 PM PDT 24
Finished Aug 14 05:16:45 PM PDT 24
Peak memory 200724 kb
Host smart-2171bf8c-51f9-4b07-8c30-4d306f56d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017163539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3017163539
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.640585001
Short name T303
Test name
Test status
Simulation time 14041011 ps
CPU time 0.61 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:16:34 PM PDT 24
Peak memory 196760 kb
Host smart-73e24dd8-a7cc-4ec0-9479-0f3319d590c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640585001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.640585001
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2594859433
Short name T371
Test name
Test status
Simulation time 3109877757 ps
CPU time 43.36 seconds
Started Aug 14 05:16:30 PM PDT 24
Finished Aug 14 05:17:14 PM PDT 24
Peak memory 200744 kb
Host smart-5585a910-327a-44ee-a985-d6addd3457df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594859433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2594859433
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.418642969
Short name T533
Test name
Test status
Simulation time 540878753 ps
CPU time 4 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:16:39 PM PDT 24
Peak memory 200660 kb
Host smart-8fe86fb8-ea38-4ea1-903b-0eba6b8d8d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418642969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.418642969
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2676912972
Short name T81
Test name
Test status
Simulation time 130411057657 ps
CPU time 2244.14 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:53:57 PM PDT 24
Peak memory 783600 kb
Host smart-4ece13fb-0cde-41e9-9b1a-b6e63c609d67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676912972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2676912972
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.562389332
Short name T233
Test name
Test status
Simulation time 5101085765 ps
CPU time 83.23 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:55 PM PDT 24
Peak memory 200684 kb
Host smart-7bb211c8-b292-4518-9a10-ad2b1fe431c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562389332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.562389332
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3267256486
Short name T278
Test name
Test status
Simulation time 16798537426 ps
CPU time 106.83 seconds
Started Aug 14 05:16:37 PM PDT 24
Finished Aug 14 05:18:24 PM PDT 24
Peak memory 200776 kb
Host smart-6719669b-41d0-4414-a58d-918e7d33c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267256486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3267256486
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.909974055
Short name T342
Test name
Test status
Simulation time 99391064 ps
CPU time 4.57 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:39 PM PDT 24
Peak memory 200684 kb
Host smart-feef7a2f-21ec-41d4-b141-43f8abc1a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909974055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.909974055
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1099802719
Short name T144
Test name
Test status
Simulation time 127082020697 ps
CPU time 1022.05 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:33:35 PM PDT 24
Peak memory 691468 kb
Host smart-c244d084-94f9-4680-809f-dcabaca00c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099802719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1099802719
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.563456277
Short name T104
Test name
Test status
Simulation time 12848133890 ps
CPU time 114.69 seconds
Started Aug 14 05:16:33 PM PDT 24
Finished Aug 14 05:18:28 PM PDT 24
Peak memory 200740 kb
Host smart-e0d8b0be-d617-4b0e-9f58-517c96bed7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563456277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.563456277
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1546766169
Short name T58
Test name
Test status
Simulation time 19263899 ps
CPU time 0.59 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:35 PM PDT 24
Peak memory 196508 kb
Host smart-4a0b8080-3099-47d1-b26a-84aab667ae7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546766169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1546766169
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1075684225
Short name T392
Test name
Test status
Simulation time 21676037110 ps
CPU time 83.42 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:17:55 PM PDT 24
Peak memory 200748 kb
Host smart-a019479f-d0f1-4418-9c8e-3d6e520ae835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075684225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1075684225
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2874413416
Short name T44
Test name
Test status
Simulation time 2867386653 ps
CPU time 39.41 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:17:14 PM PDT 24
Peak memory 200732 kb
Host smart-272fba48-af28-49f8-954b-432448aad89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874413416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2874413416
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3120356384
Short name T404
Test name
Test status
Simulation time 4579847928 ps
CPU time 854.84 seconds
Started Aug 14 05:16:32 PM PDT 24
Finished Aug 14 05:30:47 PM PDT 24
Peak memory 718200 kb
Host smart-223b45a2-0e59-4f79-80df-cd55c5e1f821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120356384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3120356384
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1698328866
Short name T433
Test name
Test status
Simulation time 521733492 ps
CPU time 9.24 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:16:44 PM PDT 24
Peak memory 200532 kb
Host smart-036175af-65ef-4ad7-9a60-daa5e098629d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698328866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1698328866
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.291231815
Short name T45
Test name
Test status
Simulation time 40252416422 ps
CPU time 139.8 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:18:54 PM PDT 24
Peak memory 200756 kb
Host smart-0dbe0588-fb69-4737-aece-635f28467396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291231815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.291231815
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2727511724
Short name T378
Test name
Test status
Simulation time 4994696789 ps
CPU time 16.84 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:51 PM PDT 24
Peak memory 200744 kb
Host smart-cb6dbc4c-c2ec-4a7b-a4ae-05522f21b281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727511724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2727511724
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.485850876
Short name T96
Test name
Test status
Simulation time 36055863922 ps
CPU time 467.42 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:24:23 PM PDT 24
Peak memory 200816 kb
Host smart-11959a8f-bcb5-43dc-838e-efaf9e5900c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485850876 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.485850876
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2480654428
Short name T462
Test name
Test status
Simulation time 330798204 ps
CPU time 18.34 seconds
Started Aug 14 05:16:34 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200624 kb
Host smart-ab27faef-dccd-4196-92b0-adfe2a811331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480654428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2480654428
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.472673354
Short name T283
Test name
Test status
Simulation time 19895097 ps
CPU time 0.59 seconds
Started Aug 14 05:15:03 PM PDT 24
Finished Aug 14 05:15:04 PM PDT 24
Peak memory 196652 kb
Host smart-1aa8acfd-cb16-4e73-acb6-a4401c1c9604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472673354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.472673354
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1755688335
Short name T386
Test name
Test status
Simulation time 5941056178 ps
CPU time 88.23 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:16:33 PM PDT 24
Peak memory 209088 kb
Host smart-f1d2c13e-ac66-4a88-ae77-5ce7b22873bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755688335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1755688335
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2480111905
Short name T222
Test name
Test status
Simulation time 3234983366 ps
CPU time 61.73 seconds
Started Aug 14 05:15:03 PM PDT 24
Finished Aug 14 05:16:05 PM PDT 24
Peak memory 217064 kb
Host smart-e14a954d-93b4-45d1-80a8-a3f4dd095b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480111905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2480111905
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.20428163
Short name T191
Test name
Test status
Simulation time 5754543282 ps
CPU time 241.22 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:19:05 PM PDT 24
Peak memory 598948 kb
Host smart-2076b62b-d1df-4e49-b06f-8acb8e5309ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20428163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.20428163
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3527251262
Short name T458
Test name
Test status
Simulation time 8077587278 ps
CPU time 62.57 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:07 PM PDT 24
Peak memory 200740 kb
Host smart-9054bf94-d25e-4bf1-bb99-0a4c821d6d29
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527251262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3527251262
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.11370053
Short name T309
Test name
Test status
Simulation time 179981778451 ps
CPU time 117 seconds
Started Aug 14 05:15:09 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 200928 kb
Host smart-1644ec2e-3d47-479d-9169-6892f89c8a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11370053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.11370053
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.2174574383
Short name T254
Test name
Test status
Simulation time 51566340 ps
CPU time 1.14 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:15:05 PM PDT 24
Peak memory 200700 kb
Host smart-fd28d91f-44c5-46e3-bdc1-abcda1b675df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174574383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2174574383
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4189407824
Short name T32
Test name
Test status
Simulation time 489535686471 ps
CPU time 4095.98 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 06:23:22 PM PDT 24
Peak memory 828328 kb
Host smart-d721efd6-be8c-47e3-8030-351c3944f95c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189407824 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4189407824
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2550833439
Short name T227
Test name
Test status
Simulation time 2205458033 ps
CPU time 38.38 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:15:43 PM PDT 24
Peak memory 200736 kb
Host smart-51afce82-6546-460c-8706-ae672810880f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2550833439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2550833439
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3059222804
Short name T525
Test name
Test status
Simulation time 19830163622 ps
CPU time 110.63 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:55 PM PDT 24
Peak memory 200800 kb
Host smart-b21e332b-f78a-43b4-b98f-d8f9dd94a34e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3059222804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3059222804
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1132122300
Short name T466
Test name
Test status
Simulation time 6049011127 ps
CPU time 74.01 seconds
Started Aug 14 05:15:07 PM PDT 24
Finished Aug 14 05:16:21 PM PDT 24
Peak memory 200756 kb
Host smart-ffcce383-52f6-4559-a4f3-1c951ba5e9b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1132122300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1132122300
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1131579018
Short name T48
Test name
Test status
Simulation time 142389157110 ps
CPU time 592.88 seconds
Started Aug 14 05:15:08 PM PDT 24
Finished Aug 14 05:25:01 PM PDT 24
Peak memory 200748 kb
Host smart-5926c008-d241-4db9-b297-1b624079c9a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1131579018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1131579018
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3997118300
Short name T109
Test name
Test status
Simulation time 84124734978 ps
CPU time 2138.38 seconds
Started Aug 14 05:15:08 PM PDT 24
Finished Aug 14 05:50:48 PM PDT 24
Peak memory 208916 kb
Host smart-2844c472-8ced-421d-bb40-a539127818be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3997118300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3997118300
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1659696729
Short name T68
Test name
Test status
Simulation time 43062910301 ps
CPU time 2333.11 seconds
Started Aug 14 05:15:05 PM PDT 24
Finished Aug 14 05:53:59 PM PDT 24
Peak memory 216328 kb
Host smart-3ca52bcd-0301-4214-bda5-c49f2017894e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1659696729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1659696729
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3454781145
Short name T257
Test name
Test status
Simulation time 1255661831 ps
CPU time 62.72 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:07 PM PDT 24
Peak memory 200656 kb
Host smart-117a1f1e-398d-4ae2-a8c1-a8c74385fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454781145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3454781145
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1502730684
Short name T354
Test name
Test status
Simulation time 50717878 ps
CPU time 0.64 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:16:44 PM PDT 24
Peak memory 196912 kb
Host smart-d8c2d91d-8c89-4697-8964-0e993f076aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502730684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1502730684
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.317815051
Short name T206
Test name
Test status
Simulation time 9751825760 ps
CPU time 80.05 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:17:56 PM PDT 24
Peak memory 200804 kb
Host smart-3c48db72-9583-4a87-92ca-c271d8f1739d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317815051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.317815051
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2591195972
Short name T438
Test name
Test status
Simulation time 184612640 ps
CPU time 10.17 seconds
Started Aug 14 05:16:42 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200684 kb
Host smart-cc1d8bb2-2522-4847-91a3-a9c0fda6bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591195972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2591195972
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3170823169
Short name T444
Test name
Test status
Simulation time 13456331721 ps
CPU time 1192.71 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:36:33 PM PDT 24
Peak memory 705696 kb
Host smart-9b9d48ca-44ec-4755-a081-a06aa35ee955
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170823169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3170823169
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4250638646
Short name T99
Test name
Test status
Simulation time 411713957 ps
CPU time 22.52 seconds
Started Aug 14 05:16:44 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 200636 kb
Host smart-b277f02b-d99b-41fc-b75b-6df0cb475652
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250638646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4250638646
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3517350213
Short name T301
Test name
Test status
Simulation time 39753861921 ps
CPU time 128.48 seconds
Started Aug 14 05:16:36 PM PDT 24
Finished Aug 14 05:18:44 PM PDT 24
Peak memory 200776 kb
Host smart-90847aa0-9f84-49c7-99dd-0e4ee24705a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517350213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3517350213
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.125996302
Short name T237
Test name
Test status
Simulation time 515644328 ps
CPU time 3.33 seconds
Started Aug 14 05:16:35 PM PDT 24
Finished Aug 14 05:16:38 PM PDT 24
Peak memory 200688 kb
Host smart-b7ba5943-69a6-4e19-b0ea-d8a7ec286576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125996302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.125996302
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1996340696
Short name T83
Test name
Test status
Simulation time 2303454466 ps
CPU time 156.12 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:19:17 PM PDT 24
Peak memory 364200 kb
Host smart-868b96ea-d8eb-4684-8d93-c5a9319fd1b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996340696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1996340696
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2767359285
Short name T276
Test name
Test status
Simulation time 79665750265 ps
CPU time 128.15 seconds
Started Aug 14 05:16:42 PM PDT 24
Finished Aug 14 05:18:50 PM PDT 24
Peak memory 200744 kb
Host smart-3517b76b-e9b1-4df1-9d37-d48a404cfd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767359285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2767359285
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.179024290
Short name T507
Test name
Test status
Simulation time 14810006 ps
CPU time 0.66 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:16:40 PM PDT 24
Peak memory 196376 kb
Host smart-4b7b3b5d-ee1a-4639-bb12-79421edc1017
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179024290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.179024290
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.848755549
Short name T530
Test name
Test status
Simulation time 4033508503 ps
CPU time 58.25 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:17:38 PM PDT 24
Peak memory 200680 kb
Host smart-5aa97c9d-5639-430e-ac55-10edc464b24d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=848755549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.848755549
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3471454596
Short name T5
Test name
Test status
Simulation time 6412719838 ps
CPU time 29.84 seconds
Started Aug 14 05:16:46 PM PDT 24
Finished Aug 14 05:17:16 PM PDT 24
Peak memory 217092 kb
Host smart-e4788f0a-b544-4207-be97-24b6c12d8a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471454596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3471454596
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2483994609
Short name T487
Test name
Test status
Simulation time 4952372944 ps
CPU time 959.35 seconds
Started Aug 14 05:16:46 PM PDT 24
Finished Aug 14 05:32:45 PM PDT 24
Peak memory 732720 kb
Host smart-8065624a-7e99-4613-8814-1eed0a39fb79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2483994609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2483994609
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1584141659
Short name T47
Test name
Test status
Simulation time 28543089705 ps
CPU time 88.13 seconds
Started Aug 14 05:16:44 PM PDT 24
Finished Aug 14 05:18:12 PM PDT 24
Peak memory 200600 kb
Host smart-63cc5bad-fd84-477f-89dd-6d0913166619
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584141659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1584141659
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1738709103
Short name T436
Test name
Test status
Simulation time 10943923347 ps
CPU time 195.96 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:19:57 PM PDT 24
Peak memory 200740 kb
Host smart-55be63b3-9772-45b4-bfcb-205a592766ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738709103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1738709103
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2179237318
Short name T357
Test name
Test status
Simulation time 231825043 ps
CPU time 4.38 seconds
Started Aug 14 05:16:48 PM PDT 24
Finished Aug 14 05:16:53 PM PDT 24
Peak memory 200752 kb
Host smart-310e5fea-ba3a-4346-9a02-4977aac3bcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179237318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2179237318
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1308740710
Short name T285
Test name
Test status
Simulation time 18669498295 ps
CPU time 448.18 seconds
Started Aug 14 05:16:45 PM PDT 24
Finished Aug 14 05:24:13 PM PDT 24
Peak memory 200740 kb
Host smart-cfa25f34-5e38-45db-beab-1845ef06f285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308740710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1308740710
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.206944514
Short name T275
Test name
Test status
Simulation time 20055557963 ps
CPU time 133.47 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:18:54 PM PDT 24
Peak memory 200724 kb
Host smart-753f1ad4-b6da-4dce-a18f-b67796ab3d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206944514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.206944514
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1248075729
Short name T194
Test name
Test status
Simulation time 14140848 ps
CPU time 0.6 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:16:44 PM PDT 24
Peak memory 195728 kb
Host smart-77c6c866-06bd-4755-bfed-4f0e96b43307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248075729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1248075729
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2178048271
Short name T205
Test name
Test status
Simulation time 7693346162 ps
CPU time 72.69 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:17:53 PM PDT 24
Peak memory 200736 kb
Host smart-b65226d3-6dbb-4433-ad16-808e31d43f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2178048271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2178048271
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1227742162
Short name T249
Test name
Test status
Simulation time 13459461961 ps
CPU time 72.14 seconds
Started Aug 14 05:16:45 PM PDT 24
Finished Aug 14 05:17:58 PM PDT 24
Peak memory 200836 kb
Host smart-9ad39647-fb47-4561-b491-07c439aa8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227742162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1227742162
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2393277928
Short name T503
Test name
Test status
Simulation time 14551469217 ps
CPU time 560.74 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:26:04 PM PDT 24
Peak memory 652340 kb
Host smart-41ebac06-6903-4df0-84ac-2f29c6e4886e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393277928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2393277928
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2948973759
Short name T101
Test name
Test status
Simulation time 12031601108 ps
CPU time 197.09 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:20:01 PM PDT 24
Peak memory 200712 kb
Host smart-5771d62f-2b61-45c4-8acf-be4c599b67b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948973759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2948973759
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3151548058
Short name T195
Test name
Test status
Simulation time 41077393025 ps
CPU time 183.36 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:19:44 PM PDT 24
Peak memory 216980 kb
Host smart-9ba11b33-4096-4ab7-acfa-62748b810402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151548058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3151548058
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.4097532218
Short name T179
Test name
Test status
Simulation time 2945512000 ps
CPU time 7.35 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:16:49 PM PDT 24
Peak memory 200756 kb
Host smart-cb474817-ed7e-4ef3-ab0d-33055f716fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097532218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.4097532218
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3994262851
Short name T93
Test name
Test status
Simulation time 302558021280 ps
CPU time 1399.04 seconds
Started Aug 14 05:16:40 PM PDT 24
Finished Aug 14 05:39:59 PM PDT 24
Peak memory 715984 kb
Host smart-49a82ebc-2786-47a3-96c9-16a0b88cc6b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994262851 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3994262851
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.916024529
Short name T395
Test name
Test status
Simulation time 2722704006 ps
CPU time 33.07 seconds
Started Aug 14 05:16:39 PM PDT 24
Finished Aug 14 05:17:12 PM PDT 24
Peak memory 200656 kb
Host smart-70d11faf-bbd1-4c2e-8a4c-93c5532cccd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916024529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.916024529
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.232058284
Short name T528
Test name
Test status
Simulation time 13993805 ps
CPU time 0.6 seconds
Started Aug 14 05:16:42 PM PDT 24
Finished Aug 14 05:16:43 PM PDT 24
Peak memory 195880 kb
Host smart-3f2f5332-9076-40e0-a5db-d53666b72299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232058284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.232058284
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2040909460
Short name T440
Test name
Test status
Simulation time 1101403923 ps
CPU time 15.18 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:16:58 PM PDT 24
Peak memory 200668 kb
Host smart-7f0ec6cd-5d4c-4f2a-b7f1-217c6eb6f25e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040909460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2040909460
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3212964017
Short name T380
Test name
Test status
Simulation time 4504436402 ps
CPU time 59.32 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:17:40 PM PDT 24
Peak memory 209024 kb
Host smart-9ae8491d-cdfa-4a80-b56b-7b6777d6cf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212964017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3212964017
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2395617349
Short name T171
Test name
Test status
Simulation time 2587733252 ps
CPU time 373.94 seconds
Started Aug 14 05:16:44 PM PDT 24
Finished Aug 14 05:22:59 PM PDT 24
Peak memory 597920 kb
Host smart-70d7593e-bdc4-409a-bb1a-24acad8a5060
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2395617349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2395617349
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4013060581
Short name T73
Test name
Test status
Simulation time 9933119361 ps
CPU time 66.34 seconds
Started Aug 14 05:16:39 PM PDT 24
Finished Aug 14 05:17:46 PM PDT 24
Peak memory 200712 kb
Host smart-40903e2b-1565-4652-9b3a-4f5d1126d138
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013060581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4013060581
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2821417397
Short name T388
Test name
Test status
Simulation time 29075957064 ps
CPU time 178.8 seconds
Started Aug 14 05:16:42 PM PDT 24
Finished Aug 14 05:19:40 PM PDT 24
Peak memory 200720 kb
Host smart-1e222826-fbf9-4711-a4ca-f95637c993bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821417397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2821417397
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2308771264
Short name T334
Test name
Test status
Simulation time 5340654684 ps
CPU time 14 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:16:55 PM PDT 24
Peak memory 200728 kb
Host smart-cedb8b9c-b5bf-4557-bd6a-8a6442cdf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308771264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2308771264
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.197249731
Short name T85
Test name
Test status
Simulation time 339888606867 ps
CPU time 4032.09 seconds
Started Aug 14 05:16:48 PM PDT 24
Finished Aug 14 06:24:01 PM PDT 24
Peak memory 826116 kb
Host smart-21b45710-9861-450e-b30b-d588c48c6e15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197249731 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.197249731
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2009942190
Short name T406
Test name
Test status
Simulation time 1834604793 ps
CPU time 23.08 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:17:04 PM PDT 24
Peak memory 200668 kb
Host smart-c0b8286e-0206-4258-8acd-45ec25f4c0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009942190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2009942190
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.824205772
Short name T288
Test name
Test status
Simulation time 12479686 ps
CPU time 0.59 seconds
Started Aug 14 05:16:39 PM PDT 24
Finished Aug 14 05:16:40 PM PDT 24
Peak memory 196412 kb
Host smart-7b194926-b5e5-4cf0-972b-2a0809a877af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824205772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.824205772
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4254761715
Short name T262
Test name
Test status
Simulation time 1735076649 ps
CPU time 25.05 seconds
Started Aug 14 05:16:44 PM PDT 24
Finished Aug 14 05:17:09 PM PDT 24
Peak memory 200828 kb
Host smart-262cae54-59cf-4440-a247-3269831a34cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254761715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4254761715
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3178599745
Short name T162
Test name
Test status
Simulation time 1753029554 ps
CPU time 22.79 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:17:04 PM PDT 24
Peak memory 200732 kb
Host smart-bc6e3eb0-a6ad-4d17-bc68-80822f6630a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178599745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3178599745
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2260020191
Short name T87
Test name
Test status
Simulation time 18052770594 ps
CPU time 859.41 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:31:01 PM PDT 24
Peak memory 698212 kb
Host smart-73127f17-2727-43f3-9479-a3b3496325ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260020191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2260020191
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.257297852
Short name T180
Test name
Test status
Simulation time 54732940270 ps
CPU time 161.31 seconds
Started Aug 14 05:16:39 PM PDT 24
Finished Aug 14 05:19:20 PM PDT 24
Peak memory 200748 kb
Host smart-f4cf6920-6572-47dd-98db-ccb1d9f29ebc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257297852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.257297852
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2138589032
Short name T505
Test name
Test status
Simulation time 34489439 ps
CPU time 0.66 seconds
Started Aug 14 05:16:47 PM PDT 24
Finished Aug 14 05:16:47 PM PDT 24
Peak memory 197128 kb
Host smart-8b5834f1-25bf-4249-a612-036cf785730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138589032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2138589032
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1996045350
Short name T211
Test name
Test status
Simulation time 762883051 ps
CPU time 7.73 seconds
Started Aug 14 05:16:44 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200708 kb
Host smart-a8b770e1-8704-4c00-b619-ebbf51a902f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996045350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1996045350
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2933577436
Short name T91
Test name
Test status
Simulation time 375360153960 ps
CPU time 1931.34 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:48:53 PM PDT 24
Peak memory 774908 kb
Host smart-760eab18-3043-4020-a036-c31ee651827e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933577436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2933577436
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.171255603
Short name T238
Test name
Test status
Simulation time 30554816820 ps
CPU time 136.39 seconds
Started Aug 14 05:16:43 PM PDT 24
Finished Aug 14 05:18:59 PM PDT 24
Peak memory 200748 kb
Host smart-2b000718-9178-4fa5-acdc-2ea124245112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171255603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.171255603
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1946942115
Short name T219
Test name
Test status
Simulation time 13044556 ps
CPU time 0.65 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 197444 kb
Host smart-e6188187-1983-48ec-8313-dfb699de9ab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946942115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1946942115
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3383564067
Short name T174
Test name
Test status
Simulation time 2078480855 ps
CPU time 33.13 seconds
Started Aug 14 05:16:46 PM PDT 24
Finished Aug 14 05:17:19 PM PDT 24
Peak memory 200672 kb
Host smart-10a08158-d099-4686-bb8f-c70c9c9bebf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383564067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3383564067
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3620155581
Short name T302
Test name
Test status
Simulation time 1812130249 ps
CPU time 36.3 seconds
Started Aug 14 05:16:49 PM PDT 24
Finished Aug 14 05:17:25 PM PDT 24
Peak memory 200684 kb
Host smart-d43bba35-b0e3-411d-abdc-8da0fcae7673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620155581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3620155581
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3719147386
Short name T368
Test name
Test status
Simulation time 9924178317 ps
CPU time 809.94 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:30:20 PM PDT 24
Peak memory 680648 kb
Host smart-ffd1e304-0acf-4f11-ad7f-f1b5d315da37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3719147386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3719147386
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2986311526
Short name T366
Test name
Test status
Simulation time 220460648373 ps
CPU time 172.94 seconds
Started Aug 14 05:16:49 PM PDT 24
Finished Aug 14 05:19:42 PM PDT 24
Peak memory 200740 kb
Host smart-1b816bd8-1c39-4182-a712-ac901b715325
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986311526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2986311526
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3918917982
Short name T432
Test name
Test status
Simulation time 836971135 ps
CPU time 21.21 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:17:02 PM PDT 24
Peak memory 200656 kb
Host smart-7da49e82-0871-48c5-a99d-626d6bbe802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918917982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3918917982
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4227455731
Short name T8
Test name
Test status
Simulation time 6368909607 ps
CPU time 7.81 seconds
Started Aug 14 05:16:41 PM PDT 24
Finished Aug 14 05:16:49 PM PDT 24
Peak memory 200740 kb
Host smart-508f0100-dcbd-40c7-9e33-f0f0b8e60c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227455731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4227455731
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.129298276
Short name T499
Test name
Test status
Simulation time 63596805650 ps
CPU time 1723.68 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:45:42 PM PDT 24
Peak memory 761196 kb
Host smart-f86a0891-2b56-4ca9-b2ff-0b5efbd5c7b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129298276 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.129298276
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1217570604
Short name T12
Test name
Test status
Simulation time 10475342705 ps
CPU time 47.58 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:17:39 PM PDT 24
Peak memory 200808 kb
Host smart-65976d50-b6a6-4ff9-80fb-970129bedf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217570604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1217570604
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.910066657
Short name T307
Test name
Test status
Simulation time 16851193 ps
CPU time 0.61 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:16:53 PM PDT 24
Peak memory 196776 kb
Host smart-743798b0-3974-4c85-96d2-f72e05365e61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910066657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.910066657
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2862575705
Short name T4
Test name
Test status
Simulation time 298244463 ps
CPU time 16.75 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:17:08 PM PDT 24
Peak memory 200668 kb
Host smart-7d82e9a1-9166-4b0e-acd1-75b35aa6ff07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862575705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2862575705
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.4293664828
Short name T397
Test name
Test status
Simulation time 8462248259 ps
CPU time 62.43 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:17:53 PM PDT 24
Peak memory 200908 kb
Host smart-94b92a91-9b36-4265-b85d-a9eecb126aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293664828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.4293664828
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.915049056
Short name T86
Test name
Test status
Simulation time 2128635379 ps
CPU time 420.76 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:23:52 PM PDT 24
Peak memory 673012 kb
Host smart-c5ab5844-c020-47a2-84eb-c7250c6d44c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=915049056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.915049056
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2711604100
Short name T427
Test name
Test status
Simulation time 40060709720 ps
CPU time 147.95 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:19:18 PM PDT 24
Peak memory 200796 kb
Host smart-3fc93a4b-0dd0-4c14-8a71-4d6a8f29d971
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711604100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2711604100
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.429008023
Short name T348
Test name
Test status
Simulation time 895168656 ps
CPU time 43.05 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:17:33 PM PDT 24
Peak memory 200724 kb
Host smart-09f75360-6495-4205-97f6-c26d0f501964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429008023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.429008023
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2762478963
Short name T419
Test name
Test status
Simulation time 19042935 ps
CPU time 0.68 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:16:50 PM PDT 24
Peak memory 197204 kb
Host smart-828ff6fc-0e41-4f96-b145-5c99c1bd373d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762478963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2762478963
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1741827289
Short name T230
Test name
Test status
Simulation time 87032078805 ps
CPU time 157.3 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:19:36 PM PDT 24
Peak memory 200752 kb
Host smart-a7d3f4cd-9410-4424-bd44-586acd9c0a86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741827289 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1741827289
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3161598189
Short name T330
Test name
Test status
Simulation time 2292929851 ps
CPU time 114.27 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:18:44 PM PDT 24
Peak memory 200740 kb
Host smart-92efd2d5-aae4-438f-8f16-0c4276243d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161598189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3161598189
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3634059438
Short name T479
Test name
Test status
Simulation time 38895983 ps
CPU time 0.62 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 196756 kb
Host smart-dac97961-4e90-4336-ac4e-dfd295670bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634059438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3634059438
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1665550109
Short name T216
Test name
Test status
Simulation time 1175318602 ps
CPU time 64.41 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:17:55 PM PDT 24
Peak memory 200652 kb
Host smart-f8b6dd04-d26d-47a4-8fcf-3fbcad94ffc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1665550109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1665550109
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3187389955
Short name T24
Test name
Test status
Simulation time 777600448 ps
CPU time 6.81 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:16:59 PM PDT 24
Peak memory 200696 kb
Host smart-ac4dfdac-5290-45eb-9457-402ff5534e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187389955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3187389955
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1442670111
Short name T352
Test name
Test status
Simulation time 4145105582 ps
CPU time 420.39 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:24:00 PM PDT 24
Peak memory 702868 kb
Host smart-33263e29-fc45-480a-8bfd-8aaffd18a4e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442670111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1442670111
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2868567901
Short name T312
Test name
Test status
Simulation time 1373185285 ps
CPU time 47.53 seconds
Started Aug 14 05:16:53 PM PDT 24
Finished Aug 14 05:17:40 PM PDT 24
Peak memory 200656 kb
Host smart-a772e2c9-482b-4ee2-a744-a36ad5f07702
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868567901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2868567901
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4088259592
Short name T393
Test name
Test status
Simulation time 26645457 ps
CPU time 1.12 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200656 kb
Host smart-d582bae8-02af-4e47-95cc-f14f839750d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088259592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4088259592
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3064927974
Short name T267
Test name
Test status
Simulation time 2507526479 ps
CPU time 8.11 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:06 PM PDT 24
Peak memory 200728 kb
Host smart-55686fe5-fd31-49ac-8a46-9dc1042c49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064927974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3064927974
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2103292501
Short name T94
Test name
Test status
Simulation time 36678998503 ps
CPU time 462.03 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:24:34 PM PDT 24
Peak memory 262648 kb
Host smart-a323eecb-1dbe-4ff7-ac34-ab0b75c4972f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103292501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2103292501
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.33780010
Short name T218
Test name
Test status
Simulation time 3796863196 ps
CPU time 48.45 seconds
Started Aug 14 05:16:49 PM PDT 24
Finished Aug 14 05:17:38 PM PDT 24
Peak memory 200788 kb
Host smart-dc0fe340-9c89-4a73-a146-c20fa61cf5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33780010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.33780010
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1347879068
Short name T365
Test name
Test status
Simulation time 49252442 ps
CPU time 0.6 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 196736 kb
Host smart-1c108311-07fa-44cf-9397-0516a3da3c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347879068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1347879068
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.759668813
Short name T336
Test name
Test status
Simulation time 874731981 ps
CPU time 26.15 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:17:17 PM PDT 24
Peak memory 200664 kb
Host smart-5eb3984b-cddb-4b5a-b31c-8eb1a62a83c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759668813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.759668813
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3703271649
Short name T292
Test name
Test status
Simulation time 12665164814 ps
CPU time 55.01 seconds
Started Aug 14 05:16:55 PM PDT 24
Finished Aug 14 05:17:50 PM PDT 24
Peak memory 200752 kb
Host smart-29446cfc-f557-4fb1-8621-7a62b16b1a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703271649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3703271649
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2343181672
Short name T286
Test name
Test status
Simulation time 18037874977 ps
CPU time 444.99 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 05:24:17 PM PDT 24
Peak memory 667056 kb
Host smart-2a837bb8-e5f7-4762-a5db-4b164f82514d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2343181672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2343181672
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3942782894
Short name T521
Test name
Test status
Simulation time 40602266619 ps
CPU time 98.68 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:18:30 PM PDT 24
Peak memory 200800 kb
Host smart-4e82a74f-7939-4798-a01e-c17c00ff483f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942782894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3942782894
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2041143447
Short name T328
Test name
Test status
Simulation time 3640978497 ps
CPU time 65.84 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:17:57 PM PDT 24
Peak memory 200772 kb
Host smart-6c8ad21b-202e-42c7-bde3-79b40223925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041143447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2041143447
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1775824711
Short name T65
Test name
Test status
Simulation time 1867901968 ps
CPU time 9.14 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:17:01 PM PDT 24
Peak memory 200704 kb
Host smart-7a9774fa-88f6-458f-8f2b-4bed77c8897a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775824711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1775824711
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3397883235
Short name T28
Test name
Test status
Simulation time 53716877465 ps
CPU time 2812.12 seconds
Started Aug 14 05:16:52 PM PDT 24
Finished Aug 14 06:03:45 PM PDT 24
Peak memory 787680 kb
Host smart-96b0a43e-63ea-40a7-a6b1-c7cd19bab654
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397883235 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3397883235
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.44942579
Short name T112
Test name
Test status
Simulation time 9810892775 ps
CPU time 31.15 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:30 PM PDT 24
Peak memory 200748 kb
Host smart-ad003d63-163a-4838-b5f7-d4ddea551aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44942579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.44942579
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2208594942
Short name T183
Test name
Test status
Simulation time 47630894 ps
CPU time 0.58 seconds
Started Aug 14 05:17:00 PM PDT 24
Finished Aug 14 05:17:01 PM PDT 24
Peak memory 197432 kb
Host smart-008cbcd0-6a46-4d64-9952-98f6cadb274f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208594942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2208594942
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3948314956
Short name T18
Test name
Test status
Simulation time 4186319973 ps
CPU time 31.19 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:29 PM PDT 24
Peak memory 200732 kb
Host smart-67af2e0d-b2a7-4ee6-bd18-8a4588600df6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3948314956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3948314956
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3364774373
Short name T213
Test name
Test status
Simulation time 2424354480 ps
CPU time 30.98 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:17:29 PM PDT 24
Peak memory 200768 kb
Host smart-c6ef54bd-8cc1-470a-8500-5ea14f50b9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364774373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3364774373
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4259935409
Short name T107
Test name
Test status
Simulation time 20803883298 ps
CPU time 398.79 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:23:37 PM PDT 24
Peak memory 478128 kb
Host smart-1233d622-bbf8-494b-bcf7-ebbd1da59261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259935409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4259935409
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2443346429
Short name T375
Test name
Test status
Simulation time 14855149287 ps
CPU time 162.18 seconds
Started Aug 14 05:16:57 PM PDT 24
Finished Aug 14 05:19:40 PM PDT 24
Peak memory 200776 kb
Host smart-d37f39a3-3556-4d0b-9c1e-a1602e06f8b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443346429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2443346429
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.254285275
Short name T304
Test name
Test status
Simulation time 12655902079 ps
CPU time 54.71 seconds
Started Aug 14 05:16:50 PM PDT 24
Finished Aug 14 05:17:45 PM PDT 24
Peak memory 200664 kb
Host smart-31805dd4-658d-47f1-8e2f-c8341bb01a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254285275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.254285275
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3510808619
Short name T369
Test name
Test status
Simulation time 115978688 ps
CPU time 1.32 seconds
Started Aug 14 05:16:51 PM PDT 24
Finished Aug 14 05:16:52 PM PDT 24
Peak memory 200628 kb
Host smart-3d6ece44-e73e-4b0e-acd6-2d1fa52648a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510808619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3510808619
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.4274558224
Short name T49
Test name
Test status
Simulation time 31699784116 ps
CPU time 868.15 seconds
Started Aug 14 05:16:58 PM PDT 24
Finished Aug 14 05:31:27 PM PDT 24
Peak memory 344564 kb
Host smart-eb01e99e-2f36-4fd4-b828-3bf5f6263e91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274558224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.4274558224
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.727484016
Short name T435
Test name
Test status
Simulation time 12276096300 ps
CPU time 77.46 seconds
Started Aug 14 05:16:59 PM PDT 24
Finished Aug 14 05:18:17 PM PDT 24
Peak memory 200744 kb
Host smart-75d9dc14-eb82-4d26-bc9c-380ca6490781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727484016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.727484016
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3636893939
Short name T511
Test name
Test status
Simulation time 14110365 ps
CPU time 0.6 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:15:14 PM PDT 24
Peak memory 196744 kb
Host smart-a46202d4-53e6-4ed4-a148-7bf147a77947
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636893939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3636893939
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1212470254
Short name T177
Test name
Test status
Simulation time 1309852305 ps
CPU time 33.57 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:15:47 PM PDT 24
Peak memory 200828 kb
Host smart-49cec5bd-e65d-40fb-8a61-442bf888071e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1212470254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1212470254
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1088439537
Short name T244
Test name
Test status
Simulation time 1132012000 ps
CPU time 60.72 seconds
Started Aug 14 05:15:11 PM PDT 24
Finished Aug 14 05:16:12 PM PDT 24
Peak memory 200608 kb
Host smart-2be67f5c-c90a-421f-bb5b-de426abc9bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088439537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1088439537
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3702679041
Short name T400
Test name
Test status
Simulation time 15507797861 ps
CPU time 706.97 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:27:00 PM PDT 24
Peak memory 703328 kb
Host smart-da647d77-fc9a-4bfb-89f4-c3b92c3c6785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3702679041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3702679041
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4256790283
Short name T430
Test name
Test status
Simulation time 301693982 ps
CPU time 5.7 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:15:22 PM PDT 24
Peak memory 200564 kb
Host smart-84e39235-1546-4c8c-a11f-2c5017946c6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256790283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4256790283
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2288706963
Short name T398
Test name
Test status
Simulation time 59888837559 ps
CPU time 98.67 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:16:43 PM PDT 24
Peak memory 200708 kb
Host smart-f0f911a5-cb93-4e4f-bf09-062ce3850996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288706963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2288706963
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3070308980
Short name T308
Test name
Test status
Simulation time 579725427 ps
CPU time 6.96 seconds
Started Aug 14 05:15:04 PM PDT 24
Finished Aug 14 05:15:11 PM PDT 24
Peak memory 200704 kb
Host smart-c5dc6d26-6205-4451-8698-279f62d9c3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070308980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3070308980
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1431453356
Short name T95
Test name
Test status
Simulation time 406670066643 ps
CPU time 1520.23 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:40:34 PM PDT 24
Peak memory 504332 kb
Host smart-ea0817ee-5dfa-47c9-88be-9b894679142a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431453356 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1431453356
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.35534176
Short name T320
Test name
Test status
Simulation time 1052400018 ps
CPU time 4.07 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:15:20 PM PDT 24
Peak memory 200548 kb
Host smart-6475b9ac-8cbf-4bd4-8aae-2554ce10fe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35534176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.35534176
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1389451795
Short name T359
Test name
Test status
Simulation time 57938127 ps
CPU time 0.57 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:15:17 PM PDT 24
Peak memory 195776 kb
Host smart-603d2474-4c26-42c1-b327-8dde3bd4dbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389451795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1389451795
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.317090979
Short name T251
Test name
Test status
Simulation time 609893625 ps
CPU time 34.11 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:15:48 PM PDT 24
Peak memory 200672 kb
Host smart-b0e3c4e3-8f8e-47c0-b014-91f348277988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317090979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.317090979
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3422973826
Short name T373
Test name
Test status
Simulation time 7488823637 ps
CPU time 13.55 seconds
Started Aug 14 05:15:17 PM PDT 24
Finished Aug 14 05:15:31 PM PDT 24
Peak memory 200740 kb
Host smart-3d54cfba-1683-4510-9843-8d79c8c4dfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422973826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3422973826
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1768218782
Short name T337
Test name
Test status
Simulation time 14742390319 ps
CPU time 259.39 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:19:36 PM PDT 24
Peak memory 598356 kb
Host smart-4ee26593-4b9a-45fc-b5ae-64c8dc9279b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1768218782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1768218782
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1336815106
Short name T331
Test name
Test status
Simulation time 15007007 ps
CPU time 0.78 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:15:14 PM PDT 24
Peak memory 197304 kb
Host smart-3633100f-697f-4bcd-a1c4-3fcb4bfbf60a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336815106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1336815106
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3561802642
Short name T467
Test name
Test status
Simulation time 82172583921 ps
CPU time 112.13 seconds
Started Aug 14 05:15:15 PM PDT 24
Finished Aug 14 05:17:07 PM PDT 24
Peak memory 200948 kb
Host smart-28facb26-1444-424b-a55a-ac970727fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561802642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3561802642
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2000097291
Short name T355
Test name
Test status
Simulation time 1231173829 ps
CPU time 7.91 seconds
Started Aug 14 05:15:10 PM PDT 24
Finished Aug 14 05:15:18 PM PDT 24
Peak memory 200692 kb
Host smart-afb121f0-7fe1-4875-b688-cd16b048317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000097291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2000097291
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.172856032
Short name T111
Test name
Test status
Simulation time 31441960907 ps
CPU time 284.78 seconds
Started Aug 14 05:15:12 PM PDT 24
Finished Aug 14 05:19:57 PM PDT 24
Peak memory 200752 kb
Host smart-f0bd4b60-44ef-45ad-8c98-8ed27eca19b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172856032 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.172856032
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1532738997
Short name T531
Test name
Test status
Simulation time 2079447169 ps
CPU time 56.98 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:16:10 PM PDT 24
Peak memory 200692 kb
Host smart-91b594ff-f9ee-4109-8331-5e1f65351549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532738997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1532738997
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.33977882
Short name T443
Test name
Test status
Simulation time 13061371 ps
CPU time 0.59 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:15:14 PM PDT 24
Peak memory 196784 kb
Host smart-160c5a4c-cb45-45f7-8683-2670708f7b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.33977882
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3033902146
Short name T272
Test name
Test status
Simulation time 1572430410 ps
CPU time 79.6 seconds
Started Aug 14 05:15:12 PM PDT 24
Finished Aug 14 05:16:32 PM PDT 24
Peak memory 200736 kb
Host smart-a69c2048-54e7-4b9e-8e45-d18f7fa6d521
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3033902146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3033902146
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1642663494
Short name T240
Test name
Test status
Simulation time 2440616858 ps
CPU time 26.95 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:15:41 PM PDT 24
Peak memory 200768 kb
Host smart-e65ee04f-c63a-4ee8-84fc-13b1829d4c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642663494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1642663494
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3217448587
Short name T332
Test name
Test status
Simulation time 1403433044 ps
CPU time 209.31 seconds
Started Aug 14 05:15:15 PM PDT 24
Finished Aug 14 05:18:45 PM PDT 24
Peak memory 458916 kb
Host smart-c8e9e5e7-15dc-465e-a2d8-cbeec7b46b96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3217448587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3217448587
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.516324659
Short name T167
Test name
Test status
Simulation time 212747524 ps
CPU time 11.64 seconds
Started Aug 14 05:15:12 PM PDT 24
Finished Aug 14 05:15:24 PM PDT 24
Peak memory 200628 kb
Host smart-f37d6e5d-347f-44c8-836a-c936f48521c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516324659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.516324659
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3337099216
Short name T43
Test name
Test status
Simulation time 3103695244 ps
CPU time 57.58 seconds
Started Aug 14 05:15:15 PM PDT 24
Finished Aug 14 05:16:13 PM PDT 24
Peak memory 200752 kb
Host smart-1d2eb566-2dd7-4425-9a8e-5ac46aad54e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337099216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3337099216
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1327141859
Short name T217
Test name
Test status
Simulation time 2011088161 ps
CPU time 12.62 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 200696 kb
Host smart-cc26137d-7891-4e90-a759-0ece7c11fa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327141859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1327141859
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2750103197
Short name T517
Test name
Test status
Simulation time 222522478 ps
CPU time 12.47 seconds
Started Aug 14 05:15:11 PM PDT 24
Finished Aug 14 05:15:24 PM PDT 24
Peak memory 200736 kb
Host smart-3cbf133b-06bc-4079-880d-5c85bb596266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750103197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2750103197
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1030406829
Short name T297
Test name
Test status
Simulation time 13738702 ps
CPU time 0.6 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 195724 kb
Host smart-21fd2fc3-cb1b-4525-9fb7-523d7c907b2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030406829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1030406829
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1821350179
Short name T13
Test name
Test status
Simulation time 5402092241 ps
CPU time 80.08 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:16:34 PM PDT 24
Peak memory 216952 kb
Host smart-eac467fd-37c9-42c1-9c51-207ffbd497b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821350179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1821350179
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.485697728
Short name T514
Test name
Test status
Simulation time 2185881314 ps
CPU time 39.19 seconds
Started Aug 14 05:15:13 PM PDT 24
Finished Aug 14 05:15:52 PM PDT 24
Peak memory 200640 kb
Host smart-1907f99f-8901-4789-ba11-818ce6fd9d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485697728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.485697728
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4087631791
Short name T411
Test name
Test status
Simulation time 16589423137 ps
CPU time 679.42 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:26:35 PM PDT 24
Peak memory 658080 kb
Host smart-46ee7f40-ea42-4e15-b19c-26b3483e74e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087631791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4087631791
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2010636547
Short name T100
Test name
Test status
Simulation time 1883103666 ps
CPU time 104.24 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:17:10 PM PDT 24
Peak memory 200688 kb
Host smart-2c312338-4509-41ca-a9d6-579e0225832b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010636547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2010636547
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3256107153
Short name T165
Test name
Test status
Simulation time 41927430279 ps
CPU time 138.69 seconds
Started Aug 14 05:15:16 PM PDT 24
Finished Aug 14 05:17:35 PM PDT 24
Peak memory 208900 kb
Host smart-fef57d31-5f37-4fa4-b0a5-e547e74d8c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256107153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3256107153
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.833717019
Short name T269
Test name
Test status
Simulation time 713854508 ps
CPU time 11.92 seconds
Started Aug 14 05:15:14 PM PDT 24
Finished Aug 14 05:15:26 PM PDT 24
Peak memory 200692 kb
Host smart-2b531783-6064-4998-a364-e5030da78b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833717019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.833717019
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2614948930
Short name T212
Test name
Test status
Simulation time 165440684603 ps
CPU time 1609.48 seconds
Started Aug 14 05:15:28 PM PDT 24
Finished Aug 14 05:42:18 PM PDT 24
Peak memory 738128 kb
Host smart-0ea713de-7230-4d81-ac13-fd0e7f353816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614948930 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2614948930
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3566423867
Short name T469
Test name
Test status
Simulation time 26814834101 ps
CPU time 36.88 seconds
Started Aug 14 05:15:27 PM PDT 24
Finished Aug 14 05:16:04 PM PDT 24
Peak memory 200736 kb
Host smart-1dd41efc-9386-4421-9d51-1e3fbacccd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566423867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3566423867
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.627077381
Short name T428
Test name
Test status
Simulation time 18557643 ps
CPU time 0.58 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 195780 kb
Host smart-f84ff81e-0659-448d-9fda-25edccc0eace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627077381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.627077381
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2037292416
Short name T482
Test name
Test status
Simulation time 4372020832 ps
CPU time 85.52 seconds
Started Aug 14 05:15:25 PM PDT 24
Finished Aug 14 05:16:50 PM PDT 24
Peak memory 200752 kb
Host smart-e4cc8156-6b76-47c3-836f-a3b60a8bef21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037292416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2037292416
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3532420054
Short name T161
Test name
Test status
Simulation time 3441475729 ps
CPU time 47.91 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:16:14 PM PDT 24
Peak memory 200744 kb
Host smart-7f817aa9-578a-47a0-9184-c66718068ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532420054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3532420054
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1178396137
Short name T256
Test name
Test status
Simulation time 8600438268 ps
CPU time 719.73 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:27:26 PM PDT 24
Peak memory 703832 kb
Host smart-510939ad-ec9c-4894-8690-c3fd1135f215
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178396137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1178396137
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.342957996
Short name T453
Test name
Test status
Simulation time 2206261059 ps
CPU time 124.45 seconds
Started Aug 14 05:15:25 PM PDT 24
Finished Aug 14 05:17:30 PM PDT 24
Peak memory 200608 kb
Host smart-80fa1948-ba15-4fdc-91f3-63b313aff04c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342957996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.342957996
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.630957036
Short name T344
Test name
Test status
Simulation time 12532553169 ps
CPU time 172 seconds
Started Aug 14 05:15:27 PM PDT 24
Finished Aug 14 05:18:19 PM PDT 24
Peak memory 217124 kb
Host smart-b05bc6c9-a359-4d5a-97fd-b7c944c81514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630957036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.630957036
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2032618143
Short name T343
Test name
Test status
Simulation time 730050082 ps
CPU time 12.98 seconds
Started Aug 14 05:15:25 PM PDT 24
Finished Aug 14 05:15:38 PM PDT 24
Peak memory 200744 kb
Host smart-f3dae994-bf65-4ec7-8fcd-cb2a872502ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032618143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2032618143
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2244008149
Short name T483
Test name
Test status
Simulation time 3075601027 ps
CPU time 161.51 seconds
Started Aug 14 05:15:26 PM PDT 24
Finished Aug 14 05:18:08 PM PDT 24
Peak memory 200756 kb
Host smart-edc4d767-e4bf-49e8-b654-e9a7fecbad34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244008149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2244008149
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3343758549
Short name T321
Test name
Test status
Simulation time 5308270377 ps
CPU time 65.75 seconds
Started Aug 14 05:15:24 PM PDT 24
Finished Aug 14 05:16:30 PM PDT 24
Peak memory 200720 kb
Host smart-978717ce-6cf5-47cf-8d76-5ad787caee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343758549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3343758549
Directory /workspace/9.hmac_wipe_secret/latest
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