Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16752805	1			T1	11287		T2	2042		T3	23822
all_values[1]	16752805	1			T1	11287		T2	2042		T3	23822
all_values[2]	16752805	1			T1	11287		T2	2042		T3	23822

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

233048

1

T1

1614

T9

718

T14

983

auto[1]

50025367

1

T1

32247

T2

6126

T3

71466

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42864356

1

T1

28199

T2

5246

T3

66437

auto[1]

7394059

1

T1

5662

T2

880

T3

5029

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82568	1			T9	716		T14	2		T17	734
all_values[0]	auto[0]	auto[1]	294	1			T9	2		T20	2		T21	6
all_values[0]	auto[1]	auto[0]	16651338	1			T1	11260		T2	2019		T3	23803
all_values[0]	auto[1]	auto[1]	18605	1			T1	27		T2	23		T3	19
all_values[1]	auto[0]	auto[0]	75609	1			T14	981		T16	2128		T5	2820
all_values[1]	auto[0]	auto[1]	176	1			T21	5		T6	2		T69	6
all_values[1]	auto[1]	auto[0]	16676776	1			T1	11287		T2	2042		T3	23822
all_values[1]	auto[1]	auto[1]	244	1			T21	4		T22	1		T6	2
all_values[2]	auto[0]	auto[0]	43123	1			T1	1614		T21	7		T135	2
all_values[2]	auto[0]	auto[1]	31278	1			T21	7		T135	2		T23	587
all_values[2]	auto[1]	auto[0]	9334942	1			T1	4038		T2	1185		T3	18812
all_values[2]	auto[1]	auto[1]	7343462	1			T1	5635		T2	857		T3	5010