Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107052

1

T1

40

T2

34

T3

16

auto[1]

108544

1

T1

28

T2

38

T3

14

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	81592	1			T1	34		T3	11		T4	15
len_1026_2046	4144	1			T2	4		T3	1		T4	3
len_514_1022	2553	1			T2	2		T16	2		T21	8
len_2_510	5224	1			T15	1		T21	47		T68	9
len_2056	150	1			T2	2		T20	3		T21	1
len_2048	281	1			T2	3		T3	1		T16	1
len_2040	198	1			T2	2		T61	2		T27	1
len_1032	126	1			T2	1		T20	5		T21	3
len_1024	1771	1			T2	3		T4	1		T15	1
len_1016	183	1			T2	3		T20	1		T155	1
len_520	224	1			T60	2		T62	3		T27	1
len_512	290	1			T2	1		T15	2		T20	3
len_504	138	1			T2	4		T20	1		T21	1
len_8	937	1			T5	3		T21	12		T135	4
len_0	9986	1			T2	11		T3	2		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

86

1

T47

2

T56

1

T64

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	41220	1			T1	20		T3	6		T4	9
auto[0]	len_1026_2046	2119	1			T2	2		T21	5		T68	4
auto[0]	len_514_1022	1777	1			T16	2		T21	4		T68	2
auto[0]	len_2_510	3403	1			T15	1		T21	46		T68	1
auto[0]	len_2056	92	1			T2	2		T20	1		T21	1
auto[0]	len_2048	157	1			T2	1		T3	1		T20	1
auto[0]	len_2040	104	1			T2	1		T61	2		T27	1
auto[0]	len_1032	64	1			T2	1		T20	3		T21	2
auto[0]	len_1024	250	1			T2	2		T4	1		T15	1
auto[0]	len_1016	97	1			T2	2		T155	1		T61	3
auto[0]	len_520	96	1			T60	2		T62	3		T27	1
auto[0]	len_512	158	1			T2	1		T15	1		T20	3
auto[0]	len_504	93	1			T2	2		T138	2		T60	1
auto[0]	len_8	25	1			T155	1		T97	1		T156	1
auto[0]	len_0	3870	1			T2	3		T3	1		T4	1
auto[1]	len_2050_plus	40372	1			T1	14		T3	5		T4	6
auto[1]	len_1026_2046	2025	1			T2	2		T3	1		T4	3
auto[1]	len_514_1022	776	1			T2	2		T21	4		T68	8
auto[1]	len_2_510	1821	1			T21	1		T68	8		T137	14
auto[1]	len_2056	58	1			T20	2		T60	2		T86	1
auto[1]	len_2048	124	1			T2	2		T16	1		T21	3
auto[1]	len_2040	94	1			T2	1		T102	1		T156	3
auto[1]	len_1032	62	1			T20	2		T21	1		T62	3
auto[1]	len_1024	1521	1			T2	1		T16	1		T20	1
auto[1]	len_1016	86	1			T2	1		T20	1		T60	1
auto[1]	len_520	128	1			T69	1		T100	2		T157	3
auto[1]	len_512	132	1			T15	1		T21	1		T68	1
auto[1]	len_504	45	1			T2	2		T20	1		T21	1
auto[1]	len_8	912	1			T5	3		T21	12		T135	4
auto[1]	len_0	6116	1			T2	8		T3	1		T14	3

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

46

1

T64

2

T19

1

T158

2

auto[1]

len_upper

40

1

T47

2

T56

1

T159

1