Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4237568

1

T1

27

T2

589

T3

7272

auto[1]

2517846

1

T1

13

T2

408

T3

4676

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2492808

1

T1

20

T2

279

T3

6533

auto[1]

4262606

1

T1

20

T2

718

T3

5415

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3093984

1

T1

23

T2

420

T3

7531

auto[1]

3661430

1

T1

17

T2

577

T3

4417

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4275604

1

T1

20

T2

531

T3

6097

auto[1]

2479810

1

T1

20

T2

466

T3

5851

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6048213	1			T1	29		T2	981		T3	11704
fifo_depth[1]	116915	1			T1	1		T2	10		T3	188
fifo_depth[2]	96443	1			T1	1		T2	5		T3	47
fifo_depth[3]	79945	1			T1	1		T2	1		T3	9
fifo_depth[4]	70382	1			T1	2		T4	183		T15	1
fifo_depth[5]	56410	1			T4	169		T5	133		T21	1033
fifo_depth[6]	44594	1			T1	1		T4	123		T5	104
fifo_depth[7]	29521	1			T4	82		T5	84		T21	487

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707201

1

T1

11

T2

16

T3

244

auto[1]

6048213

1

T1

29

T2

981

T3

11704

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6746666

1

T1

40

T2

997

T3

11948

auto[1]

8748

1

T21

44

T22

111

T84

77

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

22609

1

T3

8

T16

43

T21

225

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30185

1

T1

3

T3

79

T4

115

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30554

1

T1

2

T3

3

T4

356

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27947

1

T1

1

T3

9

T14

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

178897

1

T2

3

T3

38

T15

15

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

35296

1

T1

1

T3

18

T4

52

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

26618

1

T2

2

T3

47

T4

339

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21672

1

T16

24

T20

2

T21

109

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44173

1

T1

2

T2

3

T4

52

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29798

1

T3

10

T15

14

T16

83

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42699

1

T4

128

T16

1

T20

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

39845

1

T3

24

T16

6

T20

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

55161

1

T1

1

T2

2

T15

14

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

37987

1

T1

1

T4

236

T21

361

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

38716

1

T2

1

T3

8

T15

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

45044

1

T2

5

T4

14

T16

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

148852

1

T1

4

T2

22

T3

313

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

165797

1

T1

3

T2

25

T3

2149

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

150270

1

T2

1

T3

50

T4

613

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

144045

1

T1

1

T2

29

T3

185

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1645072

1

T1

2

T2

46

T3

1967

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

163831

1

T1

2

T2

138

T3

680

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

149840

1

T1

2

T2

78

T3

1985

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

152499

1

T1

2

T2

76

T4

442

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

413621

1

T1

2

T2

136

T3

231

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

368736

1

T1

1

T2

12

T3

1478

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

428555

1

T1

1

T2

49

T3

1104

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

405122

1

T2

2

T3

890

T4

335

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

462092

1

T1

3

T2

122

T4

638

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

435461

1

T1

2

T2

80

T3

301

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

437875

1

T1

1

T2

66

T3

343

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

376545

1

T1

3

T2

99

T3

28

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

170868

1

T1

4

T2

22

T3

321

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

195610

1

T1

6

T2

25

T3

2228

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

180266

1

T1

2

T2

1

T3

53

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

171617

1

T1

2

T2

29

T3

194

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1823391

1

T1

2

T2

49

T3

2005

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

198113

1

T1

3

T2

138

T3

698

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

175912

1

T1

2

T2

80

T3

2032

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

173443

1

T1

2

T2

76

T4

442

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

456880

1

T1

4

T2

139

T3

231

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

398347

1

T1

1

T2

12

T3

1488

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

470843

1

T1

1

T2

49

T3

1104

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

444609

1

T2

2

T3

914

T4

335

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

516614

1

T1

4

T2

124

T4

638

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

473128

1

T1

3

T2

80

T3

301

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

475966

1

T1

1

T2

67

T3

351

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

421059

1

T1

3

T2

104

T3

28

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

593

1

T22

1

T91

6

T96

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

372

1

T22

3

T91

3

T96

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

558

1

T22

40

T96

8

T7

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

375

1

T96

5

T162

19

T44

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

578

1

T7

50

T163

4

T164

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1014

1

T84

7

T7

70

T163

23

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

546

1

T22

64

T84

70

T163

10

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

728

1

T91

4

T162

9

T163

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

914

1

T163

178

T35

6

T25

30

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

187

1

T22

3

T163

94

T44

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

411

1

T91

29

T163

6

T165

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

358

1

T162

14

T163

130

T164

44

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

639

1

T21

44

T7

235

T44

32

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

320

1

T91

76

T165

3

T166

11

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

625

1

T156

7

T44

1

T167

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

530

1

T91

98

T44

308

T12

5

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

148852

1

T1

4

T2

22

T3

313

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

165797

1

T1

3

T2

25

T3

2149

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

150270

1

T2

1

T3

50

T4

613

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

144045

1

T1

1

T2

29

T3

185

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1645072

1

T1

2

T2

46

T3

1967

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

163831

1

T1

2

T2

138

T3

680

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

149840

1

T1

2

T2

78

T3

1985

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

152499

1

T1

2

T2

76

T4

442

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

413621

1

T1

2

T2

136

T3

231

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

368736

1

T1

1

T2

12

T3

1478

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

428555

1

T1

1

T2

49

T3

1104

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

405122

1

T2

2

T3

890

T4

335

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

462092

1

T1

3

T2

122

T4

638

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

435461

1

T1

2

T2

80

T3

301

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

437875

1

T1

1

T2

66

T3

343

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

376545

1

T1

3

T2

99

T3

28

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

2789

1

T3

4

T16

36

T21

44

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3219

1

T3

60

T4

21

T15

4

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3376

1

T3

3

T4

67

T16

17

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3256

1

T3

8

T14

5

T16

12

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

45624

1

T2

1

T3

30

T15

12

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3524

1

T3

14

T4

9

T15

13

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3008

1

T2

2

T3

34

T4

54

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

2851

1

T16

20

T20

2

T21

19

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5890

1

T1

1

T2

1

T4

3

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

4878

1

T3

8

T15

12

T16

68

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6092

1

T4

21

T20

3

T21

144

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5646

1

T3

21

T16

4

T20

1

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

8346

1

T2

1

T15

7

T16

9

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5739

1

T4

40

T21

59

T23

31

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6376

1

T2

1

T3

6

T15

12

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6301

1

T2

4

T4

1

T16

10

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2306

1

T3

3

T16

4

T21

38

fifo_depth[2]

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2463

1

T1

1

T3

17

T4

15

fifo_depth[2]

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auto[0]

2668

1

T4

62

T16

2

T21

189

fifo_depth[2]

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2524

1

T16

4

T21

36

T160

39

fifo_depth[2]

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auto[0]

auto[0]

35976

1

T2

2

T3

7

T15

2

fifo_depth[2]

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auto[0]

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2930

1

T3

4

T4

7

T15

3

fifo_depth[2]

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1

T3

10

T4

42

T15

2

fifo_depth[2]

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1

T16

4

T21

18

T160

37

fifo_depth[2]

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1

T2

1

T4

8

T5

65

fifo_depth[2]

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1

T3

2

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2

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12

fifo_depth[2]

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auto[0]

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1

T4

33

T16

1

T20

2

fifo_depth[2]

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auto[1]

auto[1]

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1

T3

3

T16

2

T21

94

fifo_depth[2]

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1

T2

1

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5

T16

2

fifo_depth[2]

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1

T4

45

T21

60

T23

33

fifo_depth[2]

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1

T3

1

T15

2

T21

46

fifo_depth[2]

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auto[1]

5811

1

T2

1

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3

T16

3

fifo_depth[3]

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auto[0]

auto[0]

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1

T3

1

T16

3

T21

42

fifo_depth[3]

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auto[0]

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2081

1

T3

2

T4

16

T21

118

fifo_depth[3]

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auto[0]

2246

1

T4

61

T21

188

T23

16

fifo_depth[3]

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1

T3

1

T16

2

T21

35

fifo_depth[3]

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1

T3

1

T15

1

T21

114

fifo_depth[3]

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auto[0]

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2340

1

T4

6

T16

4

T21

36

fifo_depth[3]

auto[0]

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auto[1]

auto[0]

1884

1

T3

3

T4

43

T21

86

fifo_depth[3]

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auto[1]

1640

1

T21

15

T160

12

T161

1

fifo_depth[3]

auto[1]

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auto[0]

auto[0]

4624

1

T2

1

T4

9

T5

66

fifo_depth[3]

auto[1]

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auto[0]

auto[1]

3449

1

T16

2

T20

1

T21

11

fifo_depth[3]

auto[1]

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auto[1]

auto[0]

4684

1

T4

26

T20

1

T21

149

fifo_depth[3]

auto[1]

auto[0]

auto[1]

auto[1]

4465

1

T20

1

T21

91

T135

74

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[0]

5579

1

T15

2

T16

1

T5

88

fifo_depth[3]

auto[1]

auto[1]

auto[0]

auto[1]

4598

1

T1

1

T4

52

T21

49

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[0]

4809

1

T3

1

T21

52

T135

116

fifo_depth[3]

auto[1]

auto[1]

auto[1]

auto[1]

5262

1

T4

3

T16

1

T21

87

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[0]

1914

1

T21

36

T137

8

T57

8

fifo_depth[4]

auto[0]

auto[0]

auto[0]

auto[1]

1963

1

T4

16

T21

112

T68

12

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[0]

2195

1

T1

1

T4

56

T16

1

fifo_depth[4]

auto[0]

auto[0]

auto[1]

auto[1]

2187

1

T21

34

T160

1

T47

1

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[0]

20746

1

T21

86

T68

11

T137

1

fifo_depth[4]

auto[0]

auto[1]

auto[0]

auto[1]

2353

1

T4

9

T15

1

T16

2

fifo_depth[4]

auto[0]

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auto[1]

auto[0]

1906

1

T4

51

T21

95

T68

4

fifo_depth[4]

auto[0]

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auto[1]

auto[1]

1668

1

T21

15

T160

1

T59

28

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[0]

4497

1

T4

7

T5

60

T21

125

fifo_depth[4]

auto[1]

auto[0]

auto[0]

auto[1]

3214

1

T16

1

T21

8

T47

2

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[0]

4604

1

T4

14

T21

146

T135

32

fifo_depth[4]

auto[1]

auto[0]

auto[1]

auto[1]

4089

1

T21

86

T68

10

T135

67

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[0]

5228

1

T1

1

T5

93

T21

160

fifo_depth[4]

auto[1]

auto[1]

auto[0]

auto[1]

4342

1

T4

29

T21

47

T23

28

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[0]

4594

1

T21

40

T135

123

T168

43

fifo_depth[4]

auto[1]

auto[1]

auto[1]

auto[1]

4882

1

T4

1

T21

69

T68

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[0]

1478

1

T21

27

T60

2

T27

1

fifo_depth[5]

auto[0]

auto[0]

auto[0]

auto[1]

1630

1

T4

14

T21

86

T68

7

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[0]

1751

1

T4

48

T21

147

T23

9

fifo_depth[5]

auto[0]

auto[0]

auto[1]

auto[1]

1671

1

T21

22

T59

7

T60

1

fifo_depth[5]

auto[0]

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auto[0]

auto[0]

14366

1

T21

66

T68

11

T155

1862

fifo_depth[5]

auto[0]

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auto[0]

auto[1]

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1

T4

7

T21

8

T137

3

fifo_depth[5]

auto[0]

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auto[0]

1501

1

T4

45

T21

82

T23

17

fifo_depth[5]

auto[0]

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1225

1

T21

15

T59

28

T60

2

fifo_depth[5]

auto[1]

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auto[0]

3871

1

T4

7

T5

52

T21

100

fifo_depth[5]

auto[1]

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2789

1

T21

9

T59

23

T22

4

fifo_depth[5]

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auto[0]

3863

1

T4

15

T21

120

T135

32

fifo_depth[5]

auto[1]

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auto[1]

3798

1

T21

85

T135

72

T168

89

fifo_depth[5]

auto[1]

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auto[0]

auto[0]

4390

1

T5

81

T21

135

T46

78

fifo_depth[5]

auto[1]

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auto[0]

auto[1]

3807

1

T4

31

T21

46

T23

17

fifo_depth[5]

auto[1]

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auto[1]

auto[0]

4071

1

T21

29

T135

97

T168

38

fifo_depth[5]

auto[1]

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auto[1]

auto[1]

4282

1

T4

2

T21

56

T68

3

fifo_depth[6]

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auto[0]

1043

1

T21

19

T137

2

T57

5

fifo_depth[6]

auto[0]

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auto[0]

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1449

1

T1

1

T4

11

T21

50

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[0]

1461

1

T4

33

T21

104

T23

7

fifo_depth[6]

auto[0]

auto[0]

auto[1]

auto[1]

1379

1

T21

18

T59

11

T60

2

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[0]

10188

1

T21

56

T68

8

T137

1

fifo_depth[6]

auto[0]

auto[1]

auto[0]

auto[1]

1614

1

T4

6

T21

14

T64

1

fifo_depth[6]

auto[0]

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auto[1]

auto[0]

1309

1

T4

45

T21

60

T23

12

fifo_depth[6]

auto[0]

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auto[1]

auto[1]

938

1

T21

11

T160

1

T59

11

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[0]

3356

1

T4

4

T5

44

T21

53

fifo_depth[6]

auto[1]

auto[0]

auto[0]

auto[1]

2305

1

T21

3

T169

1

T59

16

fifo_depth[6]

auto[1]

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auto[0]

3111

1

T4

6

T21

85

T135

28

fifo_depth[6]

auto[1]

auto[0]

auto[1]

auto[1]

3072

1

T21

74

T135

60

T168

91

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[0]

3626

1

T5

60

T21

115

T46

62

fifo_depth[6]

auto[1]

auto[1]

auto[0]

auto[1]

3038

1

T4

16

T21

40

T23

14

fifo_depth[6]

auto[1]

auto[1]

auto[1]

auto[0]

3199

1

T21

23

T135

86

T168

31

fifo_depth[6]

auto[1]

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auto[1]

auto[1]

3506

1

T4

2

T21

24

T68

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[0]

851

1

T21

9

T27

1

T22

1

fifo_depth[7]

auto[0]

auto[0]

auto[0]

auto[1]

1035

1

T4

7

T21

42

T68

2

fifo_depth[7]

auto[0]

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auto[1]

auto[0]

1144

1

T4

17

T21

57

T23

5

fifo_depth[7]

auto[0]

auto[0]

auto[1]

auto[1]

831

1

T21

7

T59

4

T69

1

fifo_depth[7]

auto[0]

auto[1]

auto[0]

auto[0]

6068

1

T21

46

T68

6

T155

851

fifo_depth[7]

auto[0]

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auto[0]

auto[1]

1146

1

T4

2

T21

6

T88

1

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[0]

949

1

T4

29

T21

34

T23

8

fifo_depth[7]

auto[0]

auto[1]

auto[1]

auto[1]

637

1

T21

6

T59

7

T61

1

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[0]

2258

1

T4

5

T5

37

T21

18

fifo_depth[7]

auto[1]

auto[0]

auto[0]

auto[1]

1520

1

T21

2

T59

5

T22

17

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[0]

2055

1

T4

10

T21

38

T135

24

fifo_depth[7]

auto[1]

auto[0]

auto[1]

auto[1]

2034

1

T21

58

T135

56

T168

58

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[0]

2526

1

T5

47

T21

95

T46

46

fifo_depth[7]

auto[1]

auto[1]

auto[0]

auto[1]

2000

1

T4

11

T21

27

T23

6

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[0]

2165

1

T21

16

T135

48

T168

26

fifo_depth[7]

auto[1]

auto[1]

auto[1]

auto[1]

2302

1

T4

1

T21

26

T168

5