Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16752805	1			T1	11287		T2	2042		T3	23822
all_pins[1]	16752805	1			T1	11287		T2	2042		T3	23822
all_pins[2]	16752805	1			T1	11287		T2	2042		T3	23822

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42895312	1			T1	28197		T2	5246		T3	66435
values[0x1]	7363103	1			T1	5664		T2	880		T3	5031
transitions[0x0=>0x1]	7362972	1			T1	5664		T2	880		T3	5031
transitions[0x1=>0x0]	7362983	1			T1	5664		T2	880		T3	5031

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16733422	1			T1	11258		T2	2019		T3	23801
all_pins[0]	values[0x1]	19383	1			T1	29		T2	23		T3	21
all_pins[0]	transitions[0x0=>0x1]	19328	1			T1	29		T2	23		T3	21
all_pins[0]	transitions[0x1=>0x0]	7343418	1			T1	5635		T2	857		T3	5010
all_pins[1]	values[0x0]	16752547	1			T1	11287		T2	2042		T3	23822
all_pins[1]	values[0x1]	258	1			T21	4		T22	2		T6	2
all_pins[1]	transitions[0x0=>0x1]	222	1			T21	3		T22	2		T6	2
all_pins[1]	transitions[0x1=>0x0]	19347	1			T1	29		T2	23		T3	21
all_pins[2]	values[0x0]	9409343	1			T1	5652		T2	1185		T3	18812
all_pins[2]	values[0x1]	7343462	1			T1	5635		T2	857		T3	5010
all_pins[2]	transitions[0x0=>0x1]	7343422	1			T1	5635		T2	857		T3	5010
all_pins[2]	transitions[0x1=>0x0]	218	1			T21	3		T22	2		T6	1