Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 796 1 T21 24 T6 10 T69 17
all_values[1] 796 1 T21 24 T6 10 T69 17
all_values[2] 796 1 T21 24 T6 10 T69 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1231 1 T21 40 T6 15 T69 30
auto[1] 1157 1 T21 32 T6 15 T69 21


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 889 1 T21 23 T6 8 T69 14
auto[1] 1499 1 T21 49 T6 22 T69 37


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1387 1 T21 38 T6 16 T69 28
auto[1] 1001 1 T21 34 T6 14 T69 23


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 151 1 T21 3 T6 1 T69 1
all_values[0] auto[0] auto[0] auto[1] 73 1 T21 2 T6 1 T69 2
all_values[0] auto[0] auto[1] auto[0] 151 1 T21 5 T6 2 T142 1
all_values[0] auto[0] auto[1] auto[1] 80 1 T21 3 T6 1 T69 4
all_values[0] auto[1] auto[0] auto[1] 186 1 T21 7 T6 2 T69 3
all_values[0] auto[1] auto[1] auto[1] 155 1 T21 4 T6 3 T69 7
all_values[1] auto[0] auto[0] auto[0] 135 1 T21 5 T6 2 T69 3
all_values[1] auto[0] auto[0] auto[1] 101 1 T21 4 T6 2 T69 3
all_values[1] auto[0] auto[1] auto[0] 120 1 T21 5 T69 2 T142 1
all_values[1] auto[0] auto[1] auto[1] 101 1 T21 1 T6 2 T69 1
all_values[1] auto[1] auto[0] auto[1] 176 1 T21 6 T6 3 T69 7
all_values[1] auto[1] auto[1] auto[1] 163 1 T21 3 T6 1 T69 1
all_values[2] auto[0] auto[0] auto[0] 179 1 T21 3 T6 1 T69 4
all_values[2] auto[0] auto[0] auto[1] 67 1 T21 3 T6 1 T69 3
all_values[2] auto[0] auto[1] auto[0] 153 1 T21 2 T6 2 T69 4
all_values[2] auto[0] auto[1] auto[1] 76 1 T21 2 T6 1 T69 1
all_values[2] auto[1] auto[0] auto[1] 163 1 T21 7 T6 2 T69 4
all_values[2] auto[1] auto[1] auto[1] 158 1 T21 7 T6 3 T69 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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