Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3802	1			T1	8		T2	9		T3	3
sha2_none	3977	1			T1	8		T2	5		T3	5
sha2_512	7080	1			T1	8		T2	4		T3	11
sha2_384	6949	1			T1	8		T2	15		T3	4
sha2_256	5871	1			T1	8		T2	14		T3	4

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17732

1

T1

27

T2

28

T3

17

auto[1]

10333

1

T1

13

T2

21

T3

10

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10220

1

T1

20

T2

17

T3

14

auto[1]

17845

1

T1

20

T2

32

T3

13

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14378

1

T1

17

T2

29

T3

13

disabled

13687

1

T1

23

T2

20

T3

14

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4245	1			T1	7		T2	9		T3	5
key_none	7585	1			T1	1		T2	10		T3	4
key_1024	4070	1			T1	6		T2	7		T3	5
key_512	3506	1			T1	7		T2	3		T3	2
key_384	3076	1			T1	5		T2	5		T3	3
key_256	2764	1			T1	8		T2	8		T3	3
key_128	2731	1			T1	6		T2	7		T3	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17875

1

T1

20

T2

26

T3

10

auto[1]

10190

1

T1

20

T2

23

T3

17

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27900

1

T1

40

T2

49

T3

27

disabled

165

1

T14

1

T17

3

T21

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1476

1

T1

4

T2

6

T3

1

enabled

auto[0]

auto[0]

auto[1]

1409

1

T1

1

T2

1

T3

5

enabled

auto[0]

auto[1]

auto[0]

1464

1

T1

1

T2

3

T3

1

enabled

auto[0]

auto[1]

auto[1]

1427

1

T2

2

T3

2

T4

2

enabled

auto[1]

auto[0]

auto[0]

4162

1

T1

4

T2

4

T4

2

enabled

auto[1]

auto[0]

auto[1]

1410

1

T1

3

T2

6

T3

2

enabled

auto[1]

auto[1]

auto[0]

1562

1

T1

1

T2

4

T3

1

enabled

auto[1]

auto[1]

auto[1]

1468

1

T1

3

T2

3

T3

1

disabled

auto[0]

auto[0]

auto[0]

1080

1

T1

4

T2

2

T3

1

disabled

auto[0]

auto[0]

auto[1]

1148

1

T1

6

T2

1

T3

2

disabled

auto[0]

auto[1]

auto[0]

1145

1

T1

2

T2

1

T3

1

disabled

auto[0]

auto[1]

auto[1]

1071

1

T1

2

T2

1

T3

1

disabled

auto[1]

auto[0]

auto[0]

5893

1

T1

2

T2

3

T3

2

disabled

auto[1]

auto[0]

auto[1]

1154

1

T1

3

T2

5

T3

4

disabled

auto[1]

auto[1]

auto[0]

1093

1

T1

2

T2

3

T3

3

disabled

auto[1]

auto[1]

auto[1]

1103

1

T1

2

T2

4

T4

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14310

1

T1

17

T2

29

T3

13

enabled

disabled

68

1

T21

1

T74

1

T69

2

disabled

disabled

97

1

T14

1

T17

3

T21

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13590

1

T1

23

T2

20

T3

14

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1007	1			T1	2		T4	2		T16	2
key_invalid	sha2_none	837	1			T1	1		T9	1		T17	1
key_invalid	sha2_512	680	1			T3	4		T4	1		T15	2
key_invalid	sha2_384	780	1			T1	3		T2	6		T3	1
key_invalid	sha2_256	835	1			T1	1		T2	3		T4	2
key_none	sha2_invalid	481	1			T1	1		T2	3		T4	3
key_none	sha2_none	541	1			T2	2		T3	1		T4	1
key_none	sha2_512	2489	1			T3	2		T4	1		T16	1
key_none	sha2_384	2498	1			T2	1		T3	1		T4	1
key_none	sha2_256	1539	1			T2	4		T4	1		T15	2
key_1024	sha2_invalid	447	1			T1	1		T2	3		T3	1
key_1024	sha2_none	525	1			T1	1		T2	1		T3	2
key_1024	sha2_512	1676	1			T1	1		T2	1		T4	1
key_1024	sha2_384	864	1			T1	1		T2	1		T3	1
key_512	sha2_invalid	459	1			T1	1		T2	1		T16	2
key_512	sha2_none	513	1			T3	1		T4	3		T21	9
key_512	sha2_512	543	1			T1	2		T2	1		T9	1
key_512	sha2_384	1140	1			T1	2		T14	2		T16	1
key_512	sha2_256	798	1			T1	2		T2	1		T3	1
key_384	sha2_invalid	453	1			T1	1		T3	1		T9	1
key_384	sha2_none	485	1			T1	1		T2	1		T4	1
key_384	sha2_512	537	1			T1	1		T3	1		T16	2
key_384	sha2_384	548	1			T4	1		T15	1		T17	1
key_384	sha2_256	1008	1			T1	2		T2	2		T3	1
key_256	sha2_invalid	468	1			T1	2		T2	2		T15	1
key_256	sha2_none	525	1			T1	2		T2	1		T15	1
key_256	sha2_512	573	1			T1	3		T2	2		T3	2
key_256	sha2_384	536	1			T1	1		T2	3		T16	1
key_256	sha2_256	615	1			T3	1		T15	2		T17	1
key_128	sha2_invalid	466	1			T3	1		T16	1		T21	6
key_128	sha2_none	533	1			T1	3		T3	1		T15	1
key_128	sha2_512	565	1			T1	1		T3	2		T4	1
key_128	sha2_384	568	1			T1	1		T2	4		T3	1
key_128	sha2_256	547	1			T1	1		T2	3		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

515

1

T1

2

T2

1

T3

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1007	1			T1	2		T4	2		T16	2
key_invalid	sha2_none	837	1			T1	1		T9	1		T17	1
key_invalid	sha2_512	680	1			T3	4		T4	1		T15	2
key_invalid	sha2_384	780	1			T1	3		T2	6		T3	1
key_invalid	sha2_256	835	1			T1	1		T2	3		T4	2
key_none	sha2_invalid	481	1			T1	1		T2	3		T4	3
key_none	sha2_none	541	1			T2	2		T3	1		T4	1
key_none	sha2_512	2489	1			T3	2		T4	1		T16	1
key_none	sha2_384	2498	1			T2	1		T3	1		T4	1
key_none	sha2_256	1539	1			T2	4		T4	1		T15	2
key_1024	sha2_invalid	447	1			T1	1		T2	3		T3	1
key_1024	sha2_none	525	1			T1	1		T2	1		T3	2
key_1024	sha2_512	1676	1			T1	1		T2	1		T4	1
key_1024	sha2_384	864	1			T1	1		T2	1		T3	1
key_1024	sha2_256	515	1			T1	2		T2	1		T3	1
key_512	sha2_invalid	459	1			T1	1		T2	1		T16	2
key_512	sha2_none	513	1			T3	1		T4	3		T21	9
key_512	sha2_512	543	1			T1	2		T2	1		T9	1
key_512	sha2_384	1140	1			T1	2		T14	2		T16	1
key_512	sha2_256	798	1			T1	2		T2	1		T3	1
key_384	sha2_invalid	453	1			T1	1		T3	1		T9	1
key_384	sha2_none	485	1			T1	1		T2	1		T4	1
key_384	sha2_512	537	1			T1	1		T3	1		T16	2
key_384	sha2_384	548	1			T4	1		T15	1		T17	1
key_384	sha2_256	1008	1			T1	2		T2	2		T3	1
key_256	sha2_invalid	468	1			T1	2		T2	2		T15	1
key_256	sha2_none	525	1			T1	2		T2	1		T15	1
key_256	sha2_512	573	1			T1	3		T2	2		T3	2
key_256	sha2_384	536	1			T1	1		T2	3		T16	1
key_256	sha2_256	615	1			T3	1		T15	2		T17	1
key_128	sha2_invalid	466	1			T3	1		T16	1		T21	6
key_128	sha2_none	533	1			T1	3		T3	1		T15	1
key_128	sha2_512	565	1			T1	1		T3	2		T4	1
key_128	sha2_384	568	1			T1	1		T2	4		T3	1
key_128	sha2_256	547	1			T1	1		T2	3		T4	2