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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 654
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T73 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1919063686 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:40 PM PDT 24 99982504 ps
T67 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2946450315 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:40 PM PDT 24 152369008 ps
T538 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1358179133 Aug 15 04:50:55 PM PDT 24 Aug 15 04:50:56 PM PDT 24 14358342 ps
T92 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2012252571 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:38 PM PDT 24 196794300 ps
T129 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.333666894 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:40 PM PDT 24 158871578 ps
T130 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3483671588 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:39 PM PDT 24 41315740 ps
T539 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2997499622 Aug 15 04:50:44 PM PDT 24 Aug 15 04:50:46 PM PDT 24 145128604 ps
T540 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3400294171 Aug 15 04:50:47 PM PDT 24 Aug 15 04:50:50 PM PDT 24 111465255 ps
T541 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4162508086 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:42 PM PDT 24 218824180 ps
T542 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4239521736 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:38 PM PDT 24 1094271206 ps
T143 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1279460126 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:53 PM PDT 24 627037725 ps
T543 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.300700649 Aug 15 04:50:31 PM PDT 24 Aug 15 04:50:36 PM PDT 24 474866662 ps
T144 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4199210943 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:41 PM PDT 24 385774270 ps
T544 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3033501764 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:48 PM PDT 24 13299781 ps
T545 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3778372513 Aug 15 04:50:27 PM PDT 24 Aug 15 04:50:39 PM PDT 24 4378441733 ps
T546 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1223268606 Aug 15 04:50:42 PM PDT 24 Aug 15 04:50:44 PM PDT 24 73571686 ps
T547 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1419152169 Aug 15 04:50:46 PM PDT 24 Aug 15 04:50:47 PM PDT 24 29379848 ps
T548 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3184466083 Aug 15 04:50:41 PM PDT 24 Aug 15 04:50:45 PM PDT 24 74534221 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.144856488 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:40 PM PDT 24 56355780 ps
T113 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.400153266 Aug 15 04:50:32 PM PDT 24 Aug 15 04:50:42 PM PDT 24 442892682 ps
T549 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2165454357 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:50 PM PDT 24 12739733 ps
T550 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3910400738 Aug 15 04:50:33 PM PDT 24 Aug 15 05:05:35 PM PDT 24 249920006916 ps
T154 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2552037122 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:40 PM PDT 24 152436919 ps
T551 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4250209281 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:38 PM PDT 24 29218963 ps
T552 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3855113836 Aug 15 04:50:51 PM PDT 24 Aug 15 04:50:52 PM PDT 24 62797846 ps
T131 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1702908646 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:37 PM PDT 24 216104542 ps
T132 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4064110104 Aug 15 04:50:47 PM PDT 24 Aug 15 04:50:49 PM PDT 24 135261646 ps
T553 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1440357056 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:45 PM PDT 24 1932754648 ps
T554 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1423827545 Aug 15 04:50:46 PM PDT 24 Aug 15 04:50:47 PM PDT 24 49730473 ps
T145 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1156994749 Aug 15 04:50:45 PM PDT 24 Aug 15 04:50:49 PM PDT 24 100074873 ps
T555 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3322234781 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 170196065 ps
T556 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1411583275 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:36 PM PDT 24 50371474 ps
T557 /workspace/coverage/cover_reg_top/40.hmac_intr_test.1209094577 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 23022913 ps
T558 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1047741262 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:37 PM PDT 24 148619477 ps
T114 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.134148779 Aug 15 04:50:31 PM PDT 24 Aug 15 04:50:31 PM PDT 24 57907797 ps
T133 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2188146170 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:50 PM PDT 24 73321756 ps
T559 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3193089744 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:36 PM PDT 24 124218223 ps
T115 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3918562481 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:41 PM PDT 24 2149780440 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1154045869 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:39 PM PDT 24 13284562 ps
T561 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3057521141 Aug 15 04:50:47 PM PDT 24 Aug 15 04:50:48 PM PDT 24 50385743 ps
T134 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2462792802 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:37 PM PDT 24 35011786 ps
T562 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.633521291 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:40 PM PDT 24 161022696 ps
T563 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.685437418 Aug 15 04:50:51 PM PDT 24 Aug 15 04:50:52 PM PDT 24 38046818 ps
T564 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3595508856 Aug 15 04:50:44 PM PDT 24 Aug 15 04:50:48 PM PDT 24 478007468 ps
T565 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1835260040 Aug 15 04:50:47 PM PDT 24 Aug 15 04:50:48 PM PDT 24 13884407 ps
T566 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2825981323 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:52 PM PDT 24 75594420 ps
T116 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1916310638 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:51 PM PDT 24 14667513 ps
T567 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3559186378 Aug 15 04:50:52 PM PDT 24 Aug 15 04:50:53 PM PDT 24 47324212 ps
T117 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4198778343 Aug 15 04:50:32 PM PDT 24 Aug 15 04:50:33 PM PDT 24 52605340 ps
T149 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2505294340 Aug 15 04:50:28 PM PDT 24 Aug 15 04:50:29 PM PDT 24 61158131 ps
T568 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3588089293 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 57298779 ps
T569 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.845681055 Aug 15 04:50:44 PM PDT 24 Aug 15 04:50:46 PM PDT 24 101082908 ps
T570 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3510383530 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:38 PM PDT 24 77938560 ps
T147 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4228829322 Aug 15 04:50:28 PM PDT 24 Aug 15 04:50:30 PM PDT 24 317958663 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1122683009 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:37 PM PDT 24 43712829 ps
T572 /workspace/coverage/cover_reg_top/34.hmac_intr_test.351341722 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:51 PM PDT 24 54284532 ps
T573 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2182239391 Aug 15 04:50:42 PM PDT 24 Aug 15 04:50:44 PM PDT 24 63418177 ps
T574 /workspace/coverage/cover_reg_top/11.hmac_intr_test.488829631 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:39 PM PDT 24 33241747 ps
T575 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.158856706 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:39 PM PDT 24 43336383 ps
T576 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1434745392 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:40 PM PDT 24 32064409 ps
T577 /workspace/coverage/cover_reg_top/1.hmac_intr_test.600828864 Aug 15 04:50:30 PM PDT 24 Aug 15 04:50:30 PM PDT 24 40884887 ps
T578 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1835312994 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 122982819 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1370436928 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:40 PM PDT 24 30003638 ps
T579 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3259560777 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:39 PM PDT 24 56896117 ps
T580 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1462032148 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:37 PM PDT 24 295598339 ps
T119 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1523116826 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:40 PM PDT 24 28754828 ps
T581 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2903716492 Aug 15 04:50:54 PM PDT 24 Aug 15 04:50:55 PM PDT 24 14226694 ps
T582 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2994433500 Aug 15 04:50:48 PM PDT 24 Aug 15 04:59:32 PM PDT 24 52794612136 ps
T120 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1940056457 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:37 PM PDT 24 105326151 ps
T583 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3539954996 Aug 15 04:50:43 PM PDT 24 Aug 15 04:50:44 PM PDT 24 213701286 ps
T584 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2715687634 Aug 15 04:50:45 PM PDT 24 Aug 15 04:50:48 PM PDT 24 179262936 ps
T585 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2913493096 Aug 15 04:50:32 PM PDT 24 Aug 15 04:50:33 PM PDT 24 56073048 ps
T586 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2500731730 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:35 PM PDT 24 370370460 ps
T587 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2645882782 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:36 PM PDT 24 340257674 ps
T121 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1593108373 Aug 15 04:50:27 PM PDT 24 Aug 15 04:50:33 PM PDT 24 1339280977 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.209599193 Aug 15 04:50:44 PM PDT 24 Aug 15 04:50:45 PM PDT 24 66450703 ps
T122 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3431879026 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:37 PM PDT 24 85873840 ps
T589 /workspace/coverage/cover_reg_top/6.hmac_intr_test.1819505043 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:37 PM PDT 24 44702172 ps
T590 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3073468442 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:39 PM PDT 24 218885155 ps
T123 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4222001085 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:51 PM PDT 24 3803189953 ps
T591 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1182476710 Aug 15 04:50:32 PM PDT 24 Aug 15 04:50:33 PM PDT 24 11353142 ps
T592 /workspace/coverage/cover_reg_top/13.hmac_intr_test.822867809 Aug 15 04:50:42 PM PDT 24 Aug 15 04:50:42 PM PDT 24 36495104 ps
T593 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2417349291 Aug 15 04:50:46 PM PDT 24 Aug 15 04:50:50 PM PDT 24 192801979 ps
T594 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2400631315 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:39 PM PDT 24 129560501 ps
T595 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.915154842 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:34 PM PDT 24 64142395 ps
T596 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1017306582 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:39 PM PDT 24 534719780 ps
T597 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4250188291 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:37 PM PDT 24 483210687 ps
T598 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3291879808 Aug 15 04:50:54 PM PDT 24 Aug 15 04:50:56 PM PDT 24 166282368 ps
T599 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3371929118 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:40 PM PDT 24 213881405 ps
T148 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2877192011 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:39 PM PDT 24 392347073 ps
T600 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1364882882 Aug 15 04:50:55 PM PDT 24 Aug 15 04:50:56 PM PDT 24 25794811 ps
T151 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.787665928 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:55 PM PDT 24 137411708 ps
T601 /workspace/coverage/cover_reg_top/28.hmac_intr_test.836192953 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 11829056 ps
T602 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1904223614 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:35 PM PDT 24 226317377 ps
T603 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3934223038 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:38 PM PDT 24 784402963 ps
T604 /workspace/coverage/cover_reg_top/4.hmac_intr_test.757455375 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:34 PM PDT 24 11409404 ps
T605 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3273267172 Aug 15 04:50:34 PM PDT 24 Aug 15 04:50:35 PM PDT 24 30565751 ps
T606 /workspace/coverage/cover_reg_top/24.hmac_intr_test.866927256 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 60199536 ps
T607 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3989451679 Aug 15 04:50:42 PM PDT 24 Aug 15 04:50:44 PM PDT 24 150474260 ps
T608 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3312067409 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:41 PM PDT 24 1440857496 ps
T609 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1157531113 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 13963467 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2294861616 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:39 PM PDT 24 48040024 ps
T611 /workspace/coverage/cover_reg_top/37.hmac_intr_test.666761948 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 19190765 ps
T612 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3927124658 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 15331592 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1570133348 Aug 15 04:50:33 PM PDT 24 Aug 15 04:50:34 PM PDT 24 35134685 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4029512284 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:51 PM PDT 24 13271715 ps
T615 /workspace/coverage/cover_reg_top/14.hmac_intr_test.927868579 Aug 15 04:50:45 PM PDT 24 Aug 15 04:50:46 PM PDT 24 38033808 ps
T616 /workspace/coverage/cover_reg_top/26.hmac_intr_test.925219037 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:49 PM PDT 24 154935466 ps
T617 /workspace/coverage/cover_reg_top/43.hmac_intr_test.4042713088 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 11852986 ps
T618 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3521334579 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:40 PM PDT 24 448410140 ps
T619 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1774293147 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:43 PM PDT 24 263630209 ps
T146 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3173717032 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:43 PM PDT 24 238120117 ps
T620 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2885637471 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 11948744 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1548292572 Aug 15 04:50:40 PM PDT 24 Aug 15 04:50:44 PM PDT 24 1366944813 ps
T124 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2565807955 Aug 15 04:50:31 PM PDT 24 Aug 15 04:50:39 PM PDT 24 322538195 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_intr_test.250309100 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:36 PM PDT 24 24353347 ps
T623 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2611070735 Aug 15 04:50:40 PM PDT 24 Aug 15 04:50:41 PM PDT 24 216605458 ps
T624 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3230700422 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:51 PM PDT 24 532292224 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3064101235 Aug 15 04:50:29 PM PDT 24 Aug 15 04:50:34 PM PDT 24 920840967 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1159851494 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:40 PM PDT 24 57032633 ps
T627 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4245637205 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:41 PM PDT 24 283063145 ps
T125 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2578939028 Aug 15 04:50:45 PM PDT 24 Aug 15 04:50:46 PM PDT 24 30343681 ps
T628 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3851728334 Aug 15 04:50:52 PM PDT 24 Aug 15 04:50:53 PM PDT 24 32883197 ps
T126 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2417632674 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:38 PM PDT 24 18937814 ps
T629 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1363205154 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:53 PM PDT 24 477052065 ps
T630 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1053152187 Aug 15 04:50:46 PM PDT 24 Aug 15 04:50:48 PM PDT 24 151379457 ps
T631 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2234247212 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:42 PM PDT 24 351275142 ps
T632 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2567662495 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:50 PM PDT 24 41233003 ps
T633 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.847773728 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:40 PM PDT 24 44799527 ps
T150 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.393790540 Aug 15 04:50:38 PM PDT 24 Aug 15 04:50:42 PM PDT 24 249232745 ps
T152 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1543296396 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:54 PM PDT 24 429069793 ps
T634 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.565612820 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:38 PM PDT 24 133798754 ps
T635 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1649566098 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 11613342 ps
T636 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2929018604 Aug 15 04:50:39 PM PDT 24 Aug 15 04:50:40 PM PDT 24 22887064 ps
T637 /workspace/coverage/cover_reg_top/42.hmac_intr_test.225331937 Aug 15 04:50:50 PM PDT 24 Aug 15 04:50:51 PM PDT 24 29253558 ps
T127 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.52704500 Aug 15 04:50:30 PM PDT 24 Aug 15 04:50:31 PM PDT 24 78498581 ps
T153 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.508075735 Aug 15 04:50:40 PM PDT 24 Aug 15 04:50:44 PM PDT 24 2965291404 ps
T638 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.567101541 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 125162110 ps
T639 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3528938645 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:38 PM PDT 24 43895577 ps
T640 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1184136295 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 18163842 ps
T641 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1034871438 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:36 PM PDT 24 40343063 ps
T642 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.891381291 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:40 PM PDT 24 302542729 ps
T643 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3970339128 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:40 PM PDT 24 70720932 ps
T644 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2159428741 Aug 15 04:50:48 PM PDT 24 Aug 15 04:50:49 PM PDT 24 15653166 ps
T645 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.719778596 Aug 15 04:50:51 PM PDT 24 Aug 15 04:50:52 PM PDT 24 45502868 ps
T646 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1852080135 Aug 15 04:50:55 PM PDT 24 Aug 15 04:50:56 PM PDT 24 39691853 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2900097023 Aug 15 04:50:35 PM PDT 24 Aug 15 04:50:36 PM PDT 24 36747488 ps
T648 /workspace/coverage/cover_reg_top/31.hmac_intr_test.997206848 Aug 15 04:50:55 PM PDT 24 Aug 15 04:50:56 PM PDT 24 13972547 ps
T649 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1965036482 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:38 PM PDT 24 407373481 ps
T650 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.559597100 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:39 PM PDT 24 90025186 ps
T651 /workspace/coverage/cover_reg_top/47.hmac_intr_test.780057011 Aug 15 04:50:47 PM PDT 24 Aug 15 04:50:48 PM PDT 24 13574499 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2529262167 Aug 15 04:50:36 PM PDT 24 Aug 15 04:50:39 PM PDT 24 247104797 ps
T653 /workspace/coverage/cover_reg_top/39.hmac_intr_test.819689653 Aug 15 04:50:49 PM PDT 24 Aug 15 04:50:50 PM PDT 24 45628379 ps
T654 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3711613400 Aug 15 04:50:37 PM PDT 24 Aug 15 04:50:38 PM PDT 24 154662710 ps

Test location /workspace/coverage/default/48.hmac_long_msg.400731224
Short name T4
Test name
Test status
Simulation time 2188649640 ps
CPU time 118.6 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 200528 kb
Host smart-3af5b236-db7f-44d4-8d4c-8e0acc10d8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400731224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.400731224
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_stress_all.151647070
Short name T21
Test name
Test status
Simulation time 44428928712 ps
CPU time 1531.79 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:56:38 PM PDT 24
Peak memory 503764 kb
Host smart-ac177847-b51f-4aea-8945-5f7dfb82128e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151647070 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.151647070
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1283026045
Short name T13
Test name
Test status
Simulation time 25915755539 ps
CPU time 302.9 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:35:19 PM PDT 24
Peak memory 465324 kb
Host smart-f5ef349a-2298-486f-b9c8-ead4c78a4d49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1283026045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1283026045
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.873083736
Short name T7
Test name
Test status
Simulation time 12185743496 ps
CPU time 580.61 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:40:10 PM PDT 24
Peak memory 702632 kb
Host smart-7a8e8388-8128-4164-a1ee-dc04eefadba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=873083736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.873083736
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2403007030
Short name T65
Test name
Test status
Simulation time 595391696 ps
CPU time 3.09 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 200192 kb
Host smart-44db9ebc-5bca-4f61-ba51-b0d6d9a485f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403007030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2403007030
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1558515316
Short name T52
Test name
Test status
Simulation time 81948122 ps
CPU time 0.97 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:30:10 PM PDT 24
Peak memory 219784 kb
Host smart-e3a247c8-04d9-4cbd-b904-c42558e1c71d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558515316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1558515316
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.535229223
Short name T47
Test name
Test status
Simulation time 8380359837 ps
CPU time 58.98 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 208744 kb
Host smart-430575b4-758f-4112-8ce0-441d11ba84ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535229223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.535229223
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2191240696
Short name T26
Test name
Test status
Simulation time 23961535198 ps
CPU time 2117.22 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 05:06:03 PM PDT 24
Peak memory 760408 kb
Host smart-a97516e2-f68c-4792-b8f7-d0b8dd157324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191240696 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2191240696
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.4198778343
Short name T117
Test name
Test status
Simulation time 52605340 ps
CPU time 0.89 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 199876 kb
Host smart-dde4f1fe-c84e-4adf-b90d-133adad25a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198778343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.4198778343
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/4.hmac_smoke.774689251
Short name T102
Test name
Test status
Simulation time 6703530544 ps
CPU time 14.12 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:22 PM PDT 24
Peak memory 200592 kb
Host smart-94ae9026-3c46-4447-af60-8fae8982e370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774689251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.774689251
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.789639238
Short name T11
Test name
Test status
Simulation time 3382134682 ps
CPU time 104.23 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:45 PM PDT 24
Peak memory 200516 kb
Host smart-f6c69a55-b247-4028-b9a2-6ae82cfb080e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=789639238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.789639238
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_smoke.4262231143
Short name T60
Test name
Test status
Simulation time 379577114 ps
CPU time 10.1 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:30:36 PM PDT 24
Peak memory 200428 kb
Host smart-35bacadf-471b-4f39-a9cf-341464469977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262231143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4262231143
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_alert_test.303001515
Short name T28
Test name
Test status
Simulation time 23312835 ps
CPU time 0.6 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:30:28 PM PDT 24
Peak memory 196164 kb
Host smart-247dc2c1-d03f-4363-9f6e-7ac3e6d0a5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303001515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.303001515
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1543296396
Short name T152
Test name
Test status
Simulation time 429069793 ps
CPU time 3.95 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:54 PM PDT 24
Peak memory 200264 kb
Host smart-2091aedd-c732-4520-b270-bf3d2d9363ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543296396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1543296396
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_long_msg.823513874
Short name T158
Test name
Test status
Simulation time 133923392236 ps
CPU time 219.74 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:34:39 PM PDT 24
Peak memory 214224 kb
Host smart-326af574-6985-49a5-a61e-397611e6e5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823513874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.823513874
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3090072284
Short name T44
Test name
Test status
Simulation time 43417371548 ps
CPU time 577.88 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:40:04 PM PDT 24
Peak memory 208740 kb
Host smart-7648e4d7-12e4-4cc9-b446-ca761816495f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090072284 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3090072284
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3173717032
Short name T146
Test name
Test status
Simulation time 238120117 ps
CPU time 4.09 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:43 PM PDT 24
Peak memory 200220 kb
Host smart-7b9653a2-087c-45f0-8840-195a0f9765d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173717032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3173717032
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2565807955
Short name T124
Test name
Test status
Simulation time 322538195 ps
CPU time 8.08 seconds
Started Aug 15 04:50:31 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200188 kb
Host smart-f9510313-a742-4713-87a0-9ac8f5ea5c00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565807955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2565807955
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.393790540
Short name T150
Test name
Test status
Simulation time 249232745 ps
CPU time 4.02 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 200256 kb
Host smart-20d13154-7a9d-47d7-8220-fcb46bcce019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393790540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.393790540
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2306431751
Short name T283
Test name
Test status
Simulation time 74999861845 ps
CPU time 630.21 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:40:29 PM PDT 24
Peak memory 200648 kb
Host smart-f48f663e-546c-463b-862f-cc2aec6223ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306431751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2306431751
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.4222001085
Short name T123
Test name
Test status
Simulation time 3803189953 ps
CPU time 13.68 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 199720 kb
Host smart-19f8c311-8e88-448c-9383-b2494e3667e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222001085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.4222001085
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.4007473395
Short name T111
Test name
Test status
Simulation time 64290958 ps
CPU time 0.94 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:29 PM PDT 24
Peak memory 199944 kb
Host smart-9efcaa13-dd98-42e0-a38e-68975408ab1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007473395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4007473395
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1122683009
Short name T571
Test name
Test status
Simulation time 43712829 ps
CPU time 2.41 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200232 kb
Host smart-a3bb34e1-1af9-4fc9-85a7-bd025745a975
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122683009 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1122683009
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1182476710
Short name T591
Test name
Test status
Simulation time 11353142 ps
CPU time 0.6 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 195128 kb
Host smart-3f907661-a0a6-4080-ad8f-59e6ca6b0d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182476710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1182476710
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2500731730
Short name T586
Test name
Test status
Simulation time 370370460 ps
CPU time 1.66 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:35 PM PDT 24
Peak memory 200304 kb
Host smart-b7bc1025-8fb5-4a5f-8df8-6b7a61e5af8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500731730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2500731730
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1904223614
Short name T602
Test name
Test status
Simulation time 226317377 ps
CPU time 1.55 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:35 PM PDT 24
Peak memory 200192 kb
Host smart-2881ddf8-f8ac-4001-a443-92f550b13171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904223614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1904223614
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2645882782
Short name T587
Test name
Test status
Simulation time 340257674 ps
CPU time 1.95 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 200236 kb
Host smart-3b8ce363-1867-46e3-a91c-9cc1da5c33d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645882782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2645882782
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.144856488
Short name T112
Test name
Test status
Simulation time 56355780 ps
CPU time 3.01 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200224 kb
Host smart-c122360b-9d28-4709-a0b7-2ed2f3a7fdcc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144856488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.144856488
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1440357056
Short name T553
Test name
Test status
Simulation time 1932754648 ps
CPU time 5.82 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:45 PM PDT 24
Peak memory 199580 kb
Host smart-32825f67-de81-4ce0-95e9-d2291440e414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440357056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1440357056
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1034871438
Short name T641
Test name
Test status
Simulation time 40343063 ps
CPU time 0.76 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 198704 kb
Host smart-45ac5874-8ad5-4918-b018-cdea0a0a6f98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034871438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1034871438
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3193089744
Short name T559
Test name
Test status
Simulation time 124218223 ps
CPU time 1.83 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 200228 kb
Host smart-9193097f-c012-45be-8d8e-22ab31d61cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193089744 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3193089744
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1570133348
Short name T613
Test name
Test status
Simulation time 35134685 ps
CPU time 0.86 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 199664 kb
Host smart-f023644a-f912-4250-bf5a-04054e97a323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570133348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1570133348
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.600828864
Short name T577
Test name
Test status
Simulation time 40884887 ps
CPU time 0.57 seconds
Started Aug 15 04:50:30 PM PDT 24
Finished Aug 15 04:50:30 PM PDT 24
Peak memory 195208 kb
Host smart-28943040-4f7f-409b-9bee-5bb1e1da1c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600828864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.600828864
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1462032148
Short name T580
Test name
Test status
Simulation time 295598339 ps
CPU time 1.77 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200024 kb
Host smart-7f861bf8-4a18-4f4e-8145-666adb97bea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462032148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1462032148
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.300700649
Short name T543
Test name
Test status
Simulation time 474866662 ps
CPU time 4.37 seconds
Started Aug 15 04:50:31 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 200232 kb
Host smart-84dd7553-94cf-4e71-bb93-f3a7c9aa5756
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300700649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.300700649
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.4228829322
Short name T147
Test name
Test status
Simulation time 317958663 ps
CPU time 1.86 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:30 PM PDT 24
Peak memory 200216 kb
Host smart-fb5f34bd-37a8-4064-a71d-06bff7723f36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228829322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.4228829322
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2012252571
Short name T92
Test name
Test status
Simulation time 196794300 ps
CPU time 3.23 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200360 kb
Host smart-a46591b1-686c-467a-9eb8-a4cc066c7096
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012252571 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2012252571
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2417632674
Short name T126
Test name
Test status
Simulation time 18937814 ps
CPU time 0.85 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200068 kb
Host smart-e6c28560-19e4-4229-a55d-d5256b9f58ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417632674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2417632674
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4250209281
Short name T551
Test name
Test status
Simulation time 29218963 ps
CPU time 0.63 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 195308 kb
Host smart-f39d47e0-395b-45ef-b8e4-9eabc5dcdf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250209281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4250209281
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1965036482
Short name T649
Test name
Test status
Simulation time 407373481 ps
CPU time 2.16 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200164 kb
Host smart-5af6dcc3-b658-4a0e-97ae-8b7415a2072e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965036482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1965036482
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3510383530
Short name T570
Test name
Test status
Simulation time 77938560 ps
CPU time 1.18 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200232 kb
Host smart-45a21011-4620-4890-9849-3a5349ac77fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510383530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3510383530
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4245637205
Short name T627
Test name
Test status
Simulation time 283063145 ps
CPU time 1.84 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200296 kb
Host smart-5419fba3-1577-4365-a7f5-856e8150abf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245637205 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4245637205
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1940056457
Short name T120
Test name
Test status
Simulation time 105326151 ps
CPU time 0.95 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 199764 kb
Host smart-c53b3b28-dac2-42cf-931f-94d34d629a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940056457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1940056457
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.488829631
Short name T574
Test name
Test status
Simulation time 33241747 ps
CPU time 0.57 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 195196 kb
Host smart-e9480e82-4fd2-4aa5-9321-9da93dc7025e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488829631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.488829631
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.333666894
Short name T129
Test name
Test status
Simulation time 158871578 ps
CPU time 1.18 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 198916 kb
Host smart-197b8df9-8116-486f-b4b1-e2f0a8bc81b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333666894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.333666894
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4162508086
Short name T541
Test name
Test status
Simulation time 218824180 ps
CPU time 3.06 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 200196 kb
Host smart-bba7cd1a-5834-4772-a89e-7a8e4d615d4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162508086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4162508086
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3989451679
Short name T607
Test name
Test status
Simulation time 150474260 ps
CPU time 2.67 seconds
Started Aug 15 04:50:42 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 208500 kb
Host smart-20781719-855d-4a07-9562-04d88e9ccf7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989451679 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3989451679
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1523116826
Short name T119
Test name
Test status
Simulation time 28754828 ps
CPU time 0.83 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 199788 kb
Host smart-e83b495e-0235-4755-aabe-18b1cc5bba88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523116826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1523116826
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1154045869
Short name T560
Test name
Test status
Simulation time 13284562 ps
CPU time 0.58 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 195268 kb
Host smart-4c345122-66ca-4fd0-adee-46092ceda488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154045869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1154045869
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.565612820
Short name T634
Test name
Test status
Simulation time 133798754 ps
CPU time 1.77 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200220 kb
Host smart-73c018eb-3e7d-4cb0-8759-33a4f0717090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565612820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.565612820
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3184466083
Short name T548
Test name
Test status
Simulation time 74534221 ps
CPU time 3.77 seconds
Started Aug 15 04:50:41 PM PDT 24
Finished Aug 15 04:50:45 PM PDT 24
Peak memory 200288 kb
Host smart-baa4e23e-f08e-4ecf-9a61-9753580d8d12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184466083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3184466083
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.508075735
Short name T153
Test name
Test status
Simulation time 2965291404 ps
CPU time 3.18 seconds
Started Aug 15 04:50:40 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 200352 kb
Host smart-1f87645d-2fdf-4cef-9554-e7ba59f7530c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508075735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.508075735
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2715687634
Short name T584
Test name
Test status
Simulation time 179262936 ps
CPU time 2.58 seconds
Started Aug 15 04:50:45 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 208408 kb
Host smart-72815a8e-41b7-4a63-86ea-d1ed2424ac17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715687634 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2715687634
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.209599193
Short name T588
Test name
Test status
Simulation time 66450703 ps
CPU time 0.71 seconds
Started Aug 15 04:50:44 PM PDT 24
Finished Aug 15 04:50:45 PM PDT 24
Peak memory 198280 kb
Host smart-e971ea04-3897-49f8-acc0-1a5f06f4d668
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209599193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.209599193
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.822867809
Short name T592
Test name
Test status
Simulation time 36495104 ps
CPU time 0.64 seconds
Started Aug 15 04:50:42 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 195396 kb
Host smart-393bc06c-b14e-4bfa-ae8e-58c0e7c213db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822867809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.822867809
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3483671588
Short name T130
Test name
Test status
Simulation time 41315740 ps
CPU time 1.08 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200132 kb
Host smart-4a17704e-4ba7-4da9-b502-0205e2cf7a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483671588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3483671588
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2182239391
Short name T573
Test name
Test status
Simulation time 63418177 ps
CPU time 1.51 seconds
Started Aug 15 04:50:42 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 200288 kb
Host smart-458250de-6c2e-40b7-888f-e081100749f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182239391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2182239391
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1156994749
Short name T145
Test name
Test status
Simulation time 100074873 ps
CPU time 2.94 seconds
Started Aug 15 04:50:45 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 200184 kb
Host smart-1edea1e1-3901-451b-bf5e-f6d78c739f61
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156994749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1156994749
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.847773728
Short name T633
Test name
Test status
Simulation time 44799527 ps
CPU time 1.31 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200208 kb
Host smart-6f4f6907-5da0-45db-b991-4af2ec63d25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847773728 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.847773728
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2929018604
Short name T636
Test name
Test status
Simulation time 22887064 ps
CPU time 0.7 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 198564 kb
Host smart-8f187afe-9d08-4939-920f-8a1711af7db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929018604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2929018604
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.927868579
Short name T615
Test name
Test status
Simulation time 38033808 ps
CPU time 0.63 seconds
Started Aug 15 04:50:45 PM PDT 24
Finished Aug 15 04:50:46 PM PDT 24
Peak memory 195184 kb
Host smart-72d0efc7-2549-4b82-b5a2-4766eb0e9a14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927868579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.927868579
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.845681055
Short name T569
Test name
Test status
Simulation time 101082908 ps
CPU time 1.8 seconds
Started Aug 15 04:50:44 PM PDT 24
Finished Aug 15 04:50:46 PM PDT 24
Peak memory 200248 kb
Host smart-1352641c-1cd9-4f6e-b09b-45f7d5055216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845681055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.845681055
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2997499622
Short name T539
Test name
Test status
Simulation time 145128604 ps
CPU time 1.97 seconds
Started Aug 15 04:50:44 PM PDT 24
Finished Aug 15 04:50:46 PM PDT 24
Peak memory 200232 kb
Host smart-1537369c-6375-4eb9-a907-e65b11c03442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997499622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2997499622
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3595508856
Short name T564
Test name
Test status
Simulation time 478007468 ps
CPU time 3.89 seconds
Started Aug 15 04:50:44 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 200244 kb
Host smart-4db61c73-c2f3-4c7b-a92e-39a3f4c49e48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595508856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3595508856
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3291879808
Short name T598
Test name
Test status
Simulation time 166282368 ps
CPU time 1.24 seconds
Started Aug 15 04:50:54 PM PDT 24
Finished Aug 15 04:50:56 PM PDT 24
Peak memory 200076 kb
Host smart-e3491ebc-d3d3-40fd-b074-b20e7978837f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291879808 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3291879808
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.685437418
Short name T563
Test name
Test status
Simulation time 38046818 ps
CPU time 0.67 seconds
Started Aug 15 04:50:51 PM PDT 24
Finished Aug 15 04:50:52 PM PDT 24
Peak memory 198084 kb
Host smart-b3b7513c-5f95-4932-b6ac-289211ff25ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685437418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.685437418
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4029512284
Short name T614
Test name
Test status
Simulation time 13271715 ps
CPU time 0.57 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 195276 kb
Host smart-09e9fdfd-1c34-4ba9-b557-e8a0143acc0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029512284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4029512284
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.4064110104
Short name T132
Test name
Test status
Simulation time 135261646 ps
CPU time 1.67 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 200216 kb
Host smart-ccf124ee-5a19-43ac-b7e0-65486494c738
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064110104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.4064110104
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1223268606
Short name T546
Test name
Test status
Simulation time 73571686 ps
CPU time 1.79 seconds
Started Aug 15 04:50:42 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 200136 kb
Host smart-37373e9a-4b90-4224-b169-37252876d5c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223268606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1223268606
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3230700422
Short name T624
Test name
Test status
Simulation time 532292224 ps
CPU time 2.81 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 200212 kb
Host smart-8460e74d-28be-47b5-aeec-84ad3bb5b4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230700422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3230700422
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3400294171
Short name T540
Test name
Test status
Simulation time 111465255 ps
CPU time 2.54 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 200144 kb
Host smart-1713a2d5-a04d-4fe9-83e3-c0d3810289aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400294171 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3400294171
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2159428741
Short name T644
Test name
Test status
Simulation time 15653166 ps
CPU time 0.73 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 198480 kb
Host smart-43ad4786-1603-47b1-bff6-a4ba5076c306
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159428741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2159428741
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1419152169
Short name T547
Test name
Test status
Simulation time 29379848 ps
CPU time 0.6 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:47 PM PDT 24
Peak memory 195172 kb
Host smart-1f8da990-5024-41ff-b0c1-d741885f3b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419152169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1419152169
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1053152187
Short name T630
Test name
Test status
Simulation time 151379457 ps
CPU time 2.15 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 200152 kb
Host smart-1ad47d1a-9d13-4cee-abea-90ca29cf83f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053152187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1053152187
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2016847493
Short name T71
Test name
Test status
Simulation time 80428538 ps
CPU time 3.51 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 200228 kb
Host smart-3517ffe1-58e6-4636-a7f3-3d7ce26cc53b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016847493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2016847493
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1363205154
Short name T629
Test name
Test status
Simulation time 477052065 ps
CPU time 4.13 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 200192 kb
Host smart-3a99e8e4-b246-4a46-a81b-47ce9c1f2e98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363205154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1363205154
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3322234781
Short name T555
Test name
Test status
Simulation time 170196065 ps
CPU time 1.29 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 200148 kb
Host smart-5af7678e-b9d9-46ae-9755-7e65abdb2bd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322234781 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3322234781
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1184136295
Short name T640
Test name
Test status
Simulation time 18163842 ps
CPU time 0.84 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 199208 kb
Host smart-d6046f8a-dc4b-47e5-83f2-ef1a56079e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184136295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1184136295
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3927124658
Short name T612
Test name
Test status
Simulation time 15331592 ps
CPU time 0.8 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195400 kb
Host smart-91852161-b155-478b-bf62-88b8cdc1f05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927124658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3927124658
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2188146170
Short name T133
Test name
Test status
Simulation time 73321756 ps
CPU time 1.67 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 200256 kb
Host smart-f7ca16ff-4353-418d-9a7e-aafb75c2d71c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188146170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2188146170
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.567101541
Short name T638
Test name
Test status
Simulation time 125162110 ps
CPU time 1.45 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 200292 kb
Host smart-f9aa368c-6e5f-4023-955a-9033851d1326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567101541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.567101541
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1279460126
Short name T143
Test name
Test status
Simulation time 627037725 ps
CPU time 4.72 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 200096 kb
Host smart-ae86e730-3ef7-46db-9203-37c4fcef2f70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279460126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1279460126
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2994433500
Short name T582
Test name
Test status
Simulation time 52794612136 ps
CPU time 523.78 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:59:32 PM PDT 24
Peak memory 216800 kb
Host smart-40bc3fb0-fb4b-483c-864a-83ccf781164a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994433500 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2994433500
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1916310638
Short name T116
Test name
Test status
Simulation time 14667513 ps
CPU time 0.8 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 199748 kb
Host smart-92d5e102-3d3d-4375-ab3a-510f6196a7d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916310638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1916310638
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3564459997
Short name T536
Test name
Test status
Simulation time 19461834 ps
CPU time 0.62 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 195392 kb
Host smart-7877c7ac-c999-4a21-ade8-21b980fee8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564459997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3564459997
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.719778596
Short name T645
Test name
Test status
Simulation time 45502868 ps
CPU time 1.07 seconds
Started Aug 15 04:50:51 PM PDT 24
Finished Aug 15 04:50:52 PM PDT 24
Peak memory 200208 kb
Host smart-c63ad1ea-2dcf-4c4f-a5b7-b674b6f0df33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719778596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.719778596
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1604713226
Short name T72
Test name
Test status
Simulation time 295527828 ps
CPU time 2.86 seconds
Started Aug 15 04:50:54 PM PDT 24
Finished Aug 15 04:50:58 PM PDT 24
Peak memory 200176 kb
Host smart-01425522-b9ae-49c8-b03e-4137765ec917
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604713226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1604713226
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.787665928
Short name T151
Test name
Test status
Simulation time 137411708 ps
CPU time 4 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:55 PM PDT 24
Peak memory 200244 kb
Host smart-c7227aaf-5587-4df1-b797-3a901e107a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787665928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.787665928
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2825981323
Short name T566
Test name
Test status
Simulation time 75594420 ps
CPU time 1.27 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:52 PM PDT 24
Peak memory 200036 kb
Host smart-506c5cd7-1c10-49e8-8de1-e3e9c69ed1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825981323 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2825981323
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3851728334
Short name T628
Test name
Test status
Simulation time 32883197 ps
CPU time 0.71 seconds
Started Aug 15 04:50:52 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 198264 kb
Host smart-b1c181fb-8902-4a19-90bb-35f5e1e3ac50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851728334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3851728334
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2165454357
Short name T549
Test name
Test status
Simulation time 12739733 ps
CPU time 0.58 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195180 kb
Host smart-ccebf9ac-7e92-4e0f-a9df-9ebc15ed7928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165454357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2165454357
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4065333195
Short name T128
Test name
Test status
Simulation time 94795427 ps
CPU time 1.73 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:47 PM PDT 24
Peak memory 200288 kb
Host smart-b4f095db-8b72-446d-8e9b-54179edbb800
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065333195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4065333195
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2417349291
Short name T593
Test name
Test status
Simulation time 192801979 ps
CPU time 3.39 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 200132 kb
Host smart-ede9cafb-40f4-4015-af90-3458623592f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417349291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2417349291
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3073468442
Short name T590
Test name
Test status
Simulation time 218885155 ps
CPU time 5.78 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200104 kb
Host smart-a94a44ac-d594-40f7-9b82-dd4a6fc596da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073468442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3073468442
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3064101235
Short name T625
Test name
Test status
Simulation time 920840967 ps
CPU time 5.39 seconds
Started Aug 15 04:50:29 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 199892 kb
Host smart-433ead3e-b5cb-45be-8231-93e4c419f5d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064101235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3064101235
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2913493096
Short name T585
Test name
Test status
Simulation time 56073048 ps
CPU time 0.85 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 199684 kb
Host smart-32c5032a-41c1-4c6f-ac75-b7929823fcd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913493096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2913493096
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3910400738
Short name T550
Test name
Test status
Simulation time 249920006916 ps
CPU time 902.03 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 05:05:35 PM PDT 24
Peak memory 216768 kb
Host smart-2ff6d9ba-1465-4c3f-8dbe-36dd87771ebe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910400738 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3910400738
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1370436928
Short name T118
Test name
Test status
Simulation time 30003638 ps
CPU time 0.9 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 199980 kb
Host smart-054bd2e1-5dcd-4f2d-996e-6c75b3022569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370436928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1370436928
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.250309100
Short name T622
Test name
Test status
Simulation time 24353347 ps
CPU time 0.63 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 195524 kb
Host smart-5a24c6a1-0132-4b53-99ac-52496a874f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250309100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.250309100
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2462792802
Short name T134
Test name
Test status
Simulation time 35011786 ps
CPU time 1.57 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200108 kb
Host smart-9de0bf4f-2d2b-46f1-89d5-38a2375a5856
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462792802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2462792802
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1774293147
Short name T619
Test name
Test status
Simulation time 263630209 ps
CPU time 3.65 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:43 PM PDT 24
Peak memory 200196 kb
Host smart-10289e4e-21bd-4e90-ae1a-a0cc71e60808
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774293147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1774293147
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1157531113
Short name T609
Test name
Test status
Simulation time 13963467 ps
CPU time 0.61 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195172 kb
Host smart-2a04ed3c-cf4f-4381-8af8-c3d92df5b82c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157531113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1157531113
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3588089293
Short name T568
Test name
Test status
Simulation time 57298779 ps
CPU time 0.61 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195256 kb
Host smart-b837c4ae-21ba-493d-b816-529cfb728a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588089293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3588089293
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.858040268
Short name T537
Test name
Test status
Simulation time 18186997 ps
CPU time 0.68 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:47 PM PDT 24
Peak memory 195336 kb
Host smart-3d39c78e-00f2-457a-8643-fbe2bc6588eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858040268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.858040268
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3855113836
Short name T552
Test name
Test status
Simulation time 62797846 ps
CPU time 0.6 seconds
Started Aug 15 04:50:51 PM PDT 24
Finished Aug 15 04:50:52 PM PDT 24
Peak memory 195292 kb
Host smart-fbea1441-80bd-4b55-8cfd-ec0f23aca154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855113836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3855113836
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.866927256
Short name T606
Test name
Test status
Simulation time 60199536 ps
CPU time 0.6 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195316 kb
Host smart-cfc5aa9e-5d74-4b92-8541-f2a88b1e8d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866927256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.866927256
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1423827545
Short name T554
Test name
Test status
Simulation time 49730473 ps
CPU time 0.6 seconds
Started Aug 15 04:50:46 PM PDT 24
Finished Aug 15 04:50:47 PM PDT 24
Peak memory 195212 kb
Host smart-85df7cc5-3687-4710-a92e-6f6f725b6f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423827545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1423827545
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.925219037
Short name T616
Test name
Test status
Simulation time 154935466 ps
CPU time 0.63 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195276 kb
Host smart-c6568a2c-a992-4e6b-862b-6b2edb627b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925219037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.925219037
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1364882882
Short name T600
Test name
Test status
Simulation time 25794811 ps
CPU time 0.58 seconds
Started Aug 15 04:50:55 PM PDT 24
Finished Aug 15 04:50:56 PM PDT 24
Peak memory 195156 kb
Host smart-b520f3ee-4da3-49d2-95dd-78de90e7ed27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364882882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1364882882
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.836192953
Short name T601
Test name
Test status
Simulation time 11829056 ps
CPU time 0.58 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195184 kb
Host smart-366c3543-2115-4ed4-b6e0-3e2e2bc47262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836192953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.836192953
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3057521141
Short name T561
Test name
Test status
Simulation time 50385743 ps
CPU time 0.62 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 195104 kb
Host smart-e197793d-ffce-4088-9544-1564189d55cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057521141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3057521141
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3918562481
Short name T115
Test name
Test status
Simulation time 2149780440 ps
CPU time 3.48 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200192 kb
Host smart-4e4ec81a-b072-48bc-9b9a-16036ea430b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918562481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3918562481
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.400153266
Short name T113
Test name
Test status
Simulation time 442892682 ps
CPU time 9.69 seconds
Started Aug 15 04:50:32 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 200144 kb
Host smart-a757d9ea-c926-4007-b8c0-e026849fa2ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400153266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.400153266
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3259560777
Short name T579
Test name
Test status
Simulation time 56896117 ps
CPU time 0.89 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 199852 kb
Host smart-905e60d9-8eae-4ad8-84ae-f1c6ff24db17
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259560777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3259560777
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3312067409
Short name T608
Test name
Test status
Simulation time 1440857496 ps
CPU time 2.44 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200280 kb
Host smart-04e56ad1-cdf8-47b3-bab1-e9b8f681cb7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312067409 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3312067409
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.52704500
Short name T127
Test name
Test status
Simulation time 78498581 ps
CPU time 0.71 seconds
Started Aug 15 04:50:30 PM PDT 24
Finished Aug 15 04:50:31 PM PDT 24
Peak memory 198464 kb
Host smart-376239fb-aa23-4965-a3b6-7dc33cc02de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52704500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.52704500
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2900097023
Short name T647
Test name
Test status
Simulation time 36747488 ps
CPU time 0.63 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 195132 kb
Host smart-7296836c-06a6-48fb-a269-af0215fab2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900097023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2900097023
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3521334579
Short name T618
Test name
Test status
Simulation time 448410140 ps
CPU time 2.33 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200212 kb
Host smart-1206cdc4-20cf-43d1-980c-c8cf2f55e8bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521334579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3521334579
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1017306582
Short name T596
Test name
Test status
Simulation time 534719780 ps
CPU time 1.17 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200232 kb
Host smart-61dfcebd-9bdf-41dd-9e4f-70d9d8671919
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017306582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1017306582
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2877192011
Short name T148
Test name
Test status
Simulation time 392347073 ps
CPU time 1.86 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200224 kb
Host smart-09039375-bfc7-4af0-b018-bd60edc560c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877192011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2877192011
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2885637471
Short name T620
Test name
Test status
Simulation time 11948744 ps
CPU time 0.6 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195232 kb
Host smart-b886915e-9d6f-4404-b332-11072e74b8b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885637471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2885637471
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.997206848
Short name T648
Test name
Test status
Simulation time 13972547 ps
CPU time 0.56 seconds
Started Aug 15 04:50:55 PM PDT 24
Finished Aug 15 04:50:56 PM PDT 24
Peak memory 195176 kb
Host smart-81702a39-e294-46a4-ba54-89ba0164670a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997206848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.997206848
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2903716492
Short name T581
Test name
Test status
Simulation time 14226694 ps
CPU time 0.6 seconds
Started Aug 15 04:50:54 PM PDT 24
Finished Aug 15 04:50:55 PM PDT 24
Peak memory 195192 kb
Host smart-47e2faa8-615f-4536-9520-db72d99d2255
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903716492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2903716492
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2650819211
Short name T535
Test name
Test status
Simulation time 15256011 ps
CPU time 0.63 seconds
Started Aug 15 04:50:56 PM PDT 24
Finished Aug 15 04:50:57 PM PDT 24
Peak memory 195224 kb
Host smart-07198292-0d56-437f-981e-5dc6116b2300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650819211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2650819211
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.351341722
Short name T572
Test name
Test status
Simulation time 54284532 ps
CPU time 0.59 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 195236 kb
Host smart-b1a51e4a-ed4f-440b-899b-bb848ae1fbe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351341722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.351341722
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3559186378
Short name T567
Test name
Test status
Simulation time 47324212 ps
CPU time 0.61 seconds
Started Aug 15 04:50:52 PM PDT 24
Finished Aug 15 04:50:53 PM PDT 24
Peak memory 195184 kb
Host smart-ecb05083-57b8-4147-a594-f616a27007f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559186378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3559186378
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2786010710
Short name T534
Test name
Test status
Simulation time 41297951 ps
CPU time 0.62 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195340 kb
Host smart-3dc66188-4eb1-45a2-b029-44737e4add55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786010710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2786010710
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.666761948
Short name T611
Test name
Test status
Simulation time 19190765 ps
CPU time 0.65 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195356 kb
Host smart-86214181-61ce-4acd-8765-16a51fa97557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666761948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.666761948
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3033501764
Short name T544
Test name
Test status
Simulation time 13299781 ps
CPU time 0.62 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 195324 kb
Host smart-f777c0c9-e91e-428c-8de9-b3318386f860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033501764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3033501764
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.819689653
Short name T653
Test name
Test status
Simulation time 45628379 ps
CPU time 0.62 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195232 kb
Host smart-699a9f8d-2f19-4ad8-a63b-f8ca82175551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819689653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.819689653
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1593108373
Short name T121
Test name
Test status
Simulation time 1339280977 ps
CPU time 5.77 seconds
Started Aug 15 04:50:27 PM PDT 24
Finished Aug 15 04:50:33 PM PDT 24
Peak memory 200112 kb
Host smart-a124a550-4588-4c38-871f-495d1c8d39dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593108373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1593108373
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3778372513
Short name T545
Test name
Test status
Simulation time 4378441733 ps
CPU time 11.51 seconds
Started Aug 15 04:50:27 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 199736 kb
Host smart-e52a5925-fe87-4fb0-8159-ff3599a54680
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778372513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3778372513
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.134148779
Short name T114
Test name
Test status
Simulation time 57907797 ps
CPU time 0.74 seconds
Started Aug 15 04:50:31 PM PDT 24
Finished Aug 15 04:50:31 PM PDT 24
Peak memory 198628 kb
Host smart-6f46d6f7-89bf-4774-b82e-eed7dc48c69a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134148779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.134148779
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1047741262
Short name T558
Test name
Test status
Simulation time 148619477 ps
CPU time 2.45 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 208476 kb
Host smart-f8a74a84-fa95-4d45-a6e9-282f16aec579
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047741262 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1047741262
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2411117574
Short name T110
Test name
Test status
Simulation time 89490184 ps
CPU time 0.84 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 199548 kb
Host smart-217a8f36-ce66-4067-8aac-23234ffcbd07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411117574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2411117574
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.757455375
Short name T604
Test name
Test status
Simulation time 11409404 ps
CPU time 0.62 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 195396 kb
Host smart-c3c7b49a-97ef-43c7-b94f-d27250f59320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757455375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.757455375
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.4250188291
Short name T597
Test name
Test status
Simulation time 483210687 ps
CPU time 2.12 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200284 kb
Host smart-84ad5054-49a5-4cac-bce2-3fad217603bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250188291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.4250188291
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1919063686
Short name T73
Test name
Test status
Simulation time 99982504 ps
CPU time 2.08 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200232 kb
Host smart-09f3097c-7a27-4541-a3c9-946dc7976482
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919063686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1919063686
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2505294340
Short name T149
Test name
Test status
Simulation time 61158131 ps
CPU time 1.76 seconds
Started Aug 15 04:50:28 PM PDT 24
Finished Aug 15 04:50:29 PM PDT 24
Peak memory 200288 kb
Host smart-70a2a4bc-8d95-496c-b09e-9e59382a68c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505294340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2505294340
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1209094577
Short name T557
Test name
Test status
Simulation time 23022913 ps
CPU time 0.61 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195136 kb
Host smart-cc52ac42-e118-4ebe-9ebb-5edeeecc91c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209094577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1209094577
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1649566098
Short name T635
Test name
Test status
Simulation time 11613342 ps
CPU time 0.59 seconds
Started Aug 15 04:50:49 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195196 kb
Host smart-bfdd8d71-7b7e-43af-8b05-ca2d65abee73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649566098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1649566098
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.225331937
Short name T637
Test name
Test status
Simulation time 29253558 ps
CPU time 0.6 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:51 PM PDT 24
Peak memory 195260 kb
Host smart-f4e8c3f6-499f-47c5-be4c-f5ca7c55e3fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225331937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.225331937
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.4042713088
Short name T617
Test name
Test status
Simulation time 11852986 ps
CPU time 0.59 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195280 kb
Host smart-97e9cdc5-1277-428d-8e40-4a6d41cc48f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042713088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.4042713088
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2567662495
Short name T632
Test name
Test status
Simulation time 41233003 ps
CPU time 0.57 seconds
Started Aug 15 04:50:50 PM PDT 24
Finished Aug 15 04:50:50 PM PDT 24
Peak memory 195328 kb
Host smart-f15a9f40-2519-4e12-af15-271f16a781a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567662495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2567662495
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1835312994
Short name T578
Test name
Test status
Simulation time 122982819 ps
CPU time 0.64 seconds
Started Aug 15 04:50:48 PM PDT 24
Finished Aug 15 04:50:49 PM PDT 24
Peak memory 195232 kb
Host smart-f1b4c3e3-7ae1-4d06-ace4-901757a0cf4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835312994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1835312994
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1835260040
Short name T565
Test name
Test status
Simulation time 13884407 ps
CPU time 0.67 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 195220 kb
Host smart-48f8efeb-0928-4279-aa47-c09d01b4cccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835260040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1835260040
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.780057011
Short name T651
Test name
Test status
Simulation time 13574499 ps
CPU time 0.6 seconds
Started Aug 15 04:50:47 PM PDT 24
Finished Aug 15 04:50:48 PM PDT 24
Peak memory 195160 kb
Host smart-665850f5-95d8-4a26-8a7f-cca80c219bad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780057011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.780057011
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1358179133
Short name T538
Test name
Test status
Simulation time 14358342 ps
CPU time 0.62 seconds
Started Aug 15 04:50:55 PM PDT 24
Finished Aug 15 04:50:56 PM PDT 24
Peak memory 195308 kb
Host smart-3abab8b7-1631-4958-8c24-f2f82730f277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358179133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1358179133
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1852080135
Short name T646
Test name
Test status
Simulation time 39691853 ps
CPU time 0.62 seconds
Started Aug 15 04:50:55 PM PDT 24
Finished Aug 15 04:50:56 PM PDT 24
Peak memory 195288 kb
Host smart-08d26f73-a9f2-4122-a810-7ce31dcf4352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852080135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1852080135
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3970339128
Short name T643
Test name
Test status
Simulation time 70720932 ps
CPU time 2.43 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 208492 kb
Host smart-8bc51379-3597-46a4-8212-9cb7a1fdc0ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970339128 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3970339128
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1434745392
Short name T576
Test name
Test status
Simulation time 32064409 ps
CPU time 0.92 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 199788 kb
Host smart-bfb47bc3-398f-4c56-8fe7-726e38fc0c00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434745392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1434745392
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3273267172
Short name T605
Test name
Test status
Simulation time 30565751 ps
CPU time 0.56 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:35 PM PDT 24
Peak memory 195308 kb
Host smart-f155bfbb-84f1-4612-85a6-3f3ec7d50b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273267172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3273267172
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2611070735
Short name T623
Test name
Test status
Simulation time 216605458 ps
CPU time 1.23 seconds
Started Aug 15 04:50:40 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200224 kb
Host smart-22442686-b8f7-4725-a606-460b6ac4f0d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611070735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2611070735
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.559597100
Short name T650
Test name
Test status
Simulation time 90025186 ps
CPU time 1.73 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200268 kb
Host smart-7e750fac-2762-4c04-b161-58181a9106df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559597100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.559597100
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2529262167
Short name T652
Test name
Test status
Simulation time 247104797 ps
CPU time 3.13 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200228 kb
Host smart-d7b39005-e2b3-4ec9-8462-1e2258be4abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529262167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2529262167
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1159851494
Short name T626
Test name
Test status
Simulation time 57032633 ps
CPU time 3.53 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 215852 kb
Host smart-83f44b45-b991-4c93-b905-ccc8c14e7bbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159851494 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1159851494
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.158856706
Short name T575
Test name
Test status
Simulation time 43336383 ps
CPU time 0.74 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 197772 kb
Host smart-f52f1759-2656-4f83-b995-027539050940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158856706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.158856706
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.1819505043
Short name T589
Test name
Test status
Simulation time 44702172 ps
CPU time 0.57 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 195092 kb
Host smart-69bd4c0a-8adf-4f3f-b3fb-683acfdfb328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819505043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1819505043
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.915154842
Short name T595
Test name
Test status
Simulation time 64142395 ps
CPU time 1.1 seconds
Started Aug 15 04:50:33 PM PDT 24
Finished Aug 15 04:50:34 PM PDT 24
Peak memory 198956 kb
Host smart-9b7466f2-a75c-4bc8-9744-3e88e2c73dee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915154842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.915154842
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.633521291
Short name T562
Test name
Test status
Simulation time 161022696 ps
CPU time 3.38 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200200 kb
Host smart-c4e6487b-8400-4946-b58e-4b4a19a06050
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633521291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.633521291
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2552037122
Short name T154
Test name
Test status
Simulation time 152436919 ps
CPU time 3.11 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200216 kb
Host smart-f3dc0b59-463f-43e9-93dc-a220a0ef26c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552037122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2552037122
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4239521736
Short name T542
Test name
Test status
Simulation time 1094271206 ps
CPU time 2.74 seconds
Started Aug 15 04:50:35 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200336 kb
Host smart-f52ae9bd-5021-4093-8feb-94c463459c1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239521736 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4239521736
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3431879026
Short name T122
Test name
Test status
Simulation time 85873840 ps
CPU time 0.85 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 199612 kb
Host smart-67839e50-48e4-4532-bb36-64b056337470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431879026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3431879026
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3528938645
Short name T639
Test name
Test status
Simulation time 43895577 ps
CPU time 0.58 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 195292 kb
Host smart-4785c92e-3f78-4a15-9a99-42a07407a6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528938645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3528938645
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1702908646
Short name T131
Test name
Test status
Simulation time 216104542 ps
CPU time 1.23 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:37 PM PDT 24
Peak memory 200112 kb
Host smart-f4c8fdc5-18cf-4962-b5ed-5d860f992a56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702908646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1702908646
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3934223038
Short name T603
Test name
Test status
Simulation time 784402963 ps
CPU time 3.15 seconds
Started Aug 15 04:50:34 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 200128 kb
Host smart-0149bd9d-d244-4aeb-8040-7b485f0bff50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934223038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3934223038
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4199210943
Short name T144
Test name
Test status
Simulation time 385774270 ps
CPU time 2 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200308 kb
Host smart-0b9fa7ad-f8a5-4883-b5b0-5453818e3d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199210943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4199210943
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2400631315
Short name T594
Test name
Test status
Simulation time 129560501 ps
CPU time 1.27 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200096 kb
Host smart-9324e828-02d1-4e25-803b-404ff7822929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400631315 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2400631315
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3539954996
Short name T583
Test name
Test status
Simulation time 213701286 ps
CPU time 0.7 seconds
Started Aug 15 04:50:43 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 198440 kb
Host smart-ee998570-7ab3-4e20-87c6-9838f8888d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539954996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3539954996
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1411583275
Short name T556
Test name
Test status
Simulation time 50371474 ps
CPU time 0.63 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:36 PM PDT 24
Peak memory 195140 kb
Host smart-4ef4e3f1-2932-4d09-9028-27e48b16f8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411583275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1411583275
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.891381291
Short name T642
Test name
Test status
Simulation time 302542729 ps
CPU time 2.45 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200244 kb
Host smart-bb8fcaad-477c-4748-9973-0effbf2cc403
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891381291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.891381291
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3371929118
Short name T599
Test name
Test status
Simulation time 213881405 ps
CPU time 2.65 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200284 kb
Host smart-913b9dbc-28ea-4a32-836f-d331b53bfe3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371929118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3371929118
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2946450315
Short name T67
Test name
Test status
Simulation time 152369008 ps
CPU time 3.15 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:40 PM PDT 24
Peak memory 200316 kb
Host smart-495d3a23-f0f2-4d66-a3e9-7a314c25e26e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946450315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2946450315
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2234247212
Short name T631
Test name
Test status
Simulation time 351275142 ps
CPU time 3.36 seconds
Started Aug 15 04:50:38 PM PDT 24
Finished Aug 15 04:50:42 PM PDT 24
Peak memory 215764 kb
Host smart-0632e100-cbc0-466d-97e3-934a81f2dc8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234247212 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2234247212
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2578939028
Short name T125
Test name
Test status
Simulation time 30343681 ps
CPU time 0.78 seconds
Started Aug 15 04:50:45 PM PDT 24
Finished Aug 15 04:50:46 PM PDT 24
Peak memory 198432 kb
Host smart-df1024ba-2bc8-4a02-b2d4-bfbca8053646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578939028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2578939028
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3711613400
Short name T654
Test name
Test status
Simulation time 154662710 ps
CPU time 0.66 seconds
Started Aug 15 04:50:37 PM PDT 24
Finished Aug 15 04:50:38 PM PDT 24
Peak memory 195308 kb
Host smart-2c96ef88-5341-47ec-8b21-a2726dcb049b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711613400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3711613400
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2294861616
Short name T610
Test name
Test status
Simulation time 48040024 ps
CPU time 2.05 seconds
Started Aug 15 04:50:36 PM PDT 24
Finished Aug 15 04:50:39 PM PDT 24
Peak memory 200168 kb
Host smart-1eda19c7-5c0a-45e0-9aa7-37eb542b3b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294861616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2294861616
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1548292572
Short name T621
Test name
Test status
Simulation time 1366944813 ps
CPU time 4.4 seconds
Started Aug 15 04:50:40 PM PDT 24
Finished Aug 15 04:50:44 PM PDT 24
Peak memory 200292 kb
Host smart-1ac41a87-3357-4ae0-a708-0c0553c7f5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548292572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1548292572
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3493623831
Short name T66
Test name
Test status
Simulation time 97071795 ps
CPU time 1.89 seconds
Started Aug 15 04:50:39 PM PDT 24
Finished Aug 15 04:50:41 PM PDT 24
Peak memory 200264 kb
Host smart-15c66e0e-939e-4208-8d35-10820bc4a016
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493623831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3493623831
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2474970979
Short name T380
Test name
Test status
Simulation time 22519096 ps
CPU time 0.56 seconds
Started Aug 15 04:29:50 PM PDT 24
Finished Aug 15 04:29:51 PM PDT 24
Peak memory 196108 kb
Host smart-042bd1b0-3fa8-4838-91c1-682e5ff151bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474970979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2474970979
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.232337012
Short name T499
Test name
Test status
Simulation time 1224377848 ps
CPU time 61.95 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:32:16 PM PDT 24
Peak memory 200332 kb
Host smart-d0cb514a-cf57-4e82-b0b7-a67e8a5f1aa2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232337012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.232337012
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2564764548
Short name T515
Test name
Test status
Simulation time 552188244 ps
CPU time 30.87 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:30:29 PM PDT 24
Peak memory 200588 kb
Host smart-43417d70-b2d6-4f84-b041-1360464e5632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564764548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2564764548
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.4093665453
Short name T216
Test name
Test status
Simulation time 11653031634 ps
CPU time 1088.36 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:48:10 PM PDT 24
Peak memory 763620 kb
Host smart-bea72891-d8bb-4897-9633-127b73a7e05c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4093665453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.4093665453
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.4202045012
Short name T509
Test name
Test status
Simulation time 13233978373 ps
CPU time 55.7 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 200492 kb
Host smart-aa34f8df-d19c-4f48-998b-fca420142adc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202045012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.4202045012
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3472254983
Short name T175
Test name
Test status
Simulation time 18342948676 ps
CPU time 151.15 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 04:33:45 PM PDT 24
Peak memory 200356 kb
Host smart-c7e793b8-bb3d-4ebe-a4f4-7350c7748ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472254983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3472254983
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2674943460
Short name T53
Test name
Test status
Simulation time 337936832 ps
CPU time 0.96 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 218696 kb
Host smart-f4453ec8-2d17-4663-8e8e-7c725868afe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674943460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2674943460
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2026008210
Short name T493
Test name
Test status
Simulation time 801844423 ps
CPU time 13.41 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:14 PM PDT 24
Peak memory 200484 kb
Host smart-b65894ab-27f4-4409-9b64-c158d5610c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026008210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2026008210
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.945470612
Short name T265
Test name
Test status
Simulation time 10188877030 ps
CPU time 175.3 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 216860 kb
Host smart-e9da71b9-7af7-48a9-a82e-e69fae8ae230
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945470612 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.945470612
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3521761192
Short name T285
Test name
Test status
Simulation time 14056064809 ps
CPU time 77.68 seconds
Started Aug 15 04:30:02 PM PDT 24
Finished Aug 15 04:31:20 PM PDT 24
Peak memory 200576 kb
Host smart-b738a4f0-cb39-46c3-9acc-77fd3ed31ee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3521761192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3521761192
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1243875555
Short name T292
Test name
Test status
Simulation time 35122841404 ps
CPU time 57.84 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:30:55 PM PDT 24
Peak memory 200660 kb
Host smart-d20e58fe-f098-491c-8fb9-d7198e3d9483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1243875555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1243875555
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3651808193
Short name T387
Test name
Test status
Simulation time 40482478815 ps
CPU time 73.14 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 200572 kb
Host smart-8654b600-0975-44f3-8043-17e51f4e56cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3651808193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3651808193
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3697685531
Short name T317
Test name
Test status
Simulation time 159936131273 ps
CPU time 2245.22 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 215984 kb
Host smart-e995fa5a-4639-40a3-8069-68c05cbe3a7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3697685531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3697685531
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1635049017
Short name T155
Test name
Test status
Simulation time 174514654219 ps
CPU time 2243.66 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 05:07:29 PM PDT 24
Peak memory 216904 kb
Host smart-f4ed8fc3-249b-4b4c-8b8f-492030da9b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635049017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1635049017
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3302013060
Short name T433
Test name
Test status
Simulation time 6064481827 ps
CPU time 71.86 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:32:25 PM PDT 24
Peak memory 200192 kb
Host smart-a932b630-b44e-46d0-89a6-a7362bbe9f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302013060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3302013060
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3331551826
Short name T398
Test name
Test status
Simulation time 48365143 ps
CPU time 0.6 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:29:58 PM PDT 24
Peak memory 197180 kb
Host smart-4741c454-6c5c-4a1d-92ad-66d86855d69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331551826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3331551826
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.712597918
Short name T136
Test name
Test status
Simulation time 48180145 ps
CPU time 2.24 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 200468 kb
Host smart-7dff4863-1146-4bfe-9f87-47225bcfd094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712597918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.712597918
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2322695236
Short name T333
Test name
Test status
Simulation time 1279772567 ps
CPU time 21.25 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:30:15 PM PDT 24
Peak memory 200416 kb
Host smart-0e89aad6-c9b3-4c53-acb9-cc0a51191ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322695236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2322695236
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2038242438
Short name T41
Test name
Test status
Simulation time 74968556761 ps
CPU time 1437.85 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:54:01 PM PDT 24
Peak memory 784884 kb
Host smart-5e7a8fa5-1338-45e5-98d2-6c36ae01bf69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2038242438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2038242438
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2359146899
Short name T531
Test name
Test status
Simulation time 30904188443 ps
CPU time 103.29 seconds
Started Aug 15 04:29:54 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 200548 kb
Host smart-662790d6-cc7c-40d8-b606-f0993c14e70a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359146899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2359146899
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3330343934
Short name T392
Test name
Test status
Simulation time 3322705976 ps
CPU time 187.17 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:33:13 PM PDT 24
Peak memory 216884 kb
Host smart-1ef7cccf-b71a-4ce0-8509-f5e863fbeaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330343934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3330343934
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2950911303
Short name T55
Test name
Test status
Simulation time 85289287 ps
CPU time 0.85 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 218656 kb
Host smart-0d80be0c-b96f-4e65-8915-1b7045d092d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950911303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2950911303
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1347665862
Short name T39
Test name
Test status
Simulation time 261141809 ps
CPU time 6.34 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 04:30:06 PM PDT 24
Peak memory 200568 kb
Host smart-ff61e4ad-7c74-466c-a664-d750f9225194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347665862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1347665862
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1560971554
Short name T524
Test name
Test status
Simulation time 205310790846 ps
CPU time 1337.17 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:52:25 PM PDT 24
Peak memory 676764 kb
Host smart-9aad0b34-166f-4388-9cc0-85a8bd7bae70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560971554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1560971554
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.191971963
Short name T372
Test name
Test status
Simulation time 1692439335 ps
CPU time 70.55 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 200440 kb
Host smart-dc492cf9-b9bf-4916-b434-058b5975bf34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=191971963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.191971963
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3853179841
Short name T352
Test name
Test status
Simulation time 21646362821 ps
CPU time 60.49 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 200296 kb
Host smart-219e90d2-2b05-41b8-97e9-1e7b1d0c5200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3853179841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3853179841
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.605430615
Short name T171
Test name
Test status
Simulation time 5663336978 ps
CPU time 89.16 seconds
Started Aug 15 04:30:02 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 200560 kb
Host smart-ca38aac0-1fd8-4e14-a266-1227c7ebe7d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=605430615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.605430615
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1419341050
Short name T403
Test name
Test status
Simulation time 115317718101 ps
CPU time 666.83 seconds
Started Aug 15 04:30:02 PM PDT 24
Finished Aug 15 04:41:09 PM PDT 24
Peak memory 200480 kb
Host smart-34e96f2e-ee95-465b-b78b-81236e61b49a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1419341050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1419341050
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3149620331
Short name T253
Test name
Test status
Simulation time 558812920247 ps
CPU time 2390.97 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 05:09:50 PM PDT 24
Peak memory 216468 kb
Host smart-a4600edf-313e-4794-9810-af3f8d3b101c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3149620331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3149620331
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2386934098
Short name T510
Test name
Test status
Simulation time 181521136024 ps
CPU time 2361.02 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 05:10:35 PM PDT 24
Peak memory 216208 kb
Host smart-5a7ac668-c3cf-4f5f-8c0d-652cbfe8a617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2386934098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2386934098
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3674017508
Short name T93
Test name
Test status
Simulation time 38318694045 ps
CPU time 98.26 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:31:43 PM PDT 24
Peak memory 200496 kb
Host smart-56628fe7-3f40-406d-9431-cd89a55c51f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674017508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3674017508
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.4009385535
Short name T245
Test name
Test status
Simulation time 20654187 ps
CPU time 0.57 seconds
Started Aug 15 04:30:22 PM PDT 24
Finished Aug 15 04:30:22 PM PDT 24
Peak memory 195504 kb
Host smart-bb57e04c-70ed-4a55-bbe3-274c134eb77c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009385535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.4009385535
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3223754158
Short name T189
Test name
Test status
Simulation time 824970975 ps
CPU time 45.38 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 200456 kb
Host smart-c94e278c-d78b-41b0-9d22-53ef8300cd6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3223754158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3223754158
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3767778027
Short name T410
Test name
Test status
Simulation time 3049630128 ps
CPU time 38.6 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:54 PM PDT 24
Peak memory 200480 kb
Host smart-a280c24b-8a08-48a0-883f-029c2e96f582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767778027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3767778027
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3921576145
Short name T513
Test name
Test status
Simulation time 6731277418 ps
CPU time 253.67 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:34:22 PM PDT 24
Peak memory 593216 kb
Host smart-906cb656-28b6-463d-8ce7-3980fedba538
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3921576145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3921576145
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3032927667
Short name T282
Test name
Test status
Simulation time 600616507 ps
CPU time 16.26 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 200448 kb
Host smart-f855c51b-2acf-4c1d-86c6-36dc64a2dc28
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032927667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3032927667
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2661847717
Short name T428
Test name
Test status
Simulation time 1198245847 ps
CPU time 71.7 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 200564 kb
Host smart-b3d095ac-36a5-4dda-b885-7c9b0ed9490d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661847717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2661847717
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.223651676
Short name T327
Test name
Test status
Simulation time 179071360 ps
CPU time 2.6 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:30:24 PM PDT 24
Peak memory 200404 kb
Host smart-7ee347c3-0d2a-4456-9f42-4d2acc6fd7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223651676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.223651676
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.971432577
Short name T527
Test name
Test status
Simulation time 9129258804 ps
CPU time 112.55 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:32:28 PM PDT 24
Peak memory 200632 kb
Host smart-f713d705-5475-4a51-94a5-89be43606a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971432577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.971432577
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.190757667
Short name T212
Test name
Test status
Simulation time 69552469 ps
CPU time 0.6 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:30:18 PM PDT 24
Peak memory 196640 kb
Host smart-a4240b88-e987-4853-b5b9-7f0b35bf6336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190757667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.190757667
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.302417607
Short name T281
Test name
Test status
Simulation time 6706886297 ps
CPU time 95.3 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:32:17 PM PDT 24
Peak memory 215972 kb
Host smart-d69cfe06-87f1-4078-a2cb-7216154502aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302417607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.302417607
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1717936457
Short name T257
Test name
Test status
Simulation time 4577423009 ps
CPU time 46.56 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 216688 kb
Host smart-d8a3610a-6692-49ad-986e-dd21016acdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717936457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1717936457
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3854476221
Short name T56
Test name
Test status
Simulation time 8812882698 ps
CPU time 806.56 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:43:53 PM PDT 24
Peak memory 775596 kb
Host smart-e9cdaca0-e8a5-4cb7-a7f1-4f95b159e698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854476221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3854476221
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2512982266
Short name T388
Test name
Test status
Simulation time 50672427275 ps
CPU time 227.66 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:34:28 PM PDT 24
Peak memory 200972 kb
Host smart-64ff87d7-0191-4600-be37-206f39851512
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512982266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2512982266
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3230728475
Short name T442
Test name
Test status
Simulation time 22803289718 ps
CPU time 149.42 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 200648 kb
Host smart-1775525e-cc6a-4d7b-bb05-aa11aa2247bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230728475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3230728475
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2836786184
Short name T462
Test name
Test status
Simulation time 1663869124 ps
CPU time 6.72 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:30:26 PM PDT 24
Peak memory 200452 kb
Host smart-37f87d11-435a-41ae-93c9-d6c3007b0908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836786184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2836786184
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3430290948
Short name T480
Test name
Test status
Simulation time 21473837247 ps
CPU time 538.69 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:39:25 PM PDT 24
Peak memory 610588 kb
Host smart-a1793efa-ec96-42a5-81dd-a8d5d372c9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430290948 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3430290948
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1122206224
Short name T491
Test name
Test status
Simulation time 1798495245 ps
CPU time 86.36 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:32:00 PM PDT 24
Peak memory 200512 kb
Host smart-64993398-7f7b-495b-8cf0-86cc9a2e9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122206224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1122206224
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3274833748
Short name T266
Test name
Test status
Simulation time 166147379 ps
CPU time 8.43 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:30:50 PM PDT 24
Peak memory 200388 kb
Host smart-1df854c5-14f9-41e6-9522-a3932013db70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3274833748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3274833748
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2781344995
Short name T458
Test name
Test status
Simulation time 1807985543 ps
CPU time 16.41 seconds
Started Aug 15 04:30:34 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 200548 kb
Host smart-6e38dbc7-922d-40e5-ba71-da01f38253c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781344995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2781344995
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3493197781
Short name T300
Test name
Test status
Simulation time 8613028882 ps
CPU time 723.3 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:42:35 PM PDT 24
Peak memory 711812 kb
Host smart-8586ee13-37da-4fc0-a381-e17e9eaf689c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3493197781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3493197781
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1027282204
Short name T101
Test name
Test status
Simulation time 8239142767 ps
CPU time 11.66 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:30:50 PM PDT 24
Peak memory 200464 kb
Host smart-e13916e0-b15e-4753-ba6f-c3f9001715a1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027282204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1027282204
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3440100731
Short name T346
Test name
Test status
Simulation time 10868753162 ps
CPU time 156.65 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:33:01 PM PDT 24
Peak memory 200504 kb
Host smart-2adef473-6770-4f62-9e2a-bdcd81d6c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440100731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3440100731
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2244888952
Short name T166
Test name
Test status
Simulation time 98768751632 ps
CPU time 1690.81 seconds
Started Aug 15 04:30:31 PM PDT 24
Finished Aug 15 04:58:42 PM PDT 24
Peak memory 706236 kb
Host smart-75c7a43a-ea84-4843-a4d0-ebf22b25b3b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244888952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2244888952
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3852235629
Short name T309
Test name
Test status
Simulation time 2010805988 ps
CPU time 84.7 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:31:45 PM PDT 24
Peak memory 200532 kb
Host smart-68177482-d436-4d06-bccb-08c4a21457a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852235629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3852235629
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3691500109
Short name T511
Test name
Test status
Simulation time 29288202 ps
CPU time 0.6 seconds
Started Aug 15 04:30:48 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 196172 kb
Host smart-7527a331-a136-479e-8123-d2093fff91ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691500109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3691500109
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2532685500
Short name T418
Test name
Test status
Simulation time 3961161367 ps
CPU time 53.35 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:31:25 PM PDT 24
Peak memory 200508 kb
Host smart-d6432fb7-c3a8-4a9c-99f7-96917da1b30a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532685500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2532685500
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2190576337
Short name T64
Test name
Test status
Simulation time 21792789099 ps
CPU time 14.18 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:30:38 PM PDT 24
Peak memory 200708 kb
Host smart-751293f8-1e87-4e4e-9388-2488efd8f7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190576337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2190576337
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.935522399
Short name T258
Test name
Test status
Simulation time 2692674354 ps
CPU time 542.49 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:39:24 PM PDT 24
Peak memory 694520 kb
Host smart-d2c2df48-deb4-45ad-9d71-07140796c488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935522399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.935522399
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2012724055
Short name T238
Test name
Test status
Simulation time 25966616758 ps
CPU time 225.73 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:34:19 PM PDT 24
Peak memory 200536 kb
Host smart-5cb5625e-0859-43ee-9bdf-8e1d4ab1a932
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012724055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2012724055
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.160293688
Short name T500
Test name
Test status
Simulation time 1376527263 ps
CPU time 77.38 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:31:33 PM PDT 24
Peak memory 200480 kb
Host smart-69b3158e-3b67-41fd-8549-4cf449b09627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160293688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.160293688
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3079206236
Short name T343
Test name
Test status
Simulation time 1549188562 ps
CPU time 10 seconds
Started Aug 15 04:30:34 PM PDT 24
Finished Aug 15 04:30:44 PM PDT 24
Peak memory 200424 kb
Host smart-b3f18731-609a-4f92-94da-4b401e0e579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079206236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3079206236
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2822704865
Short name T353
Test name
Test status
Simulation time 62527539112 ps
CPU time 1007.21 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:47:05 PM PDT 24
Peak memory 766112 kb
Host smart-54b81ec2-0eb0-4a79-9f4a-46bef8edef0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822704865 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2822704865
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1910954496
Short name T203
Test name
Test status
Simulation time 33411345943 ps
CPU time 139.61 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:32:44 PM PDT 24
Peak memory 200476 kb
Host smart-b3bb46e6-368f-422e-b915-42b3be3a8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910954496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1910954496
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2806952384
Short name T50
Test name
Test status
Simulation time 45795209 ps
CPU time 0.55 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:30:25 PM PDT 24
Peak memory 196484 kb
Host smart-690dbd63-2610-4946-b496-bb7973abd648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806952384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2806952384
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1114193474
Short name T249
Test name
Test status
Simulation time 336479798 ps
CPU time 17.92 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 200548 kb
Host smart-613d8735-29cb-4fa7-b334-18fa7a383540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1114193474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1114193474
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3180961541
Short name T402
Test name
Test status
Simulation time 9931037051 ps
CPU time 63.65 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:31:21 PM PDT 24
Peak memory 200540 kb
Host smart-143f0b7e-d8d5-4c91-8066-1eb1288b3579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180961541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3180961541
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.233846734
Short name T209
Test name
Test status
Simulation time 8831997085 ps
CPU time 1720.98 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:59:06 PM PDT 24
Peak memory 730640 kb
Host smart-9745f731-cc35-49cc-a94a-66c1b6dd817d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233846734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.233846734
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3769604965
Short name T393
Test name
Test status
Simulation time 2646939375 ps
CPU time 46.21 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 200372 kb
Host smart-423f6e5a-5287-4d11-a0eb-e58975644d2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769604965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3769604965
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.959829207
Short name T432
Test name
Test status
Simulation time 28415122707 ps
CPU time 111.14 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:32:20 PM PDT 24
Peak memory 200548 kb
Host smart-832d4259-8512-4d65-a145-9ecd5845fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959829207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.959829207
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2110603320
Short name T193
Test name
Test status
Simulation time 1293321947 ps
CPU time 12.85 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:30:34 PM PDT 24
Peak memory 200444 kb
Host smart-0a972987-3001-4400-825e-c84e19c52e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110603320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2110603320
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2218348976
Short name T77
Test name
Test status
Simulation time 319385782144 ps
CPU time 2075.47 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 05:05:01 PM PDT 24
Peak memory 761848 kb
Host smart-f327425b-4ae0-446f-8b64-b16fe967279b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218348976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2218348976
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.607493055
Short name T437
Test name
Test status
Simulation time 8090883076 ps
CPU time 51.36 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:31:17 PM PDT 24
Peak memory 200572 kb
Host smart-4d781f92-f7cd-4a40-829d-06c51e8c2bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607493055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.607493055
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3819122984
Short name T486
Test name
Test status
Simulation time 14265895 ps
CPU time 0.64 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:30:48 PM PDT 24
Peak memory 195492 kb
Host smart-3b16117c-55ac-4165-b091-16a2f825b4ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819122984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3819122984
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1729650406
Short name T231
Test name
Test status
Simulation time 141995873 ps
CPU time 2.6 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:35 PM PDT 24
Peak memory 200348 kb
Host smart-5ef907ef-2949-470b-9e11-f37308a0335d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729650406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1729650406
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3359632862
Short name T220
Test name
Test status
Simulation time 7928720167 ps
CPU time 49.78 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 200484 kb
Host smart-f542a0ae-f7ee-4b64-bdf9-ad410995ee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359632862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3359632862
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3076646545
Short name T532
Test name
Test status
Simulation time 5374909249 ps
CPU time 207.16 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:33:55 PM PDT 24
Peak memory 469872 kb
Host smart-a4a278ae-057f-4086-bc23-cce8beefaf21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3076646545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3076646545
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2465684111
Short name T450
Test name
Test status
Simulation time 2859781522 ps
CPU time 48.25 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:31:20 PM PDT 24
Peak memory 200432 kb
Host smart-ee1dbf52-615e-472a-a459-049a9b4f6c0e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465684111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2465684111
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1359452591
Short name T476
Test name
Test status
Simulation time 5095013880 ps
CPU time 141.34 seconds
Started Aug 15 04:30:36 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 200544 kb
Host smart-8d431ba3-ef0c-4d9a-acf0-af1d08542d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359452591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1359452591
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3906798484
Short name T324
Test name
Test status
Simulation time 923585204 ps
CPU time 4.01 seconds
Started Aug 15 04:30:40 PM PDT 24
Finished Aug 15 04:30:44 PM PDT 24
Peak memory 200476 kb
Host smart-202b6cbf-f7d8-41c2-861a-6689d907c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906798484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3906798484
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.919126405
Short name T104
Test name
Test status
Simulation time 71059616775 ps
CPU time 212.24 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:33:50 PM PDT 24
Peak memory 200472 kb
Host smart-846c9473-2e40-4b44-b05e-ad58c00b1a21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919126405 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.919126405
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.57305645
Short name T477
Test name
Test status
Simulation time 1307153212 ps
CPU time 68.79 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 199020 kb
Host smart-927cedf8-86f5-41b2-97bb-c72201f64494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57305645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.57305645
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2611795950
Short name T475
Test name
Test status
Simulation time 14501695 ps
CPU time 0.56 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:30:25 PM PDT 24
Peak memory 195504 kb
Host smart-74846bcb-5722-45cd-b224-e82332267901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611795950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2611795950
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1099266957
Short name T10
Test name
Test status
Simulation time 617297009 ps
CPU time 32.91 seconds
Started Aug 15 04:30:42 PM PDT 24
Finished Aug 15 04:31:15 PM PDT 24
Peak memory 200444 kb
Host smart-1c52f9bf-82c6-48a3-a9d7-8215e82016c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1099266957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1099266957
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1210874717
Short name T276
Test name
Test status
Simulation time 8128275392 ps
CPU time 56.88 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 200912 kb
Host smart-222cbdcd-0a18-4680-ad73-a05c4cb37fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210874717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1210874717
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.820328693
Short name T439
Test name
Test status
Simulation time 386669621 ps
CPU time 18.01 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:30:44 PM PDT 24
Peak memory 238264 kb
Host smart-67b23ced-34c8-485f-bb08-713fc33bc5ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820328693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.820328693
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.499098965
Short name T192
Test name
Test status
Simulation time 5269494374 ps
CPU time 73.11 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 200520 kb
Host smart-8ff86593-6785-4c2d-808b-ccd9ef5f743e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499098965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.499098965
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3491027109
Short name T378
Test name
Test status
Simulation time 4691311580 ps
CPU time 66.04 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:31:49 PM PDT 24
Peak memory 200512 kb
Host smart-9d93d78a-3539-4952-b72a-f25e2011448f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491027109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3491027109
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.856674127
Short name T395
Test name
Test status
Simulation time 626386318 ps
CPU time 3.19 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:30:30 PM PDT 24
Peak memory 200512 kb
Host smart-f5ff1566-e9a6-45f6-a7d4-d952dc7603a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856674127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.856674127
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1351300246
Short name T376
Test name
Test status
Simulation time 21321486007 ps
CPU time 676.14 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:41:32 PM PDT 24
Peak memory 673752 kb
Host smart-d7c350e7-30a4-48bd-a302-841a42c3b83c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351300246 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1351300246
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3176109269
Short name T512
Test name
Test status
Simulation time 10315311306 ps
CPU time 50.11 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 200524 kb
Host smart-9d29aea0-2032-4eaa-9874-e00a2b80cdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176109269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3176109269
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1717932473
Short name T243
Test name
Test status
Simulation time 14740499 ps
CPU time 0.6 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:30:17 PM PDT 24
Peak memory 197232 kb
Host smart-3f97bfc7-c673-4f6d-8508-702d1e3caafa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717932473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1717932473
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3406994368
Short name T183
Test name
Test status
Simulation time 46867292 ps
CPU time 2.51 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 200460 kb
Host smart-56fe346f-7489-4962-a712-7131c30f16de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406994368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3406994368
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1598986818
Short name T32
Test name
Test status
Simulation time 850420575 ps
CPU time 6.59 seconds
Started Aug 15 04:30:34 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 200492 kb
Host smart-b12e2bfc-9f62-460d-9731-e0c4db4d09c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598986818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1598986818
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2637312927
Short name T331
Test name
Test status
Simulation time 60073403297 ps
CPU time 625.02 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:41:04 PM PDT 24
Peak memory 708220 kb
Host smart-56eb7f02-a997-4107-9f15-f42998b04aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2637312927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2637312927
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2527935347
Short name T200
Test name
Test status
Simulation time 13035122927 ps
CPU time 78.37 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:31:43 PM PDT 24
Peak memory 200576 kb
Host smart-3acbf523-7f53-41be-a6f7-de76a4d877b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527935347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2527935347
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2812443049
Short name T181
Test name
Test status
Simulation time 2874063035 ps
CPU time 52.01 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 200532 kb
Host smart-ebed798e-7481-4840-b68a-7272fcd26115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812443049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2812443049
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2581465229
Short name T384
Test name
Test status
Simulation time 956030724 ps
CPU time 11.27 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:45 PM PDT 24
Peak memory 200476 kb
Host smart-09c397b2-d478-490c-b6b4-64f3e75e0a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581465229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2581465229
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4135806177
Short name T337
Test name
Test status
Simulation time 72478553865 ps
CPU time 218.28 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:34:06 PM PDT 24
Peak memory 208736 kb
Host smart-8492f082-b686-4da7-b61f-c80085b840d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135806177 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4135806177
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1423153525
Short name T109
Test name
Test status
Simulation time 21232982094 ps
CPU time 92.16 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 200568 kb
Host smart-8a9caaa6-f7ac-4f23-978a-90934ea7865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423153525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1423153525
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.80279419
Short name T227
Test name
Test status
Simulation time 45210519 ps
CPU time 0.59 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:33 PM PDT 24
Peak memory 196532 kb
Host smart-fbeb22b5-d659-46cb-8a4a-542478803058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80279419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.80279419
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1530152217
Short name T197
Test name
Test status
Simulation time 2135487888 ps
CPU time 59.84 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 200448 kb
Host smart-b77fcf48-f7fb-4694-b700-a009c31ddc34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1530152217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1530152217
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.579562958
Short name T252
Test name
Test status
Simulation time 11238220193 ps
CPU time 37.55 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 200504 kb
Host smart-8feefd8f-da9f-4db0-a10c-6ce8261c1442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579562958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.579562958
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.278366614
Short name T374
Test name
Test status
Simulation time 7957520167 ps
CPU time 131.88 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:32:35 PM PDT 24
Peak memory 577192 kb
Host smart-78a31aed-91d4-4cfa-9493-fe0ca7d6e4fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278366614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.278366614
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1015656277
Short name T340
Test name
Test status
Simulation time 115341713200 ps
CPU time 198.06 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:34:07 PM PDT 24
Peak memory 200492 kb
Host smart-6bedded5-3bca-462f-bc8f-4a1005b85d39
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015656277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1015656277
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1827455486
Short name T306
Test name
Test status
Simulation time 11403467372 ps
CPU time 157.23 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:33:15 PM PDT 24
Peak memory 208764 kb
Host smart-4cf2a1f5-30a6-4ab5-83d2-1c7d5b397592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827455486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1827455486
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3501780158
Short name T302
Test name
Test status
Simulation time 1009138277 ps
CPU time 8.34 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:30:45 PM PDT 24
Peak memory 200448 kb
Host smart-a6c4db3c-100b-460e-b892-568a592c8b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501780158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3501780158
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3580967723
Short name T371
Test name
Test status
Simulation time 2314053111 ps
CPU time 120.34 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:32:25 PM PDT 24
Peak memory 200504 kb
Host smart-6d274abe-6031-4855-bdf6-2522a64c7c10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580967723 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3580967723
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4115613588
Short name T9
Test name
Test status
Simulation time 633223428 ps
CPU time 8.47 seconds
Started Aug 15 04:30:31 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 200364 kb
Host smart-e3a16911-09d0-474c-9710-48e2c5cdb8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115613588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4115613588
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.471854913
Short name T261
Test name
Test status
Simulation time 19143364 ps
CPU time 0.61 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:30:25 PM PDT 24
Peak memory 197172 kb
Host smart-9dcbe53c-f00e-48ac-b5b8-e2c8ab9f9a4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471854913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.471854913
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.631289595
Short name T19
Test name
Test status
Simulation time 1458957024 ps
CPU time 80.39 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:31:58 PM PDT 24
Peak memory 200408 kb
Host smart-fa5174f2-5317-4ee4-9540-dc047dd38242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631289595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.631289595
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3773181876
Short name T347
Test name
Test status
Simulation time 25964622727 ps
CPU time 72.42 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 200536 kb
Host smart-a86e9705-76c1-4e18-9825-e5d8f2264efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773181876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3773181876
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3002276481
Short name T436
Test name
Test status
Simulation time 2989194820 ps
CPU time 528.38 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:39:25 PM PDT 24
Peak memory 695228 kb
Host smart-184ee4e0-01c3-4922-a660-8b6fc9365c9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3002276481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3002276481
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3580936930
Short name T88
Test name
Test status
Simulation time 14975591865 ps
CPU time 198.18 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:33:47 PM PDT 24
Peak memory 200488 kb
Host smart-0f988120-d93a-4fe6-9287-f1de2f713c6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580936930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3580936930
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1240242964
Short name T190
Test name
Test status
Simulation time 2386709766 ps
CPU time 37.7 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 200460 kb
Host smart-b766d46a-b14a-4fd8-b8fa-18ff50c0b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240242964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1240242964
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1229217931
Short name T422
Test name
Test status
Simulation time 641832538 ps
CPU time 7.81 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:31:03 PM PDT 24
Peak memory 200480 kb
Host smart-dafa85f1-ade3-40d3-99a5-fe8619d60119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229217931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1229217931
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2973754113
Short name T82
Test name
Test status
Simulation time 883509287812 ps
CPU time 2637.65 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 05:14:24 PM PDT 24
Peak memory 775700 kb
Host smart-234b60b9-a09c-411e-9ddf-c6b9dd372a86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973754113 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2973754113
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.1366432692
Short name T248
Test name
Test status
Simulation time 5422421112 ps
CPU time 102.46 seconds
Started Aug 15 04:30:40 PM PDT 24
Finished Aug 15 04:32:23 PM PDT 24
Peak memory 200640 kb
Host smart-ea9a0e5d-3508-4ef0-8383-064013ef896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366432692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1366432692
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1291954975
Short name T319
Test name
Test status
Simulation time 41059318 ps
CPU time 0.57 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:30:00 PM PDT 24
Peak memory 195488 kb
Host smart-54dbc618-e74d-46a6-89e2-67145eea11b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291954975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1291954975
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1846118862
Short name T334
Test name
Test status
Simulation time 2452967641 ps
CPU time 55.08 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:31:02 PM PDT 24
Peak memory 200516 kb
Host smart-ffcbb89d-7b10-4565-a80d-a2f31d7021b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846118862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1846118862
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2691876056
Short name T456
Test name
Test status
Simulation time 8761808859 ps
CPU time 61.76 seconds
Started Aug 15 04:30:02 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200512 kb
Host smart-c66ab73f-eb6f-4a67-aefb-0babba971c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691876056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2691876056
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3915481770
Short name T239
Test name
Test status
Simulation time 4915380249 ps
CPU time 117.65 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 586204 kb
Host smart-ed5e866a-91b0-47bf-b2f4-5efdd3d4160e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3915481770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3915481770
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2672412529
Short name T357
Test name
Test status
Simulation time 7608944746 ps
CPU time 127.65 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 200468 kb
Host smart-269eb8dd-8c78-4129-8bc1-6ef604ab7a2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672412529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2672412529
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_smoke.1357924572
Short name T241
Test name
Test status
Simulation time 593992353 ps
CPU time 12.52 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:21 PM PDT 24
Peak memory 200516 kb
Host smart-c3d26413-d056-40eb-baf9-dbc72d1ae723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357924572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1357924572
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.603767366
Short name T326
Test name
Test status
Simulation time 35540620143 ps
CPU time 483.32 seconds
Started Aug 15 04:30:11 PM PDT 24
Finished Aug 15 04:38:14 PM PDT 24
Peak memory 477708 kb
Host smart-d0d81fbb-931a-4397-91ce-e978dc5ccfdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603767366 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.603767366
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3880607699
Short name T187
Test name
Test status
Simulation time 7265213206 ps
CPU time 42.97 seconds
Started Aug 15 04:29:58 PM PDT 24
Finished Aug 15 04:30:42 PM PDT 24
Peak memory 200540 kb
Host smart-257e32ec-7db7-4264-9e94-ec09c4075976
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3880607699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3880607699
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.686722947
Short name T95
Test name
Test status
Simulation time 7323667746 ps
CPU time 61.48 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 200492 kb
Host smart-941cf1c3-6e78-4b36-82e6-62092599fcdb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=686722947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.686722947
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3178508780
Short name T444
Test name
Test status
Simulation time 7140636323 ps
CPU time 80.64 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 200568 kb
Host smart-95ac4618-b97a-4993-947f-8d62e315ae2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3178508780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3178508780
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3472909916
Short name T97
Test name
Test status
Simulation time 45612358776 ps
CPU time 522.7 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:38:48 PM PDT 24
Peak memory 200440 kb
Host smart-2c0ff8e4-d65e-41fb-9221-99705de22d01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3472909916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3472909916
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.507997018
Short name T330
Test name
Test status
Simulation time 149806354647 ps
CPU time 2131.57 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 05:05:41 PM PDT 24
Peak memory 216640 kb
Host smart-ade76919-577f-45b3-9eeb-d29ab8b9f31b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=507997018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.507997018
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1158395213
Short name T501
Test name
Test status
Simulation time 96309139188 ps
CPU time 2154.72 seconds
Started Aug 15 04:31:14 PM PDT 24
Finished Aug 15 05:07:09 PM PDT 24
Peak memory 216632 kb
Host smart-f7e62036-10a0-46b1-a65d-1762cb300b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1158395213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1158395213
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1568878134
Short name T482
Test name
Test status
Simulation time 5324435198 ps
CPU time 67.65 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 197952 kb
Host smart-b164e905-9f9a-4763-9e40-cdd82c75f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568878134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1568878134
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.663584031
Short name T397
Test name
Test status
Simulation time 14414671 ps
CPU time 0.59 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:30:43 PM PDT 24
Peak memory 196536 kb
Host smart-a8c902a9-1cf7-473d-8ac3-b5d18926883f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663584031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.663584031
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3313965390
Short name T18
Test name
Test status
Simulation time 365341004 ps
CPU time 18.79 seconds
Started Aug 15 04:30:30 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 200440 kb
Host smart-c4c1b07a-3012-49b6-8e8b-1712aa1e0e18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313965390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3313965390
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.397016814
Short name T414
Test name
Test status
Simulation time 10871196260 ps
CPU time 49.95 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:31:16 PM PDT 24
Peak memory 200608 kb
Host smart-9223808d-1d7d-4f4d-b69e-ad5a0e377e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397016814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.397016814
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.874000059
Short name T159
Test name
Test status
Simulation time 1040247415 ps
CPU time 148.37 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:33:21 PM PDT 24
Peak memory 413268 kb
Host smart-5feb7697-4cc9-4059-89f6-950e9839e334
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=874000059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.874000059
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2021792257
Short name T466
Test name
Test status
Simulation time 6051990298 ps
CPU time 80.68 seconds
Started Aug 15 04:30:24 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 200504 kb
Host smart-94b3bc3b-f309-4e87-9beb-9fc112b76ec2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021792257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2021792257
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3383923732
Short name T354
Test name
Test status
Simulation time 103210275064 ps
CPU time 122.68 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:32:36 PM PDT 24
Peak memory 200592 kb
Host smart-b78c3aed-0ddd-4a8b-9448-906f6dd6a594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383923732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3383923732
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4094810268
Short name T322
Test name
Test status
Simulation time 296665116 ps
CPU time 5.21 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:30:28 PM PDT 24
Peak memory 200456 kb
Host smart-2a87c9bb-68a9-4c72-bcff-f2366ce77100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094810268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4094810268
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2898080674
Short name T165
Test name
Test status
Simulation time 13251510193 ps
CPU time 110.93 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 208868 kb
Host smart-c171a288-0b2c-4969-a904-9b0ebc5e5c28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898080674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2898080674
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2958502097
Short name T508
Test name
Test status
Simulation time 19522621325 ps
CPU time 90.63 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 200504 kb
Host smart-f40284cd-f934-4bcc-9e8c-751fcc35650b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958502097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2958502097
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4101249997
Short name T365
Test name
Test status
Simulation time 15837610 ps
CPU time 0.57 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:30:53 PM PDT 24
Peak memory 195500 kb
Host smart-e6c396a2-467a-43a7-a2b2-20318f43ec53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101249997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4101249997
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3459303867
Short name T325
Test name
Test status
Simulation time 5609599905 ps
CPU time 80.82 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 200528 kb
Host smart-2fd1194b-8e96-4605-88b0-ffb0bef9b24a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459303867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3459303867
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.156402684
Short name T204
Test name
Test status
Simulation time 1730684103 ps
CPU time 30.7 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:31:18 PM PDT 24
Peak memory 200476 kb
Host smart-2038c16d-7089-4197-a37a-27f86b244b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156402684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.156402684
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1756367213
Short name T173
Test name
Test status
Simulation time 15156318823 ps
CPU time 700.06 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:42:26 PM PDT 24
Peak memory 724192 kb
Host smart-3396dbda-72d4-4b4c-a482-ab5e529e6185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756367213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1756367213
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1337530881
Short name T505
Test name
Test status
Simulation time 9702519229 ps
CPU time 162.28 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:33:24 PM PDT 24
Peak memory 200512 kb
Host smart-40f859b0-3c33-40e5-95b1-b2ece11f2879
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337530881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1337530881
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2634290939
Short name T228
Test name
Test status
Simulation time 4443991407 ps
CPU time 127.59 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 200472 kb
Host smart-ad39eb9c-aab4-4717-8a33-6c0abe75ab3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634290939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2634290939
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.872855921
Short name T229
Test name
Test status
Simulation time 1559484882 ps
CPU time 11.84 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 200512 kb
Host smart-da07b925-6bd9-4e91-a8d2-bb840ea60f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872855921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.872855921
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2183096870
Short name T34
Test name
Test status
Simulation time 34173609672 ps
CPU time 2166.99 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 05:06:36 PM PDT 24
Peak memory 796564 kb
Host smart-03b34f14-1053-4ea1-a896-cb0b731f1785
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183096870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2183096870
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.930936416
Short name T460
Test name
Test status
Simulation time 13637064454 ps
CPU time 54.99 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 200488 kb
Host smart-b04e3264-4a8c-4049-92d2-5680d1398ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930936416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.930936416
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.439921853
Short name T459
Test name
Test status
Simulation time 35719471 ps
CPU time 0.58 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 196180 kb
Host smart-0b9e7939-65f0-4844-b135-61b432871db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439921853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.439921853
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3420123987
Short name T386
Test name
Test status
Simulation time 683331356 ps
CPU time 40.1 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 200432 kb
Host smart-5281c984-4600-4c6d-8208-dc8f228d4fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3420123987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3420123987
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2409571879
Short name T269
Test name
Test status
Simulation time 3387079355 ps
CPU time 22.89 seconds
Started Aug 15 04:30:51 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 200576 kb
Host smart-d429a839-5188-49aa-90d2-bbe527680fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409571879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2409571879
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3061706074
Short name T267
Test name
Test status
Simulation time 2229173871 ps
CPU time 437.14 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:37:55 PM PDT 24
Peak memory 688664 kb
Host smart-ff4f62ed-1e98-412d-978f-653fa5dce435
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3061706074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3061706074
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1368439875
Short name T299
Test name
Test status
Simulation time 6261844915 ps
CPU time 158.8 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:33:28 PM PDT 24
Peak memory 200480 kb
Host smart-9846bbd6-a93c-45db-8f32-29daa5495a76
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368439875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1368439875
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3891144691
Short name T351
Test name
Test status
Simulation time 37992985 ps
CPU time 0.99 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:30:47 PM PDT 24
Peak memory 200232 kb
Host smart-2e096e4f-6666-4f9e-827b-44ea58a532d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891144691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3891144691
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.4068992774
Short name T237
Test name
Test status
Simulation time 534982249 ps
CPU time 6.53 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:30:39 PM PDT 24
Peak memory 200444 kb
Host smart-9fe35e40-6f85-43f6-b68e-c7ae837a8bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068992774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.4068992774
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3959853697
Short name T293
Test name
Test status
Simulation time 41036570772 ps
CPU time 1133.4 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:49:14 PM PDT 24
Peak memory 761680 kb
Host smart-2a8a5104-5d08-49fe-bc31-8e6bcc943e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959853697 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3959853697
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3509769447
Short name T367
Test name
Test status
Simulation time 30948728902 ps
CPU time 129.37 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:32:48 PM PDT 24
Peak memory 200524 kb
Host smart-7939bf03-685d-48ed-bf98-9fac1a37d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509769447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3509769447
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2836807617
Short name T182
Test name
Test status
Simulation time 36614617 ps
CPU time 0.58 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:34 PM PDT 24
Peak memory 195488 kb
Host smart-9f52c386-0a11-4bd1-9c09-5a96b6280778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836807617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2836807617
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1030876820
Short name T427
Test name
Test status
Simulation time 48184730 ps
CPU time 2.61 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:30:52 PM PDT 24
Peak memory 200324 kb
Host smart-2730afdb-eac9-4bdd-8a0c-f4283a164565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030876820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1030876820
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2711959505
Short name T275
Test name
Test status
Simulation time 10869195099 ps
CPU time 49.95 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:31:28 PM PDT 24
Peak memory 200516 kb
Host smart-9f11a4b0-e642-449b-8a42-f0abb3c827f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711959505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2711959505
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3112943861
Short name T242
Test name
Test status
Simulation time 659206843 ps
CPU time 49.97 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:31:31 PM PDT 24
Peak memory 335256 kb
Host smart-62097793-0a61-4436-8de9-e5a0f32934d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3112943861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3112943861
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1686036112
Short name T366
Test name
Test status
Simulation time 34262807242 ps
CPU time 160.17 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:33:49 PM PDT 24
Peak memory 200496 kb
Host smart-401e1f0e-4533-4933-8506-4ac190800a6c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686036112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1686036112
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2299118386
Short name T307
Test name
Test status
Simulation time 2707006844 ps
CPU time 35.42 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 04:31:19 PM PDT 24
Peak memory 200496 kb
Host smart-73b922ca-c336-44d6-8376-d8c25377fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299118386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2299118386
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2906303347
Short name T526
Test name
Test status
Simulation time 320455748 ps
CPU time 12.06 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 200436 kb
Host smart-bc36b655-e244-4f70-9d72-8ce3ed7b0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906303347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2906303347
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.66602732
Short name T516
Test name
Test status
Simulation time 23566531925 ps
CPU time 864.79 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:45:11 PM PDT 24
Peak memory 670156 kb
Host smart-156d92dd-fd21-4242-bc82-17de906877de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66602732 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.66602732
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2401948549
Short name T381
Test name
Test status
Simulation time 10092944696 ps
CPU time 121.07 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 200548 kb
Host smart-e92f2425-60bf-437e-82f8-fac3189aae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401948549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2401948549
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2393983470
Short name T310
Test name
Test status
Simulation time 23410066 ps
CPU time 0.57 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:30:47 PM PDT 24
Peak memory 196184 kb
Host smart-85307f7d-c228-426c-9069-2c6562a4d641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393983470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2393983470
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1450963257
Short name T487
Test name
Test status
Simulation time 13718627128 ps
CPU time 69.25 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 208696 kb
Host smart-a7b514b8-155f-4762-bc44-27c2bb83209b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450963257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1450963257
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1800984588
Short name T474
Test name
Test status
Simulation time 5162573074 ps
CPU time 65.87 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 216696 kb
Host smart-f7408609-ddd7-43a1-a096-59a0c548033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800984588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1800984588
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4207239779
Short name T223
Test name
Test status
Simulation time 19326381123 ps
CPU time 843.55 seconds
Started Aug 15 04:30:36 PM PDT 24
Finished Aug 15 04:44:40 PM PDT 24
Peak memory 714684 kb
Host smart-833517d3-5fba-4595-96fe-cffc3c0bf339
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4207239779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4207239779
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1200356951
Short name T485
Test name
Test status
Simulation time 5185259188 ps
CPU time 139.02 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 200504 kb
Host smart-66f3d06b-5e5d-4e0f-a647-7729271416c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200356951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1200356951
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2935381066
Short name T469
Test name
Test status
Simulation time 3233867254 ps
CPU time 173.39 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:33:53 PM PDT 24
Peak memory 200528 kb
Host smart-db532159-1adc-413b-b648-e9fe23c71d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935381066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2935381066
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.681111721
Short name T271
Test name
Test status
Simulation time 176708971 ps
CPU time 7.74 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:30:58 PM PDT 24
Peak memory 200440 kb
Host smart-c9bba25e-cfe6-4bf3-83e7-1ad5c582f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681111721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.681111721
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2688680022
Short name T12
Test name
Test status
Simulation time 24346879843 ps
CPU time 3187.05 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 05:23:35 PM PDT 24
Peak memory 798704 kb
Host smart-982d69b7-e5b0-46d7-b494-0b13f8451780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688680022 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2688680022
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3505711946
Short name T284
Test name
Test status
Simulation time 30054815030 ps
CPU time 136.04 seconds
Started Aug 15 04:30:51 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 200512 kb
Host smart-5585da80-fc5a-4d44-b07b-975e5646eeeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505711946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3505711946
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3343154097
Short name T336
Test name
Test status
Simulation time 16590949 ps
CPU time 0.61 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:30:29 PM PDT 24
Peak memory 196504 kb
Host smart-bd5708d0-749e-46dd-9e86-fd161d1bf7f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343154097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3343154097
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1827586557
Short name T315
Test name
Test status
Simulation time 739762250 ps
CPU time 40.48 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 200448 kb
Host smart-54c8a240-6def-4a3a-9123-7500b9a854ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827586557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1827586557
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1219727244
Short name T341
Test name
Test status
Simulation time 12133921381 ps
CPU time 23.35 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 200544 kb
Host smart-e0842650-f73b-4b84-951c-b4099ddd6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219727244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1219727244
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2879466895
Short name T396
Test name
Test status
Simulation time 9787289731 ps
CPU time 918.58 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:45:47 PM PDT 24
Peak memory 731080 kb
Host smart-9980eb00-a777-4bdc-a7cc-00e39951c3fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879466895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2879466895
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3411121111
Short name T318
Test name
Test status
Simulation time 11139567784 ps
CPU time 140.95 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 200508 kb
Host smart-e33d8b4b-bfd2-4b37-908f-15564ca8de9e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411121111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3411121111
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2211944922
Short name T43
Test name
Test status
Simulation time 2353359971 ps
CPU time 126.72 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 200564 kb
Host smart-23a9b605-14d3-4c06-a04f-a7b93a5bdede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211944922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2211944922
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3932636895
Short name T2
Test name
Test status
Simulation time 3490749145 ps
CPU time 15.73 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 200472 kb
Host smart-5269401c-a9bb-45c3-88dc-e01e0eb42cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932636895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3932636895
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3796554647
Short name T329
Test name
Test status
Simulation time 40461454196 ps
CPU time 171.35 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:33:19 PM PDT 24
Peak memory 200620 kb
Host smart-36ed75f8-f63f-4f1a-8feb-696ffc892248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796554647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3796554647
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2558360211
Short name T140
Test name
Test status
Simulation time 5931284294 ps
CPU time 42.83 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 200472 kb
Host smart-6f23b408-5022-4f6c-81ad-eafb9f0c5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558360211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2558360211
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1119321761
Short name T180
Test name
Test status
Simulation time 47893636 ps
CPU time 0.57 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 195588 kb
Host smart-cd2766b2-4a22-4606-b168-b5a085f2964c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119321761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1119321761
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.960993545
Short name T344
Test name
Test status
Simulation time 261864108 ps
CPU time 7.6 seconds
Started Aug 15 04:30:40 PM PDT 24
Finished Aug 15 04:30:47 PM PDT 24
Peak memory 200324 kb
Host smart-ba8875f2-479c-4ce2-ae77-56f65187ee39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960993545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.960993545
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2440064726
Short name T431
Test name
Test status
Simulation time 945748978 ps
CPU time 24.86 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 200464 kb
Host smart-df9ff50e-f9a6-4000-bcf2-9397bd8fba8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440064726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2440064726
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1821463278
Short name T5
Test name
Test status
Simulation time 1767644767 ps
CPU time 293.5 seconds
Started Aug 15 04:30:34 PM PDT 24
Finished Aug 15 04:35:28 PM PDT 24
Peak memory 469716 kb
Host smart-589ba11a-04da-41ae-915d-362609b1c8b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1821463278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1821463278
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3338107380
Short name T434
Test name
Test status
Simulation time 51254631766 ps
CPU time 165.5 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:33:13 PM PDT 24
Peak memory 200464 kb
Host smart-76c5403f-c818-477a-8ef9-6328f4bc2c2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338107380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3338107380
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2957165486
Short name T214
Test name
Test status
Simulation time 6083968400 ps
CPU time 19.03 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:30:36 PM PDT 24
Peak memory 200516 kb
Host smart-24164496-cbd6-4f48-9725-218f1dd03f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957165486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2957165486
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.987782229
Short name T138
Test name
Test status
Simulation time 490614595 ps
CPU time 6.29 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:30:38 PM PDT 24
Peak memory 200336 kb
Host smart-c8b63860-efb5-4e93-8911-aec324d0d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987782229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.987782229
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3943237294
Short name T108
Test name
Test status
Simulation time 30517888577 ps
CPU time 4672 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 05:48:19 PM PDT 24
Peak memory 848972 kb
Host smart-c54fdb4d-b3c9-4408-8ffe-c13a60913cf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943237294 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3943237294
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3441052504
Short name T465
Test name
Test status
Simulation time 468368813 ps
CPU time 7.11 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:30:56 PM PDT 24
Peak memory 200520 kb
Host smart-67151917-d515-4252-8bb7-f89d26b3eecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441052504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3441052504
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2487216306
Short name T421
Test name
Test status
Simulation time 13892114 ps
CPU time 0.6 seconds
Started Aug 15 04:30:40 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 197216 kb
Host smart-be234d4f-2aa7-4ea4-82f6-8f1cf54125f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487216306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2487216306
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3788944827
Short name T211
Test name
Test status
Simulation time 288688916 ps
CPU time 16.79 seconds
Started Aug 15 04:30:22 PM PDT 24
Finished Aug 15 04:30:38 PM PDT 24
Peak memory 200556 kb
Host smart-6c43781e-d655-47c4-87ea-777fa89ad516
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3788944827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3788944827
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.727048976
Short name T162
Test name
Test status
Simulation time 4617537519 ps
CPU time 25.1 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200600 kb
Host smart-b0f8f915-bef2-4abc-98e5-9a00e50627d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727048976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.727048976
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3012008557
Short name T168
Test name
Test status
Simulation time 4720496856 ps
CPU time 774.59 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:43:41 PM PDT 24
Peak memory 653792 kb
Host smart-8af32fab-7bee-40b6-9e00-0124ebb9bb4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012008557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3012008557
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2115602907
Short name T196
Test name
Test status
Simulation time 24940226854 ps
CPU time 212.67 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 200476 kb
Host smart-05723132-0731-40a1-b6b9-bf0357b30aa0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115602907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2115602907
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2332307305
Short name T408
Test name
Test status
Simulation time 10409371689 ps
CPU time 128.21 seconds
Started Aug 15 04:30:42 PM PDT 24
Finished Aug 15 04:32:50 PM PDT 24
Peak memory 216688 kb
Host smart-c7dd1625-3636-4d7a-bcab-3a105826a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332307305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2332307305
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2951330195
Short name T399
Test name
Test status
Simulation time 6238635842 ps
CPU time 19.38 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:30:47 PM PDT 24
Peak memory 200632 kb
Host smart-7af43498-21d1-429c-9cf8-77f8be51c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951330195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2951330195
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1894079016
Short name T394
Test name
Test status
Simulation time 456146411 ps
CPU time 8.88 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:30:35 PM PDT 24
Peak memory 200460 kb
Host smart-4941abef-1e93-42a3-9df8-08b877a05e39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894079016 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1894079016
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1646510385
Short name T90
Test name
Test status
Simulation time 74323550602 ps
CPU time 102.95 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:32:26 PM PDT 24
Peak memory 200512 kb
Host smart-7857232d-2a19-4f93-ad6a-9c0b7ed8d322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646510385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1646510385
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1721577943
Short name T179
Test name
Test status
Simulation time 18466157 ps
CPU time 0.58 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:30:42 PM PDT 24
Peak memory 196116 kb
Host smart-7992e313-de94-4036-be26-3dd568d2fab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721577943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1721577943
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4004565138
Short name T1
Test name
Test status
Simulation time 1274979727 ps
CPU time 71.18 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 200428 kb
Host smart-0053e01a-680e-463d-9ead-9f310d4f8d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004565138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4004565138
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1572242778
Short name T426
Test name
Test status
Simulation time 27679584302 ps
CPU time 36.59 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200512 kb
Host smart-448cd002-6770-417e-b54d-a9fe3b50dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572242778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1572242778
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3713120656
Short name T407
Test name
Test status
Simulation time 13525168221 ps
CPU time 1268.17 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:51:47 PM PDT 24
Peak memory 734144 kb
Host smart-3948dc1b-1664-4258-bae6-fb5497402073
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713120656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3713120656
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2400482628
Short name T448
Test name
Test status
Simulation time 2554706396 ps
CPU time 46.67 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 200412 kb
Host smart-636aac25-1108-46f6-bdcc-4a75bd635f8b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400482628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2400482628
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2352307333
Short name T236
Test name
Test status
Simulation time 4162209124 ps
CPU time 68.53 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:31:56 PM PDT 24
Peak memory 216916 kb
Host smart-cd6bf158-f0c6-4186-b39a-166c5799cc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352307333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2352307333
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1254654421
Short name T264
Test name
Test status
Simulation time 612154268 ps
CPU time 10.22 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:30:37 PM PDT 24
Peak memory 200416 kb
Host smart-ace24619-3672-492f-92a4-8589b9ad9ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254654421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1254654421
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3976421979
Short name T530
Test name
Test status
Simulation time 236477608 ps
CPU time 13.45 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:31:02 PM PDT 24
Peak memory 200412 kb
Host smart-bcf95ba9-2b6b-4c97-a105-976151d03c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976421979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3976421979
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.4182394905
Short name T473
Test name
Test status
Simulation time 41078232 ps
CPU time 0.58 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:30:59 PM PDT 24
Peak memory 196480 kb
Host smart-b271a943-ae2b-4581-be91-a199ad633598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182394905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.4182394905
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2631240213
Short name T288
Test name
Test status
Simulation time 1008568894 ps
CPU time 7.57 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:30:59 PM PDT 24
Peak memory 200396 kb
Host smart-8a77a3a2-b145-49aa-99c1-ffa5df180cb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2631240213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2631240213
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2721576711
Short name T84
Test name
Test status
Simulation time 269682342 ps
CPU time 7.03 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:30:52 PM PDT 24
Peak memory 200352 kb
Host smart-c8c6ac1a-c81c-48e3-b4b3-d1e39c3f5cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721576711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2721576711
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1153586600
Short name T89
Test name
Test status
Simulation time 1617425344 ps
CPU time 244.04 seconds
Started Aug 15 04:30:48 PM PDT 24
Finished Aug 15 04:34:52 PM PDT 24
Peak memory 438108 kb
Host smart-d22fa188-d10b-491d-9a83-ad06f3dd3978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153586600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1153586600
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.3254529877
Short name T529
Test name
Test status
Simulation time 27043875524 ps
CPU time 110.28 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:32:39 PM PDT 24
Peak memory 200472 kb
Host smart-c03b15b9-a848-48ca-b292-3c86d87e8566
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254529877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3254529877
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1579842812
Short name T177
Test name
Test status
Simulation time 1522007158 ps
CPU time 42.35 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 200452 kb
Host smart-f8220fdd-2811-4070-86a4-8a98037cbc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579842812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1579842812
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2148799286
Short name T235
Test name
Test status
Simulation time 629649054 ps
CPU time 10.75 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:30:46 PM PDT 24
Peak memory 200428 kb
Host smart-a99dbe2d-2b37-41cb-889e-d8143b351ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148799286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2148799286
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2431755944
Short name T416
Test name
Test status
Simulation time 133616675936 ps
CPU time 1932.27 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 05:02:57 PM PDT 24
Peak memory 784928 kb
Host smart-605c1f99-0bee-448c-85ef-809cf3700f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431755944 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2431755944
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.858090250
Short name T521
Test name
Test status
Simulation time 2307141113 ps
CPU time 32.63 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:31:19 PM PDT 24
Peak memory 200492 kb
Host smart-0395a838-555d-44e7-a487-57d88af87579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858090250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.858090250
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1594940374
Short name T272
Test name
Test status
Simulation time 16566899 ps
CPU time 0.61 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:30:22 PM PDT 24
Peak memory 196548 kb
Host smart-802451cd-126b-4cad-8a60-34853ed04bc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594940374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1594940374
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2063046885
Short name T328
Test name
Test status
Simulation time 1000228573 ps
CPU time 15.55 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:19 PM PDT 24
Peak memory 200440 kb
Host smart-822a244f-1219-4179-9bde-e253c7f20ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063046885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2063046885
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1989044564
Short name T164
Test name
Test status
Simulation time 1473870933 ps
CPU time 39.66 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 200508 kb
Host smart-83fdadd6-e07d-4b2d-85df-c51ce2075af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989044564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1989044564
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2012275138
Short name T525
Test name
Test status
Simulation time 23386161697 ps
CPU time 903.79 seconds
Started Aug 15 04:30:05 PM PDT 24
Finished Aug 15 04:45:09 PM PDT 24
Peak memory 718596 kb
Host smart-581703d9-9abe-4cee-94f4-086bcbef2229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012275138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2012275138
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3450853001
Short name T14
Test name
Test status
Simulation time 4543502428 ps
CPU time 49.1 seconds
Started Aug 15 04:30:03 PM PDT 24
Finished Aug 15 04:30:52 PM PDT 24
Peak memory 200484 kb
Host smart-875ccb4f-2543-424e-a24d-ee604c447c48
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450853001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3450853001
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2736060887
Short name T161
Test name
Test status
Simulation time 80262663523 ps
CPU time 172.85 seconds
Started Aug 15 04:30:11 PM PDT 24
Finished Aug 15 04:33:04 PM PDT 24
Peak memory 200644 kb
Host smart-a533fc56-6ea8-452e-839e-9355e94dbb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736060887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2736060887
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.3495036802
Short name T51
Test name
Test status
Simulation time 315268291 ps
CPU time 0.94 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:30:07 PM PDT 24
Peak memory 218796 kb
Host smart-18ae657c-02e1-4790-9b16-ee7184532d82
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495036802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.3495036802
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2127721593
Short name T226
Test name
Test status
Simulation time 595459005 ps
CPU time 5.5 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 04:30:19 PM PDT 24
Peak memory 200568 kb
Host smart-cf747b19-a9c5-48fb-8462-74d63b0fdce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127721593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2127721593
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.713869043
Short name T167
Test name
Test status
Simulation time 140851490017 ps
CPU time 2843.44 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 05:17:37 PM PDT 24
Peak memory 812876 kb
Host smart-888768c6-0577-44ed-90d3-0723bb4dc1cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713869043 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.713869043
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1519012495
Short name T70
Test name
Test status
Simulation time 27481225546 ps
CPU time 442.78 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 04:37:36 PM PDT 24
Peak memory 700200 kb
Host smart-67be5c6e-00c9-4020-888b-98694cc05300
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1519012495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1519012495
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3557931195
Short name T222
Test name
Test status
Simulation time 1082040318 ps
CPU time 37.64 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 200504 kb
Host smart-f44dc4b9-737e-4b8a-8242-851766396e4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3557931195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3557931195
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3215919514
Short name T295
Test name
Test status
Simulation time 5997949164 ps
CPU time 92.59 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:31:41 PM PDT 24
Peak memory 200496 kb
Host smart-a59e978a-558e-497e-9588-2f76745270e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3215919514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3215919514
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3926683710
Short name T206
Test name
Test status
Simulation time 6122581910 ps
CPU time 73.47 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:31:21 PM PDT 24
Peak memory 200564 kb
Host smart-0f44c8a0-67bd-46bb-a704-de89771fe6b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3926683710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3926683710
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2759286434
Short name T488
Test name
Test status
Simulation time 137335295677 ps
CPU time 628.46 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:40:29 PM PDT 24
Peak memory 200580 kb
Host smart-9765619a-6c5d-47a0-81ed-d6947d87885a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2759286434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2759286434
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.4231840641
Short name T443
Test name
Test status
Simulation time 526036499011 ps
CPU time 2415.29 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 216480 kb
Host smart-4390bb72-6139-4aa0-8533-88542aae81df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4231840641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.4231840641
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1394994264
Short name T522
Test name
Test status
Simulation time 807789102610 ps
CPU time 2464.34 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 05:11:26 PM PDT 24
Peak memory 216344 kb
Host smart-9b04ef2c-ed06-4669-b1f1-babcfc93349e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1394994264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1394994264
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3561548146
Short name T141
Test name
Test status
Simulation time 21475520389 ps
CPU time 96.6 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 200492 kb
Host smart-32518347-0779-49ff-92ca-bb0c4389a929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561548146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3561548146
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.860989960
Short name T463
Test name
Test status
Simulation time 77142342 ps
CPU time 0.58 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 197204 kb
Host smart-3827041d-77b0-40af-817c-7ad98ac4cab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860989960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.860989960
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.173963151
Short name T440
Test name
Test status
Simulation time 1950905955 ps
CPU time 107.55 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 200488 kb
Host smart-9959c6ab-de6c-48d1-91e1-f37b1418d489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=173963151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.173963151
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2212429975
Short name T31
Test name
Test status
Simulation time 58251942267 ps
CPU time 55.67 seconds
Started Aug 15 04:30:42 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 200540 kb
Host smart-77b6d54f-a6e7-428b-a543-9d290081dda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212429975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2212429975
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3982392970
Short name T208
Test name
Test status
Simulation time 23588700275 ps
CPU time 1175.9 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:50:10 PM PDT 24
Peak memory 770768 kb
Host smart-4c665392-bc3c-4f34-9de3-12af3e35de9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3982392970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3982392970
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4219108957
Short name T401
Test name
Test status
Simulation time 48403590246 ps
CPU time 148.17 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:32:57 PM PDT 24
Peak memory 200504 kb
Host smart-ce515088-0cdb-458e-b414-7d26795d0551
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219108957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4219108957
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3001865440
Short name T16
Test name
Test status
Simulation time 57425625466 ps
CPU time 276.34 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:35:31 PM PDT 24
Peak memory 200492 kb
Host smart-829625b4-1b2d-4006-93f1-a0ee794081ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001865440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3001865440
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1101453146
Short name T100
Test name
Test status
Simulation time 645966776 ps
CPU time 11.2 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:30:58 PM PDT 24
Peak memory 200452 kb
Host smart-12755667-93e5-4d35-b961-9a69fcab86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101453146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1101453146
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.901973660
Short name T69
Test name
Test status
Simulation time 295515840999 ps
CPU time 1835.32 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 683400 kb
Host smart-d1135cb1-e300-407c-a51c-ef938f865f29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901973660 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.901973660
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2829588325
Short name T23
Test name
Test status
Simulation time 1790204210 ps
CPU time 22.23 seconds
Started Aug 15 04:30:34 PM PDT 24
Finished Aug 15 04:30:56 PM PDT 24
Peak memory 200560 kb
Host smart-023dba97-3395-4d83-9b19-e801a8b9958a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829588325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2829588325
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3542463952
Short name T49
Test name
Test status
Simulation time 14691910 ps
CPU time 0.63 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 196560 kb
Host smart-4722279d-e84d-485c-81c0-6ddcd16912a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542463952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3542463952
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.82257217
Short name T470
Test name
Test status
Simulation time 59817482 ps
CPU time 3.26 seconds
Started Aug 15 04:30:53 PM PDT 24
Finished Aug 15 04:30:56 PM PDT 24
Peak memory 200444 kb
Host smart-1518f716-250d-49c2-832e-c921a2a07798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82257217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.82257217
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.4220366743
Short name T291
Test name
Test status
Simulation time 22230566572 ps
CPU time 69.05 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 208724 kb
Host smart-0c0148e9-04c8-4504-bc84-4fa01ee8d7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220366743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.4220366743
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1119971729
Short name T246
Test name
Test status
Simulation time 6242932598 ps
CPU time 268.62 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:35:15 PM PDT 24
Peak memory 642788 kb
Host smart-bc088d97-1249-4b01-92f4-e19868f40eae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1119971729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1119971729
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1064483934
Short name T94
Test name
Test status
Simulation time 3028262438 ps
CPU time 160.8 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:33:11 PM PDT 24
Peak memory 200532 kb
Host smart-56e230c1-9ff9-4b5d-8a0c-3fdf5aa0cd9c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064483934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1064483934
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2455194880
Short name T425
Test name
Test status
Simulation time 1021540663 ps
CPU time 9.31 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:30:58 PM PDT 24
Peak memory 200352 kb
Host smart-7f48c3cd-7722-45a0-8e3a-42b1bebcf4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455194880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2455194880
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3249630714
Short name T278
Test name
Test status
Simulation time 5776203353 ps
CPU time 14.69 seconds
Started Aug 15 04:30:26 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 200508 kb
Host smart-bccd9722-ffc1-48b3-bda6-868732955e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249630714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3249630714
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1845113351
Short name T79
Test name
Test status
Simulation time 84147244125 ps
CPU time 274.9 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:35:21 PM PDT 24
Peak memory 215928 kb
Host smart-f788514b-3822-4ee9-841d-1acb3f5b52d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845113351 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1845113351
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1225870132
Short name T308
Test name
Test status
Simulation time 2041990945 ps
CPU time 17.61 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:31:03 PM PDT 24
Peak memory 200360 kb
Host smart-f7d22405-bb03-4c94-b3fd-744b92b8db49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225870132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1225870132
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3781253932
Short name T314
Test name
Test status
Simulation time 10982431 ps
CPU time 0.58 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:30:43 PM PDT 24
Peak memory 195536 kb
Host smart-a5be8d7c-be7e-47a5-9cd0-4efd0b41c1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781253932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3781253932
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.773754418
Short name T213
Test name
Test status
Simulation time 6801238951 ps
CPU time 64.64 seconds
Started Aug 15 04:30:39 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 217016 kb
Host smart-a11ddc9f-a7fc-4a82-b604-8fa724093977
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773754418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.773754418
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4215171565
Short name T22
Test name
Test status
Simulation time 2724177348 ps
CPU time 37.09 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:31:23 PM PDT 24
Peak memory 200508 kb
Host smart-acf4ceaf-30be-4b7a-95b8-9cfc1caabe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215171565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4215171565
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2389268043
Short name T415
Test name
Test status
Simulation time 1617353965 ps
CPU time 277.75 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:35:21 PM PDT 24
Peak memory 619924 kb
Host smart-e2c895e6-f674-4638-8739-f78c1aae7bcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2389268043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2389268043
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.849029867
Short name T279
Test name
Test status
Simulation time 69704321960 ps
CPU time 191.89 seconds
Started Aug 15 04:30:29 PM PDT 24
Finished Aug 15 04:33:41 PM PDT 24
Peak memory 200644 kb
Host smart-d9bafe3a-e2a9-4c5e-91b5-7b687b525c61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849029867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.849029867
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1102959863
Short name T15
Test name
Test status
Simulation time 46487450798 ps
CPU time 51.02 seconds
Started Aug 15 04:30:28 PM PDT 24
Finished Aug 15 04:31:19 PM PDT 24
Peak memory 200528 kb
Host smart-51475e84-d5db-4cb1-b1ce-307206daacdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102959863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1102959863
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.790231782
Short name T481
Test name
Test status
Simulation time 1200980306 ps
CPU time 13.11 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 200464 kb
Host smart-49e99642-eb93-429e-bbb7-1b20b7bcb155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790231782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.790231782
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1995597446
Short name T323
Test name
Test status
Simulation time 26317501232 ps
CPU time 671.98 seconds
Started Aug 15 04:30:32 PM PDT 24
Finished Aug 15 04:41:44 PM PDT 24
Peak memory 664380 kb
Host smart-fbe0fef8-0638-4d0c-a5ec-3d7c78952e4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995597446 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1995597446
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3273124560
Short name T107
Test name
Test status
Simulation time 12429296474 ps
CPU time 78.63 seconds
Started Aug 15 04:30:42 PM PDT 24
Finished Aug 15 04:32:01 PM PDT 24
Peak memory 200516 kb
Host smart-a26828f8-85f5-42aa-b892-98af65659337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273124560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3273124560
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1437029610
Short name T48
Test name
Test status
Simulation time 14584517 ps
CPU time 0.56 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:30:52 PM PDT 24
Peak memory 196168 kb
Host smart-5a3e41be-a342-4fdc-8351-2788c493a7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437029610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1437029610
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4153797198
Short name T304
Test name
Test status
Simulation time 3114412581 ps
CPU time 91.9 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:32:22 PM PDT 24
Peak memory 200588 kb
Host smart-da963185-c96d-4bba-995d-72744432a8d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153797198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4153797198
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3727157767
Short name T348
Test name
Test status
Simulation time 13739582491 ps
CPU time 45.97 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:47 PM PDT 24
Peak memory 200576 kb
Host smart-1d2e7e6b-9a9c-4876-a78b-8357ce7a37d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727157767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3727157767
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2666549383
Short name T358
Test name
Test status
Simulation time 21469427155 ps
CPU time 273.28 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:35:30 PM PDT 24
Peak memory 646964 kb
Host smart-70afe97a-a713-4577-9511-d0b1d43cd080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666549383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2666549383
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.879676876
Short name T85
Test name
Test status
Simulation time 5295256433 ps
CPU time 85.54 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:31:59 PM PDT 24
Peak memory 200492 kb
Host smart-117a1ef7-8037-42f1-b4f7-6e15efbe7f73
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879676876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.879676876
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3697079652
Short name T262
Test name
Test status
Simulation time 934795200 ps
CPU time 51.19 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:31:36 PM PDT 24
Peak memory 200448 kb
Host smart-2df683f1-3004-404d-8ee2-051dc002cccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697079652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3697079652
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.192965151
Short name T86
Test name
Test status
Simulation time 799782894 ps
CPU time 11.01 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:30:57 PM PDT 24
Peak memory 200548 kb
Host smart-a247ace1-4439-43e3-900f-3ab49c09e42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192965151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.192965151
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.429894037
Short name T507
Test name
Test status
Simulation time 11670689338 ps
CPU time 597.25 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:40:56 PM PDT 24
Peak memory 200532 kb
Host smart-db3a70d3-d5ec-4e06-a9a2-19093486e33b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429894037 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.429894037
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.460174176
Short name T75
Test name
Test status
Simulation time 5558314678 ps
CPU time 100.24 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:32:29 PM PDT 24
Peak memory 200520 kb
Host smart-eb70473f-dd30-437a-928a-67cce8cae9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460174176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.460174176
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3860867383
Short name T364
Test name
Test status
Simulation time 14694257 ps
CPU time 0.59 seconds
Started Aug 15 04:30:48 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 195484 kb
Host smart-8c63870c-0c29-40c0-a7ac-10cdafa50252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860867383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3860867383
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3705378134
Short name T350
Test name
Test status
Simulation time 2513236114 ps
CPU time 40.49 seconds
Started Aug 15 04:30:48 PM PDT 24
Finished Aug 15 04:31:29 PM PDT 24
Peak memory 200500 kb
Host smart-19c68f37-f9bd-41aa-9695-4e2b2cad9254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3705378134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3705378134
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1608296971
Short name T461
Test name
Test status
Simulation time 1002281489 ps
CPU time 26.81 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:31:28 PM PDT 24
Peak memory 200520 kb
Host smart-fdbfc5d7-c12b-416d-b945-c1763c51edf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608296971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1608296971
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.61007632
Short name T135
Test name
Test status
Simulation time 22461147895 ps
CPU time 542.27 seconds
Started Aug 15 04:30:51 PM PDT 24
Finished Aug 15 04:39:53 PM PDT 24
Peak memory 728980 kb
Host smart-88b2acec-4bb4-405e-a6f1-dcf758d1382f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=61007632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.61007632
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2650296540
Short name T411
Test name
Test status
Simulation time 9430828142 ps
CPU time 31.52 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 200504 kb
Host smart-9a17f7e0-9285-43dc-9bdd-38a07b0ad5b6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650296540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2650296540
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.903413496
Short name T471
Test name
Test status
Simulation time 17050277597 ps
CPU time 212.17 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:34:26 PM PDT 24
Peak memory 208732 kb
Host smart-1940f739-3996-43af-9c61-65160c2c0904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903413496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.903413496
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.433548269
Short name T37
Test name
Test status
Simulation time 942929989 ps
CPU time 15.19 seconds
Started Aug 15 04:30:46 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200472 kb
Host smart-d6d34891-9763-4648-916f-642d7aa94c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433548269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.433548269
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3693166934
Short name T361
Test name
Test status
Simulation time 659588026355 ps
CPU time 1936.74 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 05:03:16 PM PDT 24
Peak memory 741932 kb
Host smart-623bc3d5-309a-4eec-ae94-47f8cf1b3bd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693166934 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3693166934
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.145149423
Short name T254
Test name
Test status
Simulation time 14586226092 ps
CPU time 131.63 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:33:08 PM PDT 24
Peak memory 200528 kb
Host smart-27525e2a-2f02-4afd-8bca-606ee4323aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145149423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.145149423
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1361729998
Short name T438
Test name
Test status
Simulation time 10982214 ps
CPU time 0.56 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 196236 kb
Host smart-b74c14c4-32e2-4851-a6cf-49c525756a52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361729998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1361729998
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.167046355
Short name T98
Test name
Test status
Simulation time 444946084 ps
CPU time 24.59 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:31:12 PM PDT 24
Peak memory 200408 kb
Host smart-01221aab-dfb0-42c5-8b75-f50bc8e491ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167046355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.167046355
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1103004715
Short name T453
Test name
Test status
Simulation time 4038380519 ps
CPU time 51.23 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 200508 kb
Host smart-6d8af426-2c69-4314-9d44-74212c8d2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103004715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1103004715
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2298148733
Short name T172
Test name
Test status
Simulation time 6377067878 ps
CPU time 200.22 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:34:14 PM PDT 24
Peak memory 444872 kb
Host smart-e5bd8994-b85e-44d4-94a1-272989103f25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2298148733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2298148733
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2951701056
Short name T332
Test name
Test status
Simulation time 15848436224 ps
CPU time 214.58 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:34:27 PM PDT 24
Peak memory 200508 kb
Host smart-2bf12997-15b1-409c-8c16-2c6cd230fa4b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951701056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2951701056
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.190824852
Short name T260
Test name
Test status
Simulation time 3900798946 ps
CPU time 54.28 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:31:46 PM PDT 24
Peak memory 200476 kb
Host smart-df509bf8-5423-4c19-a17f-27d970d8828b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190824852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.190824852
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.453453257
Short name T240
Test name
Test status
Simulation time 309827585 ps
CPU time 14.85 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200460 kb
Host smart-3d2b3b02-ceaa-4d71-b843-fb8da5817109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453453257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.453453257
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3949478864
Short name T356
Test name
Test status
Simulation time 44946290256 ps
CPU time 1385.54 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:53:53 PM PDT 24
Peak memory 740104 kb
Host smart-a1bc0e23-cdc1-436a-b45f-910b572d3e60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949478864 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3949478864
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3454703626
Short name T286
Test name
Test status
Simulation time 7021355121 ps
CPU time 122.81 seconds
Started Aug 15 04:30:51 PM PDT 24
Finished Aug 15 04:32:53 PM PDT 24
Peak memory 200472 kb
Host smart-fc32b651-50be-4ae7-b401-54cb27bfe5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454703626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3454703626
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1157265512
Short name T523
Test name
Test status
Simulation time 37613622 ps
CPU time 0.57 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:30:55 PM PDT 24
Peak memory 196528 kb
Host smart-cefd7158-e655-4b1e-a30e-ac9f118b55db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157265512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1157265512
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3205804100
Short name T263
Test name
Test status
Simulation time 1524430048 ps
CPU time 74.58 seconds
Started Aug 15 04:30:53 PM PDT 24
Finished Aug 15 04:32:08 PM PDT 24
Peak memory 200480 kb
Host smart-78c82cba-fd80-464d-96ec-61e4541d3ada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205804100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3205804100
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.138819789
Short name T68
Test name
Test status
Simulation time 2282906942 ps
CPU time 40.04 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:31:30 PM PDT 24
Peak memory 200548 kb
Host smart-f28ed28c-d1d0-40e4-bdba-a331c625c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138819789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.138819789
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3266171004
Short name T289
Test name
Test status
Simulation time 3182456362 ps
CPU time 541.79 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:39:45 PM PDT 24
Peak memory 494740 kb
Host smart-d8897821-48f8-4115-88ba-65142cddf7f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3266171004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3266171004
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1339240802
Short name T74
Test name
Test status
Simulation time 22290279018 ps
CPU time 195.56 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:34:05 PM PDT 24
Peak memory 200500 kb
Host smart-b00cc522-8c25-41ca-bea7-1c3c507ed6c8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339240802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1339240802
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2723099668
Short name T210
Test name
Test status
Simulation time 5091231678 ps
CPU time 30.11 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:31:19 PM PDT 24
Peak memory 200380 kb
Host smart-827c4587-aaec-4a28-97e8-c432e6d5c334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723099668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2723099668
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2188653581
Short name T250
Test name
Test status
Simulation time 2615666113 ps
CPU time 8.18 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200508 kb
Host smart-44af07aa-d7b3-4940-b7b0-b988414c7ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188653581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2188653581
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3727227758
Short name T409
Test name
Test status
Simulation time 5081015263 ps
CPU time 76.17 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:32:13 PM PDT 24
Peak memory 200556 kb
Host smart-3403e1a5-ded5-44c7-9cee-791763f5f1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727227758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3727227758
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.783870181
Short name T194
Test name
Test status
Simulation time 63966835 ps
CPU time 0.59 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:30:48 PM PDT 24
Peak memory 197180 kb
Host smart-77d47813-3fe2-4300-8b1e-38da1cbd8af3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783870181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.783870181
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2467712221
Short name T472
Test name
Test status
Simulation time 1218575953 ps
CPU time 68.55 seconds
Started Aug 15 04:30:45 PM PDT 24
Finished Aug 15 04:31:54 PM PDT 24
Peak memory 200508 kb
Host smart-b2f3792b-9ecf-4644-89a3-07835ce734d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467712221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2467712221
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1418214037
Short name T303
Test name
Test status
Simulation time 1408156123 ps
CPU time 24.36 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:31:17 PM PDT 24
Peak memory 200524 kb
Host smart-8255fb25-9aa6-4d83-b2fc-cb35c5b0ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418214037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1418214037
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3035746974
Short name T423
Test name
Test status
Simulation time 8710373064 ps
CPU time 636.9 seconds
Started Aug 15 04:30:47 PM PDT 24
Finished Aug 15 04:41:24 PM PDT 24
Peak memory 702884 kb
Host smart-99ad0e33-2484-4ce9-8fdf-235c629879b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3035746974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3035746974
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2153510351
Short name T63
Test name
Test status
Simulation time 10936239447 ps
CPU time 186.62 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:34:09 PM PDT 24
Peak memory 200540 kb
Host smart-6ede0d91-2fb9-4339-abcc-87322c66173b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153510351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2153510351
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2685944659
Short name T338
Test name
Test status
Simulation time 1411803700 ps
CPU time 20.54 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:31:02 PM PDT 24
Peak memory 200832 kb
Host smart-ca2a4b01-0c93-4f7d-bb53-b90b66c6dac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685944659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2685944659
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2987868503
Short name T320
Test name
Test status
Simulation time 812839799 ps
CPU time 9.39 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:30:48 PM PDT 24
Peak memory 200464 kb
Host smart-23ff6ebd-eaed-4e5e-80b8-137f199d9fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987868503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2987868503
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1229569767
Short name T490
Test name
Test status
Simulation time 112859964576 ps
CPU time 467.08 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:38:37 PM PDT 24
Peak memory 200536 kb
Host smart-065cad8e-0db1-48ee-9cff-2a5e15641e26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229569767 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1229569767
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3342495610
Short name T441
Test name
Test status
Simulation time 8334272688 ps
CPU time 109.33 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 200476 kb
Host smart-78327e1d-a750-4dad-ba6d-9a5ccac10c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342495610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3342495610
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2342906116
Short name T298
Test name
Test status
Simulation time 41045312 ps
CPU time 0.61 seconds
Started Aug 15 04:31:07 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 196500 kb
Host smart-dc69b8da-99fe-46db-9c0b-ec70686ed6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342906116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2342906116
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3426181920
Short name T492
Test name
Test status
Simulation time 2151537363 ps
CPU time 60.97 seconds
Started Aug 15 04:30:43 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 200476 kb
Host smart-5e3e0164-abb3-43f8-98b8-d6f9411477c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426181920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3426181920
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1268260183
Short name T57
Test name
Test status
Simulation time 4908416517 ps
CPU time 22.27 seconds
Started Aug 15 04:31:15 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 200920 kb
Host smart-46b02715-d327-4b27-baf1-695a91aa4b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268260183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1268260183
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1044994043
Short name T429
Test name
Test status
Simulation time 7744534531 ps
CPU time 1579.23 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:57:11 PM PDT 24
Peak memory 771556 kb
Host smart-43583892-e163-407c-b061-fd3a6211cc04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1044994043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1044994043
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2677905551
Short name T230
Test name
Test status
Simulation time 1578991456 ps
CPU time 81.06 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:32:19 PM PDT 24
Peak memory 200408 kb
Host smart-21e53a1a-4143-46d4-b09d-53795b76e746
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677905551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2677905551
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1190420491
Short name T290
Test name
Test status
Simulation time 49483301635 ps
CPU time 128.22 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:33:05 PM PDT 24
Peak memory 200516 kb
Host smart-e5297282-ff5c-455e-89df-12d3578347ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190420491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1190420491
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2367979138
Short name T61
Test name
Test status
Simulation time 124107581 ps
CPU time 5.36 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 200552 kb
Host smart-0bb0b522-2a48-4cea-8301-3f05c0e32c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367979138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2367979138
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.4079202182
Short name T389
Test name
Test status
Simulation time 55463964411 ps
CPU time 246.97 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:35:09 PM PDT 24
Peak memory 200532 kb
Host smart-7f6f7f9e-f6dc-490f-8430-361a5c54770d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079202182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.4079202182
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2599696962
Short name T478
Test name
Test status
Simulation time 630391304 ps
CPU time 11.52 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:31:25 PM PDT 24
Peak memory 200456 kb
Host smart-e60a69e4-3c2a-4ce6-a292-c9193041f33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599696962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2599696962
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2724808588
Short name T251
Test name
Test status
Simulation time 18541843 ps
CPU time 0.59 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:30:50 PM PDT 24
Peak memory 196148 kb
Host smart-2659392e-0cc3-43d6-b095-2ea489467716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724808588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2724808588
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2434743644
Short name T369
Test name
Test status
Simulation time 2250299654 ps
CPU time 63.16 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:31:55 PM PDT 24
Peak memory 200520 kb
Host smart-3af46aa5-b777-4c46-97a3-75036a7106c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434743644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2434743644
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1931462450
Short name T504
Test name
Test status
Simulation time 1073693628 ps
CPU time 15.38 seconds
Started Aug 15 04:30:48 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200364 kb
Host smart-b48b3f44-af51-4e05-91fe-8211cdb15745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931462450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1931462450
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3423343289
Short name T296
Test name
Test status
Simulation time 2579536176 ps
CPU time 95.24 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:32:37 PM PDT 24
Peak memory 360316 kb
Host smart-4a4c21dc-c072-4dc4-b9b8-0c244b4eddbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423343289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3423343289
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3471726223
Short name T494
Test name
Test status
Simulation time 5243528912 ps
CPU time 45.4 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:31:41 PM PDT 24
Peak memory 200668 kb
Host smart-8cb84217-e4c6-4661-819d-45241ca19967
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471726223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3471726223
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.79401040
Short name T312
Test name
Test status
Simulation time 1276135067 ps
CPU time 16.53 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:31:11 PM PDT 24
Peak memory 200424 kb
Host smart-86037fdc-1be8-46a5-a06f-62f95dde34b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79401040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.79401040
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.30083630
Short name T335
Test name
Test status
Simulation time 2197745272 ps
CPU time 6.82 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200220 kb
Host smart-f0f2d7d2-68b1-4851-8012-07187b78b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30083630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.30083630
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1001524992
Short name T76
Test name
Test status
Simulation time 1254568774829 ps
CPU time 4606.84 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 05:47:46 PM PDT 24
Peak memory 813348 kb
Host smart-f2fa7d09-c243-4764-9cd3-0e1db6a7da15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001524992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1001524992
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1782402604
Short name T363
Test name
Test status
Simulation time 24879610585 ps
CPU time 28.85 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:31:24 PM PDT 24
Peak memory 200552 kb
Host smart-985e183d-5051-413e-90a7-b3a2bea69012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782402604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1782402604
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1989133867
Short name T33
Test name
Test status
Simulation time 15390690 ps
CPU time 0.57 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:30:28 PM PDT 24
Peak memory 196140 kb
Host smart-3ac85727-3ac1-435b-ae3e-8f81af077131
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989133867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1989133867
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2160212700
Short name T45
Test name
Test status
Simulation time 732479958 ps
CPU time 20.48 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:36 PM PDT 24
Peak memory 200412 kb
Host smart-b516e86b-d85c-41f4-af50-554aaf815eea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2160212700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2160212700
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2730266250
Short name T435
Test name
Test status
Simulation time 5175975083 ps
CPU time 46.14 seconds
Started Aug 15 04:30:13 PM PDT 24
Finished Aug 15 04:30:59 PM PDT 24
Peak memory 200488 kb
Host smart-77a1e202-1e01-4d08-8158-ff3bc37e48af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730266250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2730266250
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1844397058
Short name T30
Test name
Test status
Simulation time 16500461246 ps
CPU time 791.83 seconds
Started Aug 15 04:30:04 PM PDT 24
Finished Aug 15 04:43:17 PM PDT 24
Peak memory 741908 kb
Host smart-317b1396-a4f0-42fa-96d1-5f1a7c1f34da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844397058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1844397058
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2291416505
Short name T519
Test name
Test status
Simulation time 22983583849 ps
CPU time 135.81 seconds
Started Aug 15 04:30:38 PM PDT 24
Finished Aug 15 04:32:54 PM PDT 24
Peak memory 200532 kb
Host smart-55b1600b-b899-4816-945b-17b6005bbb20
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291416505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2291416505
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3646814603
Short name T379
Test name
Test status
Simulation time 5792068612 ps
CPU time 35.98 seconds
Started Aug 15 04:30:01 PM PDT 24
Finished Aug 15 04:30:37 PM PDT 24
Peak memory 200544 kb
Host smart-c073c5fd-c16f-4088-ae86-5c90558506ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646814603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3646814603
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1857048303
Short name T54
Test name
Test status
Simulation time 238437481 ps
CPU time 0.79 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 218356 kb
Host smart-bea2ec2d-4c97-4811-a691-9cca6c046f18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857048303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1857048303
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3491950799
Short name T105
Test name
Test status
Simulation time 10171377210 ps
CPU time 810.33 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:43:39 PM PDT 24
Peak memory 689732 kb
Host smart-2aee1cc8-61bc-475f-84a3-52af97f012ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491950799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3491950799
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.4201578915
Short name T6
Test name
Test status
Simulation time 14255527215 ps
CPU time 231.25 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:34:10 PM PDT 24
Peak memory 479088 kb
Host smart-9349848b-8a94-4629-8a33-3154810961da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4201578915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.4201578915
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2708573863
Short name T218
Test name
Test status
Simulation time 4480303005 ps
CPU time 51.59 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200488 kb
Host smart-3f6e606d-b2fa-4c28-a3fd-bb884fde7e21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2708573863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2708573863
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1111788126
Short name T170
Test name
Test status
Simulation time 7657053109 ps
CPU time 59.3 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:31:05 PM PDT 24
Peak memory 200392 kb
Host smart-76527032-44c1-4cfb-9b99-84970fce308c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1111788126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1111788126
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3465064465
Short name T373
Test name
Test status
Simulation time 22120197423 ps
CPU time 132.55 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 200492 kb
Host smart-265a6fb9-4a36-43f1-a6ba-00c9d70f2288
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3465064465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3465064465
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.490960230
Short name T464
Test name
Test status
Simulation time 10688899655 ps
CPU time 602.92 seconds
Started Aug 15 04:29:57 PM PDT 24
Finished Aug 15 04:40:00 PM PDT 24
Peak memory 200552 kb
Host smart-0c6d5462-83b8-4681-9690-69af07108964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=490960230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.490960230
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3707949443
Short name T287
Test name
Test status
Simulation time 919438932132 ps
CPU time 2536.32 seconds
Started Aug 15 04:30:11 PM PDT 24
Finished Aug 15 05:12:27 PM PDT 24
Peak memory 216388 kb
Host smart-97c6c170-e44a-4af1-ae09-1df8f3739f7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3707949443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3707949443
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2162070835
Short name T449
Test name
Test status
Simulation time 268813415177 ps
CPU time 2206.67 seconds
Started Aug 15 04:29:59 PM PDT 24
Finished Aug 15 05:06:46 PM PDT 24
Peak memory 216028 kb
Host smart-f8fbc035-32bc-4e89-a1a2-1967c40e2341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2162070835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2162070835
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2070489863
Short name T383
Test name
Test status
Simulation time 52347069363 ps
CPU time 105.53 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:32:02 PM PDT 24
Peak memory 200512 kb
Host smart-9e9f2ae2-3e13-42e3-be31-5b9cc8bdc10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070489863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2070489863
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.3298669385
Short name T58
Test name
Test status
Simulation time 16886055 ps
CPU time 0.61 seconds
Started Aug 15 04:30:44 PM PDT 24
Finished Aug 15 04:30:45 PM PDT 24
Peak memory 196620 kb
Host smart-b46e7721-6ffb-424d-9709-47e96cff65f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298669385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3298669385
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.985784733
Short name T313
Test name
Test status
Simulation time 461744479 ps
CPU time 26.55 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:31:19 PM PDT 24
Peak memory 200464 kb
Host smart-f3a2f2e3-fe53-4695-9589-0592394cdaf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=985784733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.985784733
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3631050220
Short name T91
Test name
Test status
Simulation time 3480580070 ps
CPU time 30.53 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:31:26 PM PDT 24
Peak memory 200532 kb
Host smart-a156d1e8-b54c-46d6-8ba1-8862a4850f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631050220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3631050220
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.4278492387
Short name T188
Test name
Test status
Simulation time 318910277 ps
CPU time 48.92 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:32:02 PM PDT 24
Peak memory 322488 kb
Host smart-cf5808de-da3d-4049-a437-c1776856c14e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278492387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.4278492387
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4198375513
Short name T191
Test name
Test status
Simulation time 44226075170 ps
CPU time 142.56 seconds
Started Aug 15 04:30:53 PM PDT 24
Finished Aug 15 04:33:16 PM PDT 24
Peak memory 200484 kb
Host smart-8b04626c-d63c-4648-8ba8-1572e6b5b3d4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198375513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4198375513
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3211505908
Short name T247
Test name
Test status
Simulation time 4826364294 ps
CPU time 101.23 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:32:33 PM PDT 24
Peak memory 200460 kb
Host smart-98fed409-ca0f-41ff-aa15-bc00bc8ff93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211505908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3211505908
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1726129506
Short name T62
Test name
Test status
Simulation time 242917970 ps
CPU time 11.46 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 200488 kb
Host smart-277edfcc-fe35-4fb4-9c4b-247652dce735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726129506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1726129506
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.268866575
Short name T496
Test name
Test status
Simulation time 5221513775 ps
CPU time 366.57 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:36:59 PM PDT 24
Peak memory 441532 kb
Host smart-4212f5c6-afa0-4f4d-9ae0-f5fe970a0e3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268866575 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.268866575
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2009995061
Short name T345
Test name
Test status
Simulation time 5361906480 ps
CPU time 68.68 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:32:03 PM PDT 24
Peak memory 200580 kb
Host smart-4a85252a-bcbc-4408-87d0-7cf6d4476ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009995061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2009995061
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.78392304
Short name T83
Test name
Test status
Simulation time 21631155 ps
CPU time 0.6 seconds
Started Aug 15 04:30:49 PM PDT 24
Finished Aug 15 04:30:50 PM PDT 24
Peak memory 195536 kb
Host smart-343c0f4c-38da-46de-8505-1f0d3f01b72c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78392304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.78392304
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.646892791
Short name T35
Test name
Test status
Simulation time 923672577 ps
CPU time 8.87 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:20 PM PDT 24
Peak memory 200436 kb
Host smart-04d2979a-b33b-4ed4-a21d-690971f669ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646892791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.646892791
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2190328145
Short name T506
Test name
Test status
Simulation time 16797074502 ps
CPU time 830.73 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:44:56 PM PDT 24
Peak memory 738316 kb
Host smart-88ce3833-8ce8-4e87-855f-43195c63d689
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190328145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2190328145
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.804438713
Short name T311
Test name
Test status
Simulation time 5423927469 ps
CPU time 137.55 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:33:09 PM PDT 24
Peak memory 200460 kb
Host smart-805584ba-795b-4da1-8fa8-14e3500dbea5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804438713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.804438713
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.639876380
Short name T244
Test name
Test status
Simulation time 51707811079 ps
CPU time 68.84 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 200636 kb
Host smart-d74290c4-3a17-4b74-8083-09028eeb0cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639876380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.639876380
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2167145304
Short name T370
Test name
Test status
Simulation time 133363836 ps
CPU time 6.03 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:31:03 PM PDT 24
Peak memory 200532 kb
Host smart-7ab2f0bf-6810-4fdc-9087-0d709864b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167145304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2167145304
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3587554115
Short name T156
Test name
Test status
Simulation time 25524410780 ps
CPU time 1643.37 seconds
Started Aug 15 04:31:07 PM PDT 24
Finished Aug 15 04:58:31 PM PDT 24
Peak memory 725904 kb
Host smart-5ab55e0e-7408-4e45-bea1-96b436248eb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587554115 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3587554115
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2771981237
Short name T139
Test name
Test status
Simulation time 2269117802 ps
CPU time 105.28 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:32:39 PM PDT 24
Peak memory 200484 kb
Host smart-cbb3b4d3-f1ee-4104-9fa8-01c59eca84fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771981237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2771981237
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1321318656
Short name T201
Test name
Test status
Simulation time 11776906 ps
CPU time 0.59 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:30:54 PM PDT 24
Peak memory 195496 kb
Host smart-d781ab59-2ae1-4f81-9ce8-e39a6d02811a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321318656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1321318656
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1204614626
Short name T202
Test name
Test status
Simulation time 4155733137 ps
CPU time 58.63 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:00 PM PDT 24
Peak memory 200844 kb
Host smart-aee7ffc0-b1f0-4744-94bf-87f37f9c56be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204614626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1204614626
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1923559418
Short name T468
Test name
Test status
Simulation time 1254712367 ps
CPU time 10.7 seconds
Started Aug 15 04:31:11 PM PDT 24
Finished Aug 15 04:31:22 PM PDT 24
Peak memory 200428 kb
Host smart-9a75c30d-4f93-4870-a8ac-b8b5e0c6afd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923559418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1923559418
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2450620582
Short name T517
Test name
Test status
Simulation time 13949998340 ps
CPU time 764.29 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:43:50 PM PDT 24
Peak memory 755984 kb
Host smart-6a7f82e4-e658-4b7c-98f9-5e5e5d80397c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2450620582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2450620582
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2394044452
Short name T339
Test name
Test status
Simulation time 2838255233 ps
CPU time 158.03 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:33:35 PM PDT 24
Peak memory 200580 kb
Host smart-a507ff23-a006-4b90-b3c7-6ba105fda24e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394044452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2394044452
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3277883506
Short name T160
Test name
Test status
Simulation time 10333153681 ps
CPU time 183.56 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:34:04 PM PDT 24
Peak memory 200528 kb
Host smart-8a4f96f0-d46f-4450-bbe7-a7e38ff7aceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277883506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3277883506
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3597083436
Short name T255
Test name
Test status
Simulation time 2429232325 ps
CPU time 10.07 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:31:06 PM PDT 24
Peak memory 200500 kb
Host smart-15ea019b-4064-49bb-96ad-c61797b3fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597083436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3597083436
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2242934411
Short name T78
Test name
Test status
Simulation time 114585429803 ps
CPU time 882.89 seconds
Started Aug 15 04:30:50 PM PDT 24
Finished Aug 15 04:45:33 PM PDT 24
Peak memory 617780 kb
Host smart-536bf499-b503-487b-903b-f2c8d3d6e6f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242934411 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2242934411
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.443709595
Short name T297
Test name
Test status
Simulation time 524270957 ps
CPU time 7.35 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:31:03 PM PDT 24
Peak memory 200404 kb
Host smart-c1af5814-8484-4539-9bb9-83fcf26c82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443709595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.443709595
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1572196888
Short name T479
Test name
Test status
Simulation time 35389811 ps
CPU time 0.58 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:30:58 PM PDT 24
Peak memory 196356 kb
Host smart-c1b33b5b-60c9-4e23-8937-5b71f7eb62a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572196888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1572196888
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1778692007
Short name T24
Test name
Test status
Simulation time 2134821077 ps
CPU time 55.89 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:31:50 PM PDT 24
Peak memory 200436 kb
Host smart-031f9179-eefd-484e-ae65-ae67dc950a23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778692007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1778692007
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3374725496
Short name T406
Test name
Test status
Simulation time 3239028934 ps
CPU time 41.18 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:31:45 PM PDT 24
Peak memory 200524 kb
Host smart-a5c36dbb-9710-40c9-8169-d06761103572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374725496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3374725496
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2127269239
Short name T224
Test name
Test status
Simulation time 3945129144 ps
CPU time 721.68 seconds
Started Aug 15 04:30:51 PM PDT 24
Finished Aug 15 04:42:53 PM PDT 24
Peak memory 748624 kb
Host smart-285464a5-522a-4c75-9eb3-0b6ec518bb80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2127269239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2127269239
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1153041504
Short name T451
Test name
Test status
Simulation time 497637559 ps
CPU time 9.3 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 200344 kb
Host smart-64dca443-5ef9-42d6-916c-ecf5680342e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153041504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1153041504
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3520869819
Short name T445
Test name
Test status
Simulation time 1492958289 ps
CPU time 67.87 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:32:07 PM PDT 24
Peak memory 200396 kb
Host smart-189c1b87-098c-4849-b6b2-21de5a58459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520869819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3520869819
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.106182399
Short name T176
Test name
Test status
Simulation time 33051247 ps
CPU time 1.58 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 200316 kb
Host smart-9a93caad-abbc-410c-8255-f3deee2aae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106182399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.106182399
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2751013333
Short name T484
Test name
Test status
Simulation time 37066530787 ps
CPU time 544.1 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:40:04 PM PDT 24
Peak memory 208708 kb
Host smart-bb11fa1b-b5b3-4a9c-b090-6508c25d3494
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751013333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2751013333
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1377763988
Short name T405
Test name
Test status
Simulation time 5025816715 ps
CPU time 100.83 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:32:41 PM PDT 24
Peak memory 200520 kb
Host smart-f904f334-4b04-4ca1-89a7-d0ff7ee7938b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377763988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1377763988
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3899373617
Short name T273
Test name
Test status
Simulation time 18427982 ps
CPU time 0.59 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:30:59 PM PDT 24
Peak memory 196124 kb
Host smart-5e7af477-cafb-4bf1-9c18-5db24bd95477
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899373617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3899373617
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3259988401
Short name T355
Test name
Test status
Simulation time 2738107279 ps
CPU time 64.08 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:05 PM PDT 24
Peak memory 200488 kb
Host smart-316b9f17-7807-43ac-bb42-01af15bc7950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259988401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3259988401
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4185308988
Short name T186
Test name
Test status
Simulation time 7555405305 ps
CPU time 33.28 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:34 PM PDT 24
Peak memory 200440 kb
Host smart-df43d9d6-aa27-45cd-80e3-9159197eda12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185308988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4185308988
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3103779885
Short name T259
Test name
Test status
Simulation time 16537698721 ps
CPU time 1736.92 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:59:56 PM PDT 24
Peak memory 771720 kb
Host smart-c8a8d631-fa84-4dbe-b534-bf0f72205d98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3103779885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3103779885
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.474616340
Short name T174
Test name
Test status
Simulation time 2579473367 ps
CPU time 130.5 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:33:07 PM PDT 24
Peak memory 200504 kb
Host smart-8b461998-e451-46d5-8d84-131af3ac402e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474616340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.474616340
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1037914367
Short name T305
Test name
Test status
Simulation time 4332939380 ps
CPU time 72.77 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 200512 kb
Host smart-7d4f17bf-d080-4e70-ad1d-bf4bcb21372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037914367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1037914367
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.411149637
Short name T42
Test name
Test status
Simulation time 214066572 ps
CPU time 2.48 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:31:09 PM PDT 24
Peak memory 200504 kb
Host smart-c9fc2179-e21f-48c5-b52f-3eaa7c0a0a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411149637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.411149637
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2690070434
Short name T390
Test name
Test status
Simulation time 142460556418 ps
CPU time 4428.62 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 05:44:45 PM PDT 24
Peak memory 844040 kb
Host smart-474a49a2-66c6-4072-a3c3-3eafda562f35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690070434 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2690070434
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2600827855
Short name T103
Test name
Test status
Simulation time 13571515624 ps
CPU time 118.57 seconds
Started Aug 15 04:30:52 PM PDT 24
Finished Aug 15 04:32:51 PM PDT 24
Peak memory 200512 kb
Host smart-7e7ee8c4-bf7e-412d-8bf6-112a69397a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600827855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2600827855
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2264910957
Short name T256
Test name
Test status
Simulation time 139749406 ps
CPU time 0.63 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 196528 kb
Host smart-881db63a-052d-4f00-aba4-2a7ba7600ed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264910957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2264910957
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2753527581
Short name T452
Test name
Test status
Simulation time 1074146682 ps
CPU time 62.71 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 200492 kb
Host smart-64792ae6-d29f-44ee-bdbb-1a8a16f2d79a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2753527581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2753527581
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.53053041
Short name T199
Test name
Test status
Simulation time 2145290516 ps
CPU time 7.64 seconds
Started Aug 15 04:30:54 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200424 kb
Host smart-c765b880-f4d0-4f9d-aaef-3fae39c9b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53053041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.53053041
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1875215247
Short name T270
Test name
Test status
Simulation time 6816932427 ps
CPU time 1339.43 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:53:18 PM PDT 24
Peak memory 755272 kb
Host smart-d838dfae-6cbb-4551-9fe0-7c078e7c299a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1875215247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1875215247
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3085847083
Short name T17
Test name
Test status
Simulation time 5000322420 ps
CPU time 65.5 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:32:04 PM PDT 24
Peak memory 200584 kb
Host smart-420e2670-33bb-4a50-aed7-ef2caca8a478
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085847083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3085847083
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.179379620
Short name T178
Test name
Test status
Simulation time 41245294263 ps
CPU time 140.82 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:33:23 PM PDT 24
Peak memory 200608 kb
Host smart-8d7da71d-40f8-4698-9c6e-713c622d31cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179379620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.179379620
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4152109154
Short name T157
Test name
Test status
Simulation time 464685430 ps
CPU time 8.52 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 200516 kb
Host smart-a1fe4eae-633c-494e-ae27-9628aaa25ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152109154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4152109154
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2374730937
Short name T359
Test name
Test status
Simulation time 16361910896 ps
CPU time 163.6 seconds
Started Aug 15 04:31:08 PM PDT 24
Finished Aug 15 04:33:52 PM PDT 24
Peak memory 208844 kb
Host smart-e557dd1e-07f0-44b4-a3b9-793253ae383b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374730937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2374730937
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2564406869
Short name T59
Test name
Test status
Simulation time 1431908419 ps
CPU time 72.69 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 200460 kb
Host smart-f889fdca-5c1c-444b-94b4-689f1a15daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564406869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2564406869
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2313774619
Short name T497
Test name
Test status
Simulation time 14654576 ps
CPU time 0.62 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 195504 kb
Host smart-53638a7b-99be-438c-b3c3-17cf08a36bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313774619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2313774619
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3928239135
Short name T198
Test name
Test status
Simulation time 2453636357 ps
CPU time 51.64 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:31:52 PM PDT 24
Peak memory 200500 kb
Host smart-1f007968-8535-4175-a96a-4c1990aa6774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928239135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3928239135
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1088840660
Short name T514
Test name
Test status
Simulation time 727584603 ps
CPU time 38.82 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 200484 kb
Host smart-320b2de4-f6c5-4ab0-9516-3965b5aca331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088840660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1088840660
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3247866740
Short name T502
Test name
Test status
Simulation time 48971950484 ps
CPU time 574.46 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:40:40 PM PDT 24
Peak memory 512020 kb
Host smart-47a799a6-7c0d-4972-a972-28f0b425498c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247866740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3247866740
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.640238538
Short name T233
Test name
Test status
Simulation time 256971091 ps
CPU time 14.03 seconds
Started Aug 15 04:30:53 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 200384 kb
Host smart-3081ece7-61d0-4d59-a311-4f095e3f3efc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640238538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.640238538
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1835974992
Short name T234
Test name
Test status
Simulation time 742939292 ps
CPU time 40.06 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 200444 kb
Host smart-4ff4f260-6675-4426-bdda-e5014384f2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835974992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1835974992
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2379369106
Short name T420
Test name
Test status
Simulation time 50452521 ps
CPU time 0.96 seconds
Started Aug 15 04:31:00 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 199620 kb
Host smart-62b2f103-7b54-409c-8208-d71e87107cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379369106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2379369106
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.732950778
Short name T80
Test name
Test status
Simulation time 34029436785 ps
CPU time 456.42 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:38:40 PM PDT 24
Peak memory 208744 kb
Host smart-4b58ef7a-da20-46c9-8bb2-5b2f821c3cf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732950778 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.732950778
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1676814940
Short name T349
Test name
Test status
Simulation time 1252970663 ps
CPU time 60.35 seconds
Started Aug 15 04:30:56 PM PDT 24
Finished Aug 15 04:31:57 PM PDT 24
Peak memory 200452 kb
Host smart-ddae876f-5e8e-4385-8e6f-7cf8bdde9adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676814940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1676814940
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2682902744
Short name T489
Test name
Test status
Simulation time 14085556 ps
CPU time 0.57 seconds
Started Aug 15 04:31:09 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 195512 kb
Host smart-481f889f-adc2-455f-9d6c-89918880a60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682902744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2682902744
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4015277569
Short name T419
Test name
Test status
Simulation time 5202641574 ps
CPU time 67.52 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:32:12 PM PDT 24
Peak memory 200472 kb
Host smart-bc2f3171-8788-42e9-9d4f-4808c72f4110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015277569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4015277569
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4267138109
Short name T96
Test name
Test status
Simulation time 1544713550 ps
CPU time 35.73 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:40 PM PDT 24
Peak memory 200496 kb
Host smart-ce606556-5b36-427a-80d9-4114dbfd07dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267138109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4267138109
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3267227017
Short name T424
Test name
Test status
Simulation time 17199740705 ps
CPU time 781.95 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:43:59 PM PDT 24
Peak memory 753376 kb
Host smart-fbafe747-647f-4e31-8857-7e0a90d1cb4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267227017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3267227017
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.958547400
Short name T316
Test name
Test status
Simulation time 8292408510 ps
CPU time 110.59 seconds
Started Aug 15 04:31:01 PM PDT 24
Finished Aug 15 04:32:52 PM PDT 24
Peak memory 200460 kb
Host smart-bb484f30-3f26-4101-b812-253b4f56e0e7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958547400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.958547400
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1355422043
Short name T3
Test name
Test status
Simulation time 10432535876 ps
CPU time 124.58 seconds
Started Aug 15 04:30:57 PM PDT 24
Finished Aug 15 04:33:02 PM PDT 24
Peak memory 216920 kb
Host smart-0f137401-8eef-46fb-baa1-d9419a061462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355422043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1355422043
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2999511046
Short name T87
Test name
Test status
Simulation time 126509402 ps
CPU time 2.31 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 200508 kb
Host smart-b8dd5e78-4e6c-4b39-8c49-3b80baa664ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999511046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2999511046
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2615625415
Short name T81
Test name
Test status
Simulation time 200759778030 ps
CPU time 1408.75 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:54:34 PM PDT 24
Peak memory 713304 kb
Host smart-5f57bb89-2535-4b80-9032-eaabbe80f3ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615625415 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2615625415
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4183241116
Short name T400
Test name
Test status
Simulation time 4900857884 ps
CPU time 95.56 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:32:40 PM PDT 24
Peak memory 200568 kb
Host smart-14d110dc-d87a-4591-80ab-59a1d815944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183241116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4183241116
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2898278839
Short name T483
Test name
Test status
Simulation time 35771856 ps
CPU time 0.58 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:30:59 PM PDT 24
Peak memory 195492 kb
Host smart-0d1dbfc1-799e-43b1-b0ec-1da6ea36d30b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898278839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2898278839
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2955179601
Short name T225
Test name
Test status
Simulation time 3300752814 ps
CPU time 92.36 seconds
Started Aug 15 04:31:06 PM PDT 24
Finished Aug 15 04:32:39 PM PDT 24
Peak memory 200280 kb
Host smart-624eaa8f-a236-4665-b7c2-f105dc0e5e25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955179601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2955179601
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3182052508
Short name T368
Test name
Test status
Simulation time 3640419965 ps
CPU time 46.09 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:31:44 PM PDT 24
Peak memory 216716 kb
Host smart-76d358f6-6882-4f5b-8398-c8977acffa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182052508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3182052508
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.321406422
Short name T377
Test name
Test status
Simulation time 9091579637 ps
CPU time 351.61 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:36:53 PM PDT 24
Peak memory 634900 kb
Host smart-6c85e25e-7199-4801-b0bf-c7f9d8ddf4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321406422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.321406422
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3652480465
Short name T301
Test name
Test status
Simulation time 35199572023 ps
CPU time 155.89 seconds
Started Aug 15 04:31:03 PM PDT 24
Finished Aug 15 04:33:39 PM PDT 24
Peak memory 199108 kb
Host smart-9ec2a020-233a-4f4d-b829-5b0b327591f4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652480465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3652480465
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_smoke.2128654132
Short name T294
Test name
Test status
Simulation time 12200650245 ps
CPU time 11.85 seconds
Started Aug 15 04:31:02 PM PDT 24
Finished Aug 15 04:31:14 PM PDT 24
Peak memory 200504 kb
Host smart-19114bcd-6105-4f13-a8f6-fbcc7ff7b5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128654132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2128654132
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.760805108
Short name T29
Test name
Test status
Simulation time 31385915554 ps
CPU time 106.88 seconds
Started Aug 15 04:31:08 PM PDT 24
Finished Aug 15 04:32:55 PM PDT 24
Peak memory 200616 kb
Host smart-75749064-f3b0-4582-9f94-4df20e86fc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760805108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.760805108
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.571562530
Short name T503
Test name
Test status
Simulation time 17741573 ps
CPU time 0.6 seconds
Started Aug 15 04:31:08 PM PDT 24
Finished Aug 15 04:31:08 PM PDT 24
Peak memory 196120 kb
Host smart-5f1235fe-6375-4646-8fcb-4997ff9ce60f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571562530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.571562530
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.966122289
Short name T518
Test name
Test status
Simulation time 2917590222 ps
CPU time 41.75 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:31:37 PM PDT 24
Peak memory 200516 kb
Host smart-e40a44c0-e9b4-45c9-a3c0-772d1a9ce6c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966122289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.966122289
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4273256801
Short name T446
Test name
Test status
Simulation time 475810468 ps
CPU time 6.5 seconds
Started Aug 15 04:31:04 PM PDT 24
Finished Aug 15 04:31:10 PM PDT 24
Peak memory 199008 kb
Host smart-85e886fa-5406-481c-a753-bf3bb46c164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273256801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4273256801
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.508157281
Short name T413
Test name
Test status
Simulation time 2219256562 ps
CPU time 346.01 seconds
Started Aug 15 04:30:55 PM PDT 24
Finished Aug 15 04:36:41 PM PDT 24
Peak memory 664748 kb
Host smart-ff2bbf60-9576-45d3-a59a-6886bf460c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508157281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.508157281
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3436043386
Short name T528
Test name
Test status
Simulation time 12322856843 ps
CPU time 212.89 seconds
Started Aug 15 04:31:08 PM PDT 24
Finished Aug 15 04:34:41 PM PDT 24
Peak memory 200484 kb
Host smart-48caf9ef-8a97-499c-922a-39c360c7d12e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436043386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3436043386
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3980420819
Short name T498
Test name
Test status
Simulation time 28019795711 ps
CPU time 101.98 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:32:47 PM PDT 24
Peak memory 200556 kb
Host smart-dce0022b-8f7e-4f2c-8d1f-d6c1d5200bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980420819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3980420819
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3986961461
Short name T20
Test name
Test status
Simulation time 511679031 ps
CPU time 8.48 seconds
Started Aug 15 04:30:59 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 200576 kb
Host smart-e0289d83-2262-419a-9ce1-1dbdbc29c583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986961461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3986961461
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1957658607
Short name T36
Test name
Test status
Simulation time 60565840481 ps
CPU time 572.76 seconds
Started Aug 15 04:31:07 PM PDT 24
Finished Aug 15 04:40:40 PM PDT 24
Peak memory 659824 kb
Host smart-b3eb4157-1f31-44c4-9ceb-5979e59cc146
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957658607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1957658607
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1602958933
Short name T232
Test name
Test status
Simulation time 35020184834 ps
CPU time 110.96 seconds
Started Aug 15 04:31:05 PM PDT 24
Finished Aug 15 04:32:56 PM PDT 24
Peak memory 200520 kb
Host smart-a16335d7-5f91-4ebf-82f9-ab2d9e3e04b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602958933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1602958933
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1907241775
Short name T38
Test name
Test status
Simulation time 49591562 ps
CPU time 0.6 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:30:10 PM PDT 24
Peak memory 197188 kb
Host smart-772e17d2-e97e-4248-a2fb-87532b4bdbdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907241775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1907241775
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1184714988
Short name T391
Test name
Test status
Simulation time 796739951 ps
CPU time 46.06 seconds
Started Aug 15 04:30:58 PM PDT 24
Finished Aug 15 04:31:45 PM PDT 24
Peak memory 198232 kb
Host smart-969e9734-f8d8-40b7-85d8-ec2cf1b89af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1184714988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1184714988
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4135442292
Short name T163
Test name
Test status
Simulation time 1929130348 ps
CPU time 81.27 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:31:38 PM PDT 24
Peak memory 200456 kb
Host smart-a7224ed3-f5a1-44f6-b21e-6b332290a566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135442292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4135442292
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1641180940
Short name T455
Test name
Test status
Simulation time 445527656 ps
CPU time 86.67 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:31:42 PM PDT 24
Peak memory 444164 kb
Host smart-7e20e4c6-b8bf-44c4-ba35-8c9d2b9387cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641180940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1641180940
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.45849647
Short name T457
Test name
Test status
Simulation time 31818603765 ps
CPU time 105.78 seconds
Started Aug 15 04:30:12 PM PDT 24
Finished Aug 15 04:31:58 PM PDT 24
Peak memory 200504 kb
Host smart-35706c6a-3582-4b11-9c4a-f375ce67f653
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45849647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.45849647
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2031866508
Short name T274
Test name
Test status
Simulation time 1129553848 ps
CPU time 59.85 seconds
Started Aug 15 04:30:02 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200456 kb
Host smart-64156f6c-ac6c-441b-a209-aa2e60b05049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031866508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2031866508
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.809632392
Short name T467
Test name
Test status
Simulation time 313940578 ps
CPU time 13.45 seconds
Started Aug 15 04:30:27 PM PDT 24
Finished Aug 15 04:30:41 PM PDT 24
Peak memory 200448 kb
Host smart-d828d1c7-d034-45d9-b906-8333bb86d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809632392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.809632392
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1027690658
Short name T142
Test name
Test status
Simulation time 77997234231 ps
CPU time 166.75 seconds
Started Aug 15 04:31:13 PM PDT 24
Finished Aug 15 04:34:00 PM PDT 24
Peak memory 200272 kb
Host smart-9c2b199b-86a0-435f-9c67-c3f78a8230d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027690658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1027690658
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2052209120
Short name T277
Test name
Test status
Simulation time 2797121909 ps
CPU time 112.39 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:32:11 PM PDT 24
Peak memory 200524 kb
Host smart-e4027c78-e5c0-4dc1-9389-ba4f4fd5cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052209120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2052209120
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3268514391
Short name T430
Test name
Test status
Simulation time 15520161 ps
CPU time 0.6 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:30:20 PM PDT 24
Peak memory 196564 kb
Host smart-3043be28-e719-4e6c-bb2a-31217f24c741
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268514391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3268514391
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1507981853
Short name T404
Test name
Test status
Simulation time 1057236631 ps
CPU time 57.73 seconds
Started Aug 15 04:30:06 PM PDT 24
Finished Aug 15 04:31:04 PM PDT 24
Peak memory 200296 kb
Host smart-8e7c3407-b5fd-41c5-add0-e4e5fa1e4162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507981853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1507981853
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3911145728
Short name T137
Test name
Test status
Simulation time 2774675473 ps
CPU time 35.27 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:30:45 PM PDT 24
Peak memory 200624 kb
Host smart-008f7ba3-fa42-4868-9d6c-b6a1ea12d278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911145728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3911145728
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3983921640
Short name T217
Test name
Test status
Simulation time 2003766722 ps
CPU time 92.91 seconds
Started Aug 15 04:30:41 PM PDT 24
Finished Aug 15 04:32:14 PM PDT 24
Peak memory 430520 kb
Host smart-6d39e3ab-bd4d-496e-a260-2af68eb7b1a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983921640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3983921640
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2027571831
Short name T221
Test name
Test status
Simulation time 49430124600 ps
CPU time 165.64 seconds
Started Aug 15 04:30:20 PM PDT 24
Finished Aug 15 04:33:06 PM PDT 24
Peak memory 200484 kb
Host smart-4270a73c-79d1-4c18-8ac4-fe5d3c0dda64
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027571831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2027571831
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4193815030
Short name T185
Test name
Test status
Simulation time 324607133 ps
CPU time 18.3 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:34 PM PDT 24
Peak memory 200444 kb
Host smart-7fb2ab93-a6a7-4bed-8b1b-28ab83b0478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193815030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4193815030
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4283681336
Short name T360
Test name
Test status
Simulation time 711468953 ps
CPU time 8.59 seconds
Started Aug 15 04:30:35 PM PDT 24
Finished Aug 15 04:30:44 PM PDT 24
Peak memory 200468 kb
Host smart-8279c6f7-1282-42c4-90a9-2c9ee3620dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283681336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4283681336
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.336822678
Short name T447
Test name
Test status
Simulation time 21799185790 ps
CPU time 1831.19 seconds
Started Aug 15 04:30:14 PM PDT 24
Finished Aug 15 05:00:45 PM PDT 24
Peak memory 743744 kb
Host smart-8ac1e83c-32f6-4f8e-b246-ccf0c3dda6af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336822678 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.336822678
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.442229627
Short name T495
Test name
Test status
Simulation time 158206102 ps
CPU time 8.27 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:30:28 PM PDT 24
Peak memory 200496 kb
Host smart-a7e8b940-5d6c-4836-bfcf-aecb33ed95fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442229627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.442229627
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1603230047
Short name T362
Test name
Test status
Simulation time 35589489 ps
CPU time 0.6 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:30:18 PM PDT 24
Peak memory 197180 kb
Host smart-a76f3d92-4858-4d6f-923d-bc33764f0a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603230047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1603230047
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1930801806
Short name T99
Test name
Test status
Simulation time 3155591890 ps
CPU time 92.28 seconds
Started Aug 15 04:30:37 PM PDT 24
Finished Aug 15 04:32:09 PM PDT 24
Peak memory 200580 kb
Host smart-64e3e00c-4989-4457-a5ca-a5d700b9b8d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930801806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1930801806
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.183925111
Short name T375
Test name
Test status
Simulation time 9365335547 ps
CPU time 60.52 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:31:07 PM PDT 24
Peak memory 200540 kb
Host smart-1d8da682-8df2-4a74-95bc-4bbe64680b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183925111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.183925111
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.798705552
Short name T533
Test name
Test status
Simulation time 4914489330 ps
CPU time 492.9 seconds
Started Aug 15 04:30:00 PM PDT 24
Finished Aug 15 04:38:14 PM PDT 24
Peak memory 653004 kb
Host smart-e4aa3023-8512-4700-8594-5c45e641cb61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798705552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.798705552
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2621356751
Short name T342
Test name
Test status
Simulation time 50764860590 ps
CPU time 219.84 seconds
Started Aug 15 04:30:19 PM PDT 24
Finished Aug 15 04:33:59 PM PDT 24
Peak memory 200484 kb
Host smart-f480ca8c-8c43-4bac-9a0c-30fd5f860240
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621356751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2621356751
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1879491877
Short name T207
Test name
Test status
Simulation time 14005233101 ps
CPU time 40.77 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:31:06 PM PDT 24
Peak memory 200524 kb
Host smart-58ea0ca0-a8db-4836-988b-978dfb818594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879491877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1879491877
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.334381920
Short name T215
Test name
Test status
Simulation time 1550067323 ps
CPU time 6.52 seconds
Started Aug 15 04:30:33 PM PDT 24
Finished Aug 15 04:30:40 PM PDT 24
Peak memory 200404 kb
Host smart-b5d5049e-d3b6-41c7-a5e2-4002f78fa21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334381920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.334381920
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1277230819
Short name T106
Test name
Test status
Simulation time 110219957167 ps
CPU time 3111.11 seconds
Started Aug 15 04:30:14 PM PDT 24
Finished Aug 15 05:22:05 PM PDT 24
Peak memory 778400 kb
Host smart-aa58a400-7846-4305-9ed5-974db43148bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277230819 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1277230819
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.3121910201
Short name T417
Test name
Test status
Simulation time 3595366804 ps
CPU time 52.05 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:31:00 PM PDT 24
Peak memory 200520 kb
Host smart-f067d26d-dfd0-45aa-85bc-f13042c753db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121910201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3121910201
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2910483289
Short name T382
Test name
Test status
Simulation time 74680990 ps
CPU time 0.57 seconds
Started Aug 15 04:30:17 PM PDT 24
Finished Aug 15 04:30:18 PM PDT 24
Peak memory 195492 kb
Host smart-59d60fa3-d856-4812-8b03-3a3233df464c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910483289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2910483289
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1456580187
Short name T205
Test name
Test status
Simulation time 6651826189 ps
CPU time 89.02 seconds
Started Aug 15 04:30:16 PM PDT 24
Finished Aug 15 04:31:45 PM PDT 24
Peak memory 200504 kb
Host smart-98f0e2fb-64e6-45d2-87a2-09685d8186ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456580187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1456580187
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.282243303
Short name T46
Test name
Test status
Simulation time 1034534110 ps
CPU time 75.23 seconds
Started Aug 15 04:30:23 PM PDT 24
Finished Aug 15 04:31:39 PM PDT 24
Peak memory 453808 kb
Host smart-9c190131-ea9e-4336-a553-740ef9702f66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282243303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.282243303
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3102280185
Short name T219
Test name
Test status
Simulation time 706085369 ps
CPU time 20.18 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:30:30 PM PDT 24
Peak memory 200368 kb
Host smart-5924bcd2-f844-4c2c-b967-6053522b6e2b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102280185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3102280185
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1396953098
Short name T184
Test name
Test status
Simulation time 42471710767 ps
CPU time 127.47 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:32:18 PM PDT 24
Peak memory 200640 kb
Host smart-a0b4ec65-6502-476d-9614-a37b0944c62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396953098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1396953098
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1329149559
Short name T268
Test name
Test status
Simulation time 421475696 ps
CPU time 7.48 seconds
Started Aug 15 04:30:08 PM PDT 24
Finished Aug 15 04:30:16 PM PDT 24
Peak memory 200500 kb
Host smart-7ab9e5d2-9a27-44b3-917e-1108926f6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329149559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1329149559
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3431420623
Short name T195
Test name
Test status
Simulation time 14799030035 ps
CPU time 401.23 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:36:56 PM PDT 24
Peak memory 200508 kb
Host smart-e37f34e4-43cb-4ca4-b65c-a997f79eabf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431420623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3431420623
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1517205794
Short name T8
Test name
Test status
Simulation time 2162978945 ps
CPU time 226.87 seconds
Started Aug 15 04:30:11 PM PDT 24
Finished Aug 15 04:33:58 PM PDT 24
Peak memory 613996 kb
Host smart-3eee4428-ff71-4097-a601-db847d16f6cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1517205794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1517205794
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.73757918
Short name T40
Test name
Test status
Simulation time 3894203009 ps
CPU time 33.2 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:49 PM PDT 24
Peak memory 200440 kb
Host smart-73be3f04-ec8f-4a2f-bc4c-19f7b68bb2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73757918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.73757918
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.421660799
Short name T412
Test name
Test status
Simulation time 18074076 ps
CPU time 0.56 seconds
Started Aug 15 04:30:10 PM PDT 24
Finished Aug 15 04:30:11 PM PDT 24
Peak memory 196132 kb
Host smart-944d6cd9-ddea-4109-bc26-c6f3e5e43fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421660799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.421660799
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1134701906
Short name T169
Test name
Test status
Simulation time 2138242562 ps
CPU time 30.27 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:30:51 PM PDT 24
Peak memory 200436 kb
Host smart-488c4a0c-0efd-4f2e-a876-1ce378f6443b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134701906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1134701906
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1474859601
Short name T385
Test name
Test status
Simulation time 3874707214 ps
CPU time 54.11 seconds
Started Aug 15 04:30:07 PM PDT 24
Finished Aug 15 04:31:01 PM PDT 24
Peak memory 200472 kb
Host smart-d61bfa0c-ec88-479c-930a-79ae37bbaa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474859601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1474859601
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2460013642
Short name T520
Test name
Test status
Simulation time 3644659363 ps
CPU time 631.54 seconds
Started Aug 15 04:30:25 PM PDT 24
Finished Aug 15 04:40:57 PM PDT 24
Peak memory 644932 kb
Host smart-fc757a31-591e-4d37-b74a-068ef534b0dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460013642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2460013642
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2768937157
Short name T280
Test name
Test status
Simulation time 1048950688 ps
CPU time 57.83 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:31:13 PM PDT 24
Peak memory 200628 kb
Host smart-e79a7809-f76e-429d-9f52-cc8b9de15367
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768937157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2768937157
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1382788319
Short name T321
Test name
Test status
Simulation time 47668897044 ps
CPU time 147.78 seconds
Started Aug 15 04:30:18 PM PDT 24
Finished Aug 15 04:32:46 PM PDT 24
Peak memory 200492 kb
Host smart-5ee8837a-fff3-4dc2-a2cf-fa363a250a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382788319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1382788319
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2513841618
Short name T27
Test name
Test status
Simulation time 309515138 ps
CPU time 13.34 seconds
Started Aug 15 04:30:21 PM PDT 24
Finished Aug 15 04:30:34 PM PDT 24
Peak memory 200484 kb
Host smart-39cfb04d-913a-4ad5-a9c2-eff609196780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513841618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2513841618
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.4175708550
Short name T25
Test name
Test status
Simulation time 32334239513 ps
CPU time 1160.07 seconds
Started Aug 15 04:30:09 PM PDT 24
Finished Aug 15 04:49:29 PM PDT 24
Peak memory 657012 kb
Host smart-e8045f0f-ae34-477b-af32-2af3c7127f75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175708550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.4175708550
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2232127154
Short name T454
Test name
Test status
Simulation time 6257654969 ps
CPU time 27.24 seconds
Started Aug 15 04:30:15 PM PDT 24
Finished Aug 15 04:30:42 PM PDT 24
Peak memory 200572 kb
Host smart-abe05e68-be32-436e-9506-c7df8b6beb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232127154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2232127154
Directory /workspace/9.hmac_wipe_secret/latest
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