Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17601879	1			T1	4753		T3	22524		T6	6498
all_values[1]	17601879	1			T1	4753		T3	22524		T6	6498
all_values[2]	17601879	1			T1	4753		T3	22524		T6	6498

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299956

1

T3

4163

T6

3966

T8

663

auto[1]

52505681

1

T1

14259

T3

63409

T6

15528

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45007359

1

T1

12014

T3

53752

T6

15112

auto[1]

7798278

1

T1

2245

T3

13820

T6

4382

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	116874	1			T3	4159		T8	4		T23	1494
all_values[0]	auto[0]	auto[1]	385	1			T3	4		T23	2		T40	2
all_values[0]	auto[1]	auto[0]	17465106	1			T1	4744		T3	18360		T6	6496
all_values[0]	auto[1]	auto[1]	19514	1			T1	9		T3	1		T6	2
all_values[1]	auto[0]	auto[0]	102218	1			T6	1983		T8	608		T5	3
all_values[1]	auto[0]	auto[1]	204	1			T8	2		T20	1		T9	5
all_values[1]	auto[1]	auto[0]	17499169	1			T1	4753		T3	22524		T6	4515
all_values[1]	auto[1]	auto[1]	288	1			T8	2		T9	7		T12	6
all_values[2]	auto[0]	auto[0]	41214	1			T6	1		T8	11		T18	1
all_values[2]	auto[0]	auto[1]	39061	1			T6	1982		T8	38		T18	1677
all_values[2]	auto[1]	auto[0]	9782778	1			T1	2517		T3	8709		T6	2117
all_values[2]	auto[1]	auto[1]	7738826	1			T1	2236		T3	13815		T6	2398