Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

112997

1

T1

20

T6

8

T7

28

auto[1]

110172

1

T3

18

T6

4

T7

20

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	82928	1			T1	8		T3	5		T6	4
len_1026_2046	5311	1			T7	1		T8	10		T20	576
len_514_1022	4150	1			T7	2		T8	7		T23	1
len_2_510	3595	1			T8	15		T20	19		T21	12
len_2056	209	1			T7	2		T8	3		T83	2
len_2048	278	1			T8	9		T5	1		T20	1
len_2040	363	1			T7	3		T8	11		T123	6
len_1032	112	1			T7	1		T8	9		T9	1
len_1024	1731	1			T7	4		T8	7		T23	2
len_1016	161	1			T7	4		T8	8		T20	5
len_520	130	1			T8	10		T80	2		T83	2
len_512	317	1			T1	1		T7	4		T4	1
len_504	155	1			T7	1		T8	9		T20	2
len_8	1128	1			T3	4		T5	8		T20	8
len_0	11016	1			T1	1		T6	2		T7	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

93

1

T3

2

T23

1

T81

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	43709	1			T1	8		T6	3		T4	10
auto[0]	len_1026_2046	2244	1			T7	1		T8	5		T20	130
auto[0]	len_514_1022	2643	1			T8	4		T23	1		T20	9
auto[0]	len_2_510	1757	1			T8	11		T20	6		T21	8
auto[0]	len_2056	121	1			T7	1		T8	2		T83	1
auto[0]	len_2048	155	1			T8	8		T81	2		T82	1
auto[0]	len_2040	107	1			T7	2		T8	8		T123	5
auto[0]	len_1032	65	1			T7	1		T8	5		T9	1
auto[0]	len_1024	201	1			T7	2		T8	6		T23	2
auto[0]	len_1016	100	1			T7	4		T8	6		T20	5
auto[0]	len_520	74	1			T8	5		T80	2		T83	2
auto[0]	len_512	182	1			T1	1		T7	2		T81	2
auto[0]	len_504	87	1			T8	4		T80	1		T9	1
auto[0]	len_8	46	1			T80	1		T124	1		T125	1
auto[0]	len_0	5007	1			T1	1		T6	1		T7	1
auto[1]	len_2050_plus	39219	1			T3	5		T6	1		T4	9
auto[1]	len_1026_2046	3067	1			T8	5		T20	446		T36	4
auto[1]	len_514_1022	1507	1			T7	2		T8	3		T20	8
auto[1]	len_2_510	1838	1			T8	4		T20	13		T21	4
auto[1]	len_2056	88	1			T7	1		T8	1		T83	1
auto[1]	len_2048	123	1			T8	1		T5	1		T20	1
auto[1]	len_2040	256	1			T7	1		T8	3		T123	1
auto[1]	len_1032	47	1			T8	4		T126	1		T127	1
auto[1]	len_1024	1530	1			T7	2		T8	1		T20	1
auto[1]	len_1016	61	1			T8	2		T32	2		T33	2
auto[1]	len_520	56	1			T8	5		T9	1		T48	2
auto[1]	len_512	135	1			T7	2		T4	1		T8	1
auto[1]	len_504	68	1			T7	1		T8	5		T20	2
auto[1]	len_8	1082	1			T3	4		T5	8		T20	8
auto[1]	len_0	6009	1			T6	1		T7	1		T8	30

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

49

1

T23

1

T81

1

T12

4

auto[1]

len_upper

44

1

T3

2

T39

1

T38

2