Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4310644 1 T1 616 T3 5754 T6 415
auto[1] 2581792 1 T1 1730 T3 5390 T6 968


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2541753 1 T1 1528 T3 5795 T6 1
auto[1] 4350683 1 T1 818 T3 5349 T6 1382


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3310664 1 T1 2066 T6 968 T7 542
auto[1] 3581772 1 T1 280 T3 11144 T6 415


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4287141 1 T1 1898 T3 7211 T6 967
auto[1] 2605295 1 T1 448 T3 3933 T6 416


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6278023 1 T1 2106 T3 10703 T6 1360
fifo_depth[1] 115326 1 T1 41 T3 77 T6 17
fifo_depth[2] 87687 1 T1 36 T3 58 T6 5
fifo_depth[3] 69639 1 T1 34 T3 69 T6 1
fifo_depth[4] 62975 1 T1 37 T3 83 T7 11
fifo_depth[5] 48999 1 T1 35 T3 44 T7 12
fifo_depth[6] 38730 1 T1 26 T3 39 T7 8
fifo_depth[7] 24816 1 T1 20 T3 36 T7 5


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 614413 1 T1 240 T3 441 T6 23
auto[1] 6278023 1 T1 2106 T3 10703 T6 1360


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6884041 1 T1 2346 T3 11144 T6 1383
auto[1] 8395 1 T12 296 T131 372 T13 935


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 24963 1 T1 135 T7 14 T4 1
auto[0] auto[0] auto[0] auto[0] auto[1] 28938 1 T7 2 T8 542 T23 4
auto[0] auto[0] auto[0] auto[1] auto[0] 23086 1 T1 51 T7 5 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] 24381 1 T1 28 T7 4 T8 30
auto[0] auto[0] auto[1] auto[0] auto[0] 138142 1 T8 318 T20 139 T36 631
auto[0] auto[0] auto[1] auto[0] auto[1] 29947 1 T7 11 T8 234 T20 15
auto[0] auto[0] auto[1] auto[1] auto[0] 27598 1 T1 26 T6 23 T7 5
auto[0] auto[0] auto[1] auto[1] auto[1] 28926 1 T7 10 T8 102 T23 4
auto[0] auto[1] auto[0] auto[0] auto[0] 26345 1 T8 185 T20 147 T40 9
auto[0] auto[1] auto[0] auto[0] auto[1] 34834 1 T8 415 T20 39 T21 96
auto[0] auto[1] auto[0] auto[1] auto[0] 47032 1 T3 9 T7 14 T4 1
auto[0] auto[1] auto[0] auto[1] auto[1] 35834 1 T7 9 T4 1 T8 192
auto[0] auto[1] auto[1] auto[0] auto[0] 46670 1 T4 1 T8 228 T23 19
auto[0] auto[1] auto[1] auto[0] auto[1] 29216 1 T7 16 T4 1 T8 316
auto[0] auto[1] auto[1] auto[1] auto[0] 33055 1 T3 432 T8 141 T5 152
auto[0] auto[1] auto[1] auto[1] auto[1] 35446 1 T8 146 T20 97 T40 49
auto[1] auto[0] auto[0] auto[0] auto[0] 178447 1 T1 237 T7 79 T4 1
auto[1] auto[0] auto[0] auto[0] auto[1] 178944 1 T1 34 T7 25 T4 1
auto[1] auto[0] auto[0] auto[1] auto[0] 182898 1 T1 657 T7 102 T4 1
auto[1] auto[0] auto[0] auto[1] auto[1] 169233 1 T1 106 T7 36 T4 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1728905 1 T1 210 T7 42 T4 2
auto[1] auto[0] auto[1] auto[0] auto[1] 185044 1 T6 1 T7 30 T4 1
auto[1] auto[0] auto[1] auto[1] auto[0] 181227 1 T1 582 T6 944 T7 115
auto[1] auto[0] auto[1] auto[1] auto[1] 179985 1 T7 62 T8 915 T18 15
auto[1] auto[1] auto[0] auto[0] auto[0] 386980 1 T4 1 T8 1333 T5 2
auto[1] auto[1] auto[0] auto[0] auto[1] 410124 1 T3 3931 T4 2 T8 1837
auto[1] auto[1] auto[0] auto[1] auto[0] 392907 1 T3 1855 T7 24 T4 1
auto[1] auto[1] auto[0] auto[1] auto[1] 396807 1 T1 280 T6 1 T7 68
auto[1] auto[1] auto[1] auto[0] auto[0] 461584 1 T3 1821 T7 35 T4 3
auto[1] auto[1] auto[1] auto[0] auto[1] 421561 1 T3 2 T6 414 T7 56
auto[1] auto[1] auto[1] auto[1] auto[0] 407302 1 T3 3094 T7 10 T4 1
auto[1] auto[1] auto[1] auto[1] auto[1] 416075 1 T7 73 T4 1 T8 1210


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 203138 1 T1 372 T7 93 T4 2
auto[0] auto[0] auto[0] auto[0] auto[1] 207125 1 T1 34 T7 27 T4 1
auto[0] auto[0] auto[0] auto[1] auto[0] 205947 1 T1 708 T7 107 T4 2
auto[0] auto[0] auto[0] auto[1] auto[1] 192398 1 T1 134 T7 40 T4 1
auto[0] auto[0] auto[1] auto[0] auto[0] 1866460 1 T1 210 T7 42 T4 2
auto[0] auto[0] auto[1] auto[0] auto[1] 214337 1 T6 1 T7 41 T4 1
auto[0] auto[0] auto[1] auto[1] auto[0] 207591 1 T1 608 T6 967 T7 120
auto[0] auto[0] auto[1] auto[1] auto[1] 208153 1 T7 72 T8 1017 T18 15
auto[0] auto[1] auto[0] auto[0] auto[0] 413036 1 T4 1 T8 1518 T5 2
auto[0] auto[1] auto[0] auto[0] auto[1] 444763 1 T3 3931 T4 2 T8 2252
auto[0] auto[1] auto[0] auto[1] auto[0] 439522 1 T3 1864 T7 38 T4 2
auto[0] auto[1] auto[0] auto[1] auto[1] 431692 1 T1 280 T6 1 T7 77
auto[0] auto[1] auto[1] auto[0] auto[0] 508130 1 T3 1821 T7 35 T4 4
auto[0] auto[1] auto[1] auto[0] auto[1] 450362 1 T3 2 T6 414 T7 72
auto[0] auto[1] auto[1] auto[1] auto[0] 440204 1 T3 3526 T7 10 T4 1
auto[0] auto[1] auto[1] auto[1] auto[1] 451183 1 T7 73 T4 1 T8 1356
auto[1] auto[0] auto[0] auto[0] auto[0] 272 1 T12 25 T132 194 T133 1
auto[1] auto[0] auto[0] auto[0] auto[1] 757 1 T13 2 T134 38 T37 17
auto[1] auto[0] auto[0] auto[1] auto[0] 37 1 T12 6 T13 1 T134 8
auto[1] auto[0] auto[0] auto[1] auto[1] 1216 1 T131 2 T13 2 T134 84
auto[1] auto[0] auto[1] auto[0] auto[0] 587 1 T131 8 T135 40 T133 7
auto[1] auto[0] auto[1] auto[0] auto[1] 654 1 T12 32 T13 77 T134 69
auto[1] auto[0] auto[1] auto[1] auto[0] 1234 1 T12 1 T13 500 T134 13
auto[1] auto[0] auto[1] auto[1] auto[1] 758 1 T131 294 T134 13 T132 4
auto[1] auto[1] auto[0] auto[0] auto[0] 289 1 T12 172 T37 8 T136 3
auto[1] auto[1] auto[0] auto[0] auto[1] 195 1 T134 90 T133 26 T137 52
auto[1] auto[1] auto[0] auto[1] auto[0] 417 1 T131 68 T13 45 T133 21
auto[1] auto[1] auto[0] auto[1] auto[1] 949 1 T138 15 T133 276 T137 4
auto[1] auto[1] auto[1] auto[0] auto[0] 124 1 T132 33 T137 80 T139 1
auto[1] auto[1] auto[1] auto[0] auto[1] 415 1 T12 60 T135 122 T140 8
auto[1] auto[1] auto[1] auto[1] auto[0] 153 1 T134 8 T132 1 T135 54
auto[1] auto[1] auto[1] auto[1] auto[1] 338 1 T13 308 T37 7 T133 8


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 178447 1 T1 237 T7 79 T4 1
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 178944 1 T1 34 T7 25 T4 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 182898 1 T1 657 T7 102 T4 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 169233 1 T1 106 T7 36 T4 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1728905 1 T1 210 T7 42 T4 2
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 185044 1 T6 1 T7 30 T4 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 181227 1 T1 582 T6 944 T7 115
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 179985 1 T7 62 T8 915 T18 15
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 386980 1 T4 1 T8 1333 T5 2
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 410124 1 T3 3931 T4 2 T8 1837
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 392907 1 T3 1855 T7 24 T4 1
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 396807 1 T1 280 T6 1 T7 68
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 461584 1 T3 1821 T7 35 T4 3
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 421561 1 T3 2 T6 414 T7 56
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 407302 1 T3 3094 T7 10 T4 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 416075 1 T7 73 T4 1 T8 1210
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3774 1 T1 26 T7 1 T8 49
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4015 1 T7 1 T8 120 T23 4
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3442 1 T1 9 T4 1 T8 10
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3526 1 T1 4 T8 6 T23 7
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 42371 1 T8 75 T20 88 T36 111
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3716 1 T7 1 T8 42 T20 13
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3690 1 T1 2 T6 17 T7 2
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3949 1 T7 3 T8 8 T23 3
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 4676 1 T8 23 T20 92 T40 6
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5933 1 T8 98 T20 22 T21 12
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6308 1 T3 2 T7 3 T8 45
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 4954 1 T7 1 T8 26 T20 11
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8917 1 T8 28 T23 13 T20 46
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 4739 1 T7 2 T8 62 T20 90
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5622 1 T3 75 T8 23 T5 27
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5694 1 T8 22 T20 53 T40 33
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3023 1 T1 22 T7 2 T8 54
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3091 1 T8 117 T20 26 T21 16
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2709 1 T1 7 T8 7 T18 13
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2721 1 T1 4 T7 1 T8 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 27657 1 T8 80 T20 28 T36 108
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2838 1 T7 2 T8 40 T20 2
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2780 1 T1 3 T6 5 T8 18
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3157 1 T8 16 T20 8 T36 8
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 3865 1 T8 25 T20 36 T40 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5049 1 T8 106 T20 5 T21 12
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5256 1 T3 1 T7 1 T8 49
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4336 1 T7 2 T4 1 T8 39
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7631 1 T8 32 T23 5 T20 7
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 3919 1 T7 2 T8 52 T20 41
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 4803 1 T3 57 T8 16 T5 23
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4852 1 T8 24 T20 25 T40 14
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2260 1 T1 20 T7 2 T8 54
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2253 1 T8 91 T20 3 T21 9
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2184 1 T1 6 T7 1 T8 12
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2085 1 T1 5 T7 1 T8 7
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 19861 1 T8 63 T20 7 T36 101
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2227 1 T7 5 T8 45 T21 13
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2030 1 T1 3 T6 1 T7 2
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2407 1 T7 2 T8 19 T23 1
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3279 1 T8 21 T20 10 T21 13
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4449 1 T8 67 T21 11 T36 11
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4475 1 T3 2 T7 1 T8 42
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3688 1 T7 1 T8 32 T20 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6453 1 T8 31 T20 3 T36 36
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3404 1 T7 2 T4 1 T8 46
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4286 1 T3 67 T8 21 T5 21
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4298 1 T8 16 T20 12 T40 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2365 1 T1 19 T7 4 T8 38
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2338 1 T7 1 T8 86 T21 13
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2105 1 T1 10 T7 1 T8 9
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2115 1 T1 3 T8 6 T21 18
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 14718 1 T8 40 T20 7 T36 93
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2454 1 T8 28 T21 12 T36 19
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2087 1 T1 5 T8 12 T81 7
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2300 1 T7 2 T8 17 T36 11
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3089 1 T8 33 T20 5 T21 12
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4299 1 T8 54 T20 12 T21 21
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4361 1 T3 2 T7 1 T8 51
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3572 1 T7 1 T8 33 T21 4
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5924 1 T8 33 T23 1 T20 3
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3167 1 T7 1 T8 35 T20 13
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4058 1 T3 81 T8 18 T5 19
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4023 1 T8 23 T20 3 T21 16
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1604 1 T1 21 T7 2 T8 41
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1606 1 T8 54 T21 9 T36 6
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1648 1 T1 7 T7 1 T8 4
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1609 1 T1 5 T8 3 T21 15
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 10154 1 T8 25 T20 4 T36 92
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1802 1 T7 2 T8 36 T21 11
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1499 1 T1 2 T7 1 T8 15
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1783 1 T7 2 T8 11 T36 8
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2676 1 T8 19 T20 3 T21 9
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3756 1 T8 37 T21 12 T36 12
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3523 1 T3 1 T7 1 T8 31
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 2959 1 T8 22 T21 9 T36 23
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4748 1 T8 29 T36 25 T141 49
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 2736 1 T7 3 T8 42 T20 2
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3461 1 T3 43 T8 13 T5 20
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3435 1 T8 16 T20 2 T40 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1409 1 T1 15 T7 1 T8 20
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1535 1 T8 43 T21 8 T36 9
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1297 1 T1 8 T7 1 T8 10
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1334 1 T1 3 T8 2 T21 12
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7335 1 T8 22 T20 5 T36 60
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1448 1 T8 22 T21 9 T36 9
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1264 1 T8 15 T81 2 T82 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1478 1 T7 1 T8 11 T36 5
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2106 1 T8 25 T20 1 T21 4
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2967 1 T8 27 T21 10 T36 7
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2812 1 T7 3 T8 25 T5 82
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2465 1 T7 1 T8 16 T21 7
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3614 1 T8 26 T36 9 T141 14
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2080 1 T7 1 T8 27 T82 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2806 1 T3 39 T8 18 T5 16
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2780 1 T8 20 T20 2 T21 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 914 1 T1 9 T7 1 T8 16
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 916 1 T8 18 T21 12 T36 6
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 875 1 T1 4 T8 5 T20 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 842 1 T1 2 T21 11 T113 10
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4200 1 T8 4 T36 38 T82 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 838 1 T7 1 T8 10 T21 7
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 747 1 T1 5 T8 10 T81 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 921 1 T8 8 T36 4 T82 3
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1470 1 T8 20 T21 7 T36 2
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1940 1 T8 14 T21 12 T36 6
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1932 1 T7 1 T8 13 T5 78
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1729 1 T7 1 T8 19 T21 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2311 1 T8 25 T36 2 T141 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1432 1 T7 1 T8 19 T82 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1876 1 T3 36 T8 9 T5 13
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1873 1 T8 13 T21 3 T82 2

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