Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17601879	1			T1	4753		T3	22524		T6	6498
all_pins[1]	17601879	1			T1	4753		T3	22524		T6	6498
all_pins[2]	17601879	1			T1	4753		T3	22524		T6	6498

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45046172	1			T1	12014		T3	53756		T6	17094
values[0x1]	7759465	1			T1	2245		T3	13816		T6	2400
transitions[0x0=>0x1]	7759267	1			T1	2245		T3	13816		T6	2400
transitions[0x1=>0x0]	7759283	1			T1	2245		T3	13816		T6	2400

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17581541	1			T1	4744		T3	22523		T6	6496
all_pins[0]	values[0x1]	20338	1			T1	9		T3	1		T6	2
all_pins[0]	transitions[0x0=>0x1]	20256	1			T1	9		T3	1		T6	2
all_pins[0]	transitions[0x1=>0x0]	7738760	1			T1	2236		T3	13815		T6	2398
all_pins[1]	values[0x0]	17601578	1			T1	4753		T3	22524		T6	6498
all_pins[1]	values[0x1]	301	1			T8	2		T9	7		T12	8
all_pins[1]	transitions[0x0=>0x1]	250	1			T8	1		T9	4		T12	8
all_pins[1]	transitions[0x1=>0x0]	20287	1			T1	9		T3	1		T6	2
all_pins[2]	values[0x0]	9863053	1			T1	2517		T3	8709		T6	4100
all_pins[2]	values[0x1]	7738826	1			T1	2236		T3	13815		T6	2398
all_pins[2]	transitions[0x0=>0x1]	7738761	1			T1	2236		T3	13815		T6	2398
all_pins[2]	transitions[0x1=>0x0]	236	1			T8	1		T9	2		T12	8