Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 980 1 T8 7 T20 4 T9 24
all_values[1] 980 1 T8 7 T20 4 T9 24
all_values[2] 980 1 T8 7 T20 4 T9 24


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1481 1 T8 10 T20 4 T9 28
auto[1] 1459 1 T8 11 T20 8 T9 44


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1038 1 T8 6 T20 4 T9 15
auto[1] 1902 1 T8 15 T20 8 T9 57


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1670 1 T8 12 T20 6 T9 36
auto[1] 1270 1 T8 9 T20 6 T9 36


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 172 1 T8 3 T9 1 T12 3
all_values[0] auto[0] auto[0] auto[1] 97 1 T9 4 T71 4 T24 2
all_values[0] auto[0] auto[1] auto[0] 177 1 T8 1 T9 3 T12 1
all_values[0] auto[0] auto[1] auto[1] 109 1 T8 1 T20 1 T9 5
all_values[0] auto[1] auto[0] auto[1] 213 1 T9 5 T12 2 T71 14
all_values[0] auto[1] auto[1] auto[1] 212 1 T8 2 T20 3 T9 6
all_values[1] auto[0] auto[0] auto[0] 167 1 T9 1 T12 3 T71 4
all_values[1] auto[0] auto[0] auto[1] 141 1 T8 2 T20 1 T9 3
all_values[1] auto[0] auto[1] auto[0] 137 1 T20 2 T9 5 T12 2
all_values[1] auto[0] auto[1] auto[1] 121 1 T8 1 T9 3 T12 3
all_values[1] auto[1] auto[0] auto[1] 208 1 T8 3 T20 1 T9 4
all_values[1] auto[1] auto[1] auto[1] 206 1 T8 1 T9 8 T71 10
all_values[2] auto[0] auto[0] auto[0] 195 1 T8 1 T20 2 T9 2
all_values[2] auto[0] auto[0] auto[1] 83 1 T8 1 T9 3 T12 1
all_values[2] auto[0] auto[1] auto[0] 190 1 T8 1 T9 3 T71 11
all_values[2] auto[0] auto[1] auto[1] 81 1 T8 1 T9 3 T12 1
all_values[2] auto[1] auto[0] auto[1] 205 1 T9 5 T12 4 T71 8
all_values[2] auto[1] auto[1] auto[1] 226 1 T8 3 T20 2 T9 8


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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