Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4060	1			T1	4		T3	1		T7	6
sha2_none	4095	1			T1	1		T3	2		T7	7
sha2_512	7562	1			T1	4		T3	2		T6	1
sha2_384	7265	1			T1	1		T3	4		T6	1
sha2_256	6154	1			T1	1		T3	1		T6	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18333

1

T1

5

T3

4

T6

1

auto[1]

11167

1

T1

6

T3

6

T6

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10915

1

T1

8

T3

4

T7

18

auto[1]

18585

1

T1

3

T3

6

T6

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14955

1

T1

1

T3

10

T6

1

disabled

14545

1

T1

10

T6

2

T7

21

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4627	1			T1	3		T3	2		T6	1
key_none	7655	1			T1	1		T3	2		T6	1
key_1024	4342	1			T1	3		T3	1		T6	1
key_512	3737	1			T3	1		T7	5		T4	3
key_384	3342	1			T7	8		T4	4		T8	31
key_256	2935	1			T1	2		T3	2		T7	10
key_128	2798	1			T1	2		T3	2		T7	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18577

1

T1

6

T3

7

T6

2

auto[1]

10923

1

T1

5

T3

3

T6

1

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29290

1

T1

11

T3

10

T6

3

disabled

210

1

T8

2

T20

8

T40

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1479

1

T4

1

T8

17

T5

1

enabled

auto[0]

auto[0]

auto[1]

1519

1

T3

2

T4

2

T8

25

enabled

auto[0]

auto[1]

auto[0]

1614

1

T3

2

T7

3

T4

2

enabled

auto[0]

auto[1]

auto[1]

1468

1

T1

1

T7

4

T4

2

enabled

auto[1]

auto[0]

auto[0]

4199

1

T3

1

T7

3

T4

4

enabled

auto[1]

auto[0]

auto[1]

1530

1

T3

1

T6

1

T7

5

enabled

auto[1]

auto[1]

auto[0]

1604

1

T3

4

T7

1

T4

1

enabled

auto[1]

auto[1]

auto[1]

1542

1

T7

2

T4

1

T8

23

disabled

auto[0]

auto[0]

auto[0]

1189

1

T1

1

T7

5

T4

2

disabled

auto[0]

auto[0]

auto[1]

1201

1

T1

3

T7

2

T4

1

disabled

auto[0]

auto[1]

auto[0]

1248

1

T1

2

T7

3

T4

2

disabled

auto[0]

auto[1]

auto[1]

1197

1

T1

1

T7

1

T4

1

disabled

auto[1]

auto[0]

auto[0]

6015

1

T1

1

T7

2

T4

2

disabled

auto[1]

auto[0]

auto[1]

1201

1

T7

1

T4

1

T8

25

disabled

auto[1]

auto[1]

auto[0]

1229

1

T1

2

T6

2

T7

4

disabled

auto[1]

auto[1]

auto[1]

1265

1

T7

3

T8

16

T18

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14877

1

T1

1

T3

10

T6

1

enabled

disabled

78

1

T20

5

T40

1

T42

1

disabled

disabled

132

1

T8

2

T20

3

T40

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14413

1

T1

10

T6

2

T7

21

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1106	1			T1	1		T7	1		T4	1
key_invalid	sha2_none	853	1			T8	13		T18	1		T5	1
key_invalid	sha2_512	853	1			T1	2		T7	2		T8	17
key_invalid	sha2_384	848	1			T3	1		T6	1		T7	2
key_invalid	sha2_256	872	1			T3	1		T4	1		T8	18
key_none	sha2_invalid	496	1			T3	1		T7	1		T4	2
key_none	sha2_none	561	1			T4	1		T8	13		T20	4
key_none	sha2_512	2507	1			T1	1		T3	1		T7	2
key_none	sha2_384	2478	1			T7	1		T4	2		T8	8
key_none	sha2_256	1564	1			T6	1		T7	1		T4	1
key_1024	sha2_invalid	463	1			T1	1		T8	5		T5	1
key_1024	sha2_none	539	1			T1	1		T3	1		T7	1
key_1024	sha2_512	1760	1			T1	1		T6	1		T4	2
key_1024	sha2_384	941	1			T7	2		T4	1		T8	10
key_512	sha2_invalid	532	1			T7	1		T4	1		T8	9
key_512	sha2_none	515	1			T7	1		T4	1		T8	7
key_512	sha2_512	607	1			T7	1		T8	12		T5	1
key_512	sha2_384	1217	1			T3	1		T7	1		T4	1
key_512	sha2_256	826	1			T7	1		T8	7		T20	8
key_384	sha2_invalid	501	1			T7	3		T4	2		T8	5
key_384	sha2_none	555	1			T7	1		T8	3		T5	1
key_384	sha2_512	589	1			T8	8		T23	2		T20	12
key_384	sha2_384	611	1			T7	2		T4	1		T8	7
key_384	sha2_256	1045	1			T7	1		T4	1		T8	7
key_256	sha2_invalid	477	1			T1	1		T8	5		T23	1
key_256	sha2_none	545	1			T7	3		T8	7		T20	11
key_256	sha2_512	604	1			T7	3		T8	4		T18	1
key_256	sha2_384	605	1			T1	1		T3	2		T7	1
key_256	sha2_256	661	1			T7	3		T8	10		T20	9
key_128	sha2_invalid	473	1			T1	1		T4	2		T8	8
key_128	sha2_none	518	1			T3	1		T7	1		T8	9
key_128	sha2_512	625	1			T3	1		T8	13		T5	1
key_128	sha2_384	559	1			T4	2		T8	14		T20	12
key_128	sha2_256	573	1			T1	1		T7	1		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

595

1

T4

2

T8

8

T20

14

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1106	1			T1	1		T7	1		T4	1
key_invalid	sha2_none	853	1			T8	13		T18	1		T5	1
key_invalid	sha2_512	853	1			T1	2		T7	2		T8	17
key_invalid	sha2_384	848	1			T3	1		T6	1		T7	2
key_invalid	sha2_256	872	1			T3	1		T4	1		T8	18
key_none	sha2_invalid	496	1			T3	1		T7	1		T4	2
key_none	sha2_none	561	1			T4	1		T8	13		T20	4
key_none	sha2_512	2507	1			T1	1		T3	1		T7	2
key_none	sha2_384	2478	1			T7	1		T4	2		T8	8
key_none	sha2_256	1564	1			T6	1		T7	1		T4	1
key_1024	sha2_invalid	463	1			T1	1		T8	5		T5	1
key_1024	sha2_none	539	1			T1	1		T3	1		T7	1
key_1024	sha2_512	1760	1			T1	1		T6	1		T4	2
key_1024	sha2_384	941	1			T7	2		T4	1		T8	10
key_1024	sha2_256	595	1			T4	2		T8	8		T20	14
key_512	sha2_invalid	532	1			T7	1		T4	1		T8	9
key_512	sha2_none	515	1			T7	1		T4	1		T8	7
key_512	sha2_512	607	1			T7	1		T8	12		T5	1
key_512	sha2_384	1217	1			T3	1		T7	1		T4	1
key_512	sha2_256	826	1			T7	1		T8	7		T20	8
key_384	sha2_invalid	501	1			T7	3		T4	2		T8	5
key_384	sha2_none	555	1			T7	1		T8	3		T5	1
key_384	sha2_512	589	1			T8	8		T23	2		T20	12
key_384	sha2_384	611	1			T7	2		T4	1		T8	7
key_384	sha2_256	1045	1			T7	1		T4	1		T8	7
key_256	sha2_invalid	477	1			T1	1		T8	5		T23	1
key_256	sha2_none	545	1			T7	3		T8	7		T20	11
key_256	sha2_512	604	1			T7	3		T8	4		T18	1
key_256	sha2_384	605	1			T1	1		T3	2		T7	1
key_256	sha2_256	661	1			T7	3		T8	10		T20	9
key_128	sha2_invalid	473	1			T1	1		T4	2		T8	8
key_128	sha2_none	518	1			T3	1		T7	1		T8	9
key_128	sha2_512	625	1			T3	1		T8	13		T5	1
key_128	sha2_384	559	1			T4	2		T8	14		T20	12
key_128	sha2_256	573	1			T1	1		T7	1		T4	2