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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.47 95.40 97.27 100.00 100.00 98.27 98.48 99.85


Total test records in report: 654
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T89 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2598220769 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:21 PM PDT 24 19443308 ps
T58 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2659711001 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:18 PM PDT 24 97933572 ps
T534 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3971595762 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:22 PM PDT 24 1158870808 ps
T535 /workspace/coverage/cover_reg_top/18.hmac_intr_test.162856352 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:14 PM PDT 24 13645534 ps
T105 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3233692389 Aug 16 05:41:08 PM PDT 24 Aug 16 05:41:10 PM PDT 24 372587860 ps
T536 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3610255960 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:14 PM PDT 24 25782765 ps
T90 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3673753645 Aug 16 05:40:58 PM PDT 24 Aug 16 05:40:59 PM PDT 24 270340802 ps
T106 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4245919749 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:28 PM PDT 24 147559119 ps
T537 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1788440960 Aug 16 05:41:28 PM PDT 24 Aug 16 05:41:29 PM PDT 24 87630110 ps
T107 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.126933078 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:15 PM PDT 24 87644180 ps
T538 /workspace/coverage/cover_reg_top/35.hmac_intr_test.231476900 Aug 16 05:41:56 PM PDT 24 Aug 16 05:41:57 PM PDT 24 16075271 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3868600964 Aug 16 05:41:23 PM PDT 24 Aug 16 05:41:24 PM PDT 24 62953878 ps
T109 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.833990798 Aug 16 05:41:18 PM PDT 24 Aug 16 05:41:19 PM PDT 24 240985507 ps
T539 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3662094419 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:21 PM PDT 24 87009339 ps
T540 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1154993925 Aug 16 05:41:24 PM PDT 24 Aug 16 05:41:25 PM PDT 24 26713709 ps
T110 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2898221361 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:13 PM PDT 24 523641824 ps
T91 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3410852204 Aug 16 05:41:07 PM PDT 24 Aug 16 05:41:18 PM PDT 24 18225878863 ps
T92 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3141389669 Aug 16 05:41:01 PM PDT 24 Aug 16 05:41:07 PM PDT 24 1400828987 ps
T541 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3021990132 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:21 PM PDT 24 18112855 ps
T542 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1215366534 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:11 PM PDT 24 83535251 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1902167655 Aug 16 05:41:05 PM PDT 24 Aug 16 05:41:06 PM PDT 24 23523004 ps
T543 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1090483787 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:17 PM PDT 24 551759158 ps
T544 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3078250859 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:13 PM PDT 24 30400296 ps
T545 /workspace/coverage/cover_reg_top/39.hmac_intr_test.2428238647 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:18 PM PDT 24 36892982 ps
T111 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1750261587 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 58379597 ps
T116 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4033950973 Aug 16 05:41:36 PM PDT 24 Aug 16 05:41:40 PM PDT 24 133779778 ps
T112 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2569852550 Aug 16 05:41:08 PM PDT 24 Aug 16 05:41:09 PM PDT 24 23502910 ps
T546 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.236220106 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:19 PM PDT 24 231735096 ps
T547 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4222436827 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:21 PM PDT 24 14589050 ps
T548 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.881360670 Aug 16 05:40:58 PM PDT 24 Aug 16 05:41:00 PM PDT 24 211984338 ps
T549 /workspace/coverage/cover_reg_top/3.hmac_intr_test.18108731 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:11 PM PDT 24 11286699 ps
T550 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3124127194 Aug 16 05:41:46 PM PDT 24 Aug 16 05:41:46 PM PDT 24 33195450 ps
T551 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4006797530 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:28 PM PDT 24 175566856 ps
T552 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.67747201 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:14 PM PDT 24 787694011 ps
T553 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3856305270 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:15 PM PDT 24 292804831 ps
T118 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1371765535 Aug 16 05:41:09 PM PDT 24 Aug 16 05:41:11 PM PDT 24 96640037 ps
T554 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4104646314 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:13 PM PDT 24 323003107 ps
T555 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1983645586 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 37017803 ps
T556 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1527672397 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:18 PM PDT 24 645635035 ps
T557 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1291462297 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:17 PM PDT 24 204120156 ps
T558 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3503774268 Aug 16 05:41:06 PM PDT 24 Aug 16 05:41:07 PM PDT 24 15653203 ps
T559 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1918389922 Aug 16 05:41:25 PM PDT 24 Aug 16 05:41:26 PM PDT 24 117502586 ps
T94 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2817638672 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 122404846 ps
T60 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1227482532 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:21 PM PDT 24 226277082 ps
T120 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3865957675 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:17 PM PDT 24 128643602 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2110062324 Aug 16 05:41:40 PM PDT 24 Aug 16 05:42:13 PM PDT 24 4276226411 ps
T561 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3572409123 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:21 PM PDT 24 38529734 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3834769385 Aug 16 05:41:02 PM PDT 24 Aug 16 05:41:03 PM PDT 24 22856639 ps
T563 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3907800297 Aug 16 05:41:06 PM PDT 24 Aug 16 05:41:11 PM PDT 24 3247736470 ps
T564 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2492054129 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:18 PM PDT 24 39189128 ps
T565 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3966032264 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:11 PM PDT 24 70397955 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2264155561 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 35737309 ps
T566 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.988856789 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:12 PM PDT 24 21035113 ps
T567 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3922207965 Aug 16 05:41:09 PM PDT 24 Aug 16 05:41:10 PM PDT 24 34049090 ps
T568 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1808057326 Aug 16 05:41:45 PM PDT 24 Aug 16 05:41:46 PM PDT 24 389567577 ps
T569 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3987997847 Aug 16 05:41:41 PM PDT 24 Aug 16 05:41:42 PM PDT 24 39382163 ps
T570 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3788849592 Aug 16 05:41:13 PM PDT 24 Aug 16 05:58:28 PM PDT 24 97689314949 ps
T571 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.16348613 Aug 16 05:41:32 PM PDT 24 Aug 16 05:41:34 PM PDT 24 206895266 ps
T572 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1172811999 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:14 PM PDT 24 15837592 ps
T573 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3508845757 Aug 16 05:41:04 PM PDT 24 Aug 16 05:41:05 PM PDT 24 28585893 ps
T574 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4253002166 Aug 16 05:41:23 PM PDT 24 Aug 16 05:41:27 PM PDT 24 243471941 ps
T575 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2561635923 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:20 PM PDT 24 11614078 ps
T576 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.344899398 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:16 PM PDT 24 967092363 ps
T122 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.929175653 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:13 PM PDT 24 164444415 ps
T577 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2618042443 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:18 PM PDT 24 73315980 ps
T578 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3348758974 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:22 PM PDT 24 145898541 ps
T579 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2642993871 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:17 PM PDT 24 62718850 ps
T98 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2126088002 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:31 PM PDT 24 113196542 ps
T96 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.457266895 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:14 PM PDT 24 17673857 ps
T580 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3622094960 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:13 PM PDT 24 16992011 ps
T581 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4062104625 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:17 PM PDT 24 222311598 ps
T121 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1667987326 Aug 16 05:41:19 PM PDT 24 Aug 16 05:41:24 PM PDT 24 527533408 ps
T582 /workspace/coverage/cover_reg_top/9.hmac_intr_test.633900008 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 17012330 ps
T583 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4102736493 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:29 PM PDT 24 1581342380 ps
T97 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1094282766 Aug 16 05:41:33 PM PDT 24 Aug 16 05:41:34 PM PDT 24 19707070 ps
T584 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4006938515 Aug 16 05:41:21 PM PDT 24 Aug 16 05:41:23 PM PDT 24 45609846 ps
T585 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3424471621 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:17 PM PDT 24 49101664 ps
T586 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2463915074 Aug 16 05:41:52 PM PDT 24 Aug 16 05:41:55 PM PDT 24 66334727 ps
T587 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.16261744 Aug 16 05:41:07 PM PDT 24 Aug 16 05:41:11 PM PDT 24 102437351 ps
T119 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.161788913 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:13 PM PDT 24 386854843 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2260464197 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:22 PM PDT 24 96782914 ps
T589 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3948190352 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:14 PM PDT 24 272338850 ps
T590 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1478284954 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 41531385 ps
T591 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4260854593 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 29292806 ps
T99 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.780765743 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:15 PM PDT 24 68202676 ps
T592 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3597886005 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:17 PM PDT 24 261198441 ps
T593 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2757317887 Aug 16 05:41:08 PM PDT 24 Aug 16 05:41:22 PM PDT 24 143870753 ps
T594 /workspace/coverage/cover_reg_top/6.hmac_intr_test.4089226228 Aug 16 05:41:33 PM PDT 24 Aug 16 05:41:34 PM PDT 24 27695923 ps
T595 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1976720257 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:16 PM PDT 24 93827053 ps
T596 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.117300918 Aug 16 05:41:25 PM PDT 24 Aug 16 05:41:26 PM PDT 24 25866439 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3362301208 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:16 PM PDT 24 139373914 ps
T598 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.210499931 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:30 PM PDT 24 269645754 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3340811491 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:20 PM PDT 24 798411695 ps
T600 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2149318157 Aug 16 05:41:12 PM PDT 24 Aug 16 05:41:16 PM PDT 24 79473927 ps
T59 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1676681759 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:14 PM PDT 24 1155098249 ps
T601 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2465236944 Aug 16 05:41:32 PM PDT 24 Aug 16 05:41:32 PM PDT 24 34514840 ps
T602 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4038862115 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:27 PM PDT 24 20951197 ps
T603 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1278199328 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:18 PM PDT 24 184369477 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2032705384 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:21 PM PDT 24 1078470272 ps
T604 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1976160719 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:17 PM PDT 24 125875334 ps
T101 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.489085207 Aug 16 05:41:35 PM PDT 24 Aug 16 05:41:36 PM PDT 24 119346505 ps
T102 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3618377248 Aug 16 05:41:06 PM PDT 24 Aug 16 05:41:15 PM PDT 24 521250395 ps
T605 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3004122452 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:21 PM PDT 24 43046269 ps
T606 /workspace/coverage/cover_reg_top/31.hmac_intr_test.412199154 Aug 16 05:41:32 PM PDT 24 Aug 16 05:41:33 PM PDT 24 116056463 ps
T607 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1160224282 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:11 PM PDT 24 12271508 ps
T117 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3272524141 Aug 16 05:41:18 PM PDT 24 Aug 16 05:41:20 PM PDT 24 52377995 ps
T608 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4059923973 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:15 PM PDT 24 175687192 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4274877679 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:19 PM PDT 24 345964605 ps
T610 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3265391981 Aug 16 05:41:09 PM PDT 24 Aug 16 05:41:10 PM PDT 24 47007563 ps
T103 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2810878518 Aug 16 05:41:37 PM PDT 24 Aug 16 05:41:38 PM PDT 24 64862907 ps
T611 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1995127744 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:11 PM PDT 24 15493078 ps
T612 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2832971576 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:14 PM PDT 24 47744894 ps
T613 /workspace/coverage/cover_reg_top/34.hmac_intr_test.462736564 Aug 16 05:41:35 PM PDT 24 Aug 16 05:41:36 PM PDT 24 55345356 ps
T614 /workspace/coverage/cover_reg_top/19.hmac_intr_test.841309639 Aug 16 05:41:40 PM PDT 24 Aug 16 05:41:41 PM PDT 24 31225509 ps
T615 /workspace/coverage/cover_reg_top/41.hmac_intr_test.4117820074 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:13 PM PDT 24 17014431 ps
T616 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3693172390 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:12 PM PDT 24 26478323 ps
T617 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3727482457 Aug 16 05:41:09 PM PDT 24 Aug 16 05:41:11 PM PDT 24 120451815 ps
T618 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3601854766 Aug 16 05:41:21 PM PDT 24 Aug 16 05:41:25 PM PDT 24 791306599 ps
T619 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3997356884 Aug 16 05:41:06 PM PDT 24 Aug 16 05:41:07 PM PDT 24 52282706 ps
T620 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3108834537 Aug 16 05:41:23 PM PDT 24 Aug 16 05:41:25 PM PDT 24 473146439 ps
T621 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2515647374 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:17 PM PDT 24 175646606 ps
T622 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1575303311 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:11 PM PDT 24 30859850 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3636797080 Aug 16 05:41:13 PM PDT 24 Aug 16 05:41:14 PM PDT 24 19290557 ps
T624 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3379572925 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 26866255 ps
T625 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3855241974 Aug 16 05:41:10 PM PDT 24 Aug 16 05:41:10 PM PDT 24 13274449 ps
T626 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3801238595 Aug 16 05:41:10 PM PDT 24 Aug 16 05:56:31 PM PDT 24 243820869126 ps
T627 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.142486940 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:18 PM PDT 24 173032572 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2634668602 Aug 16 05:40:55 PM PDT 24 Aug 16 05:40:59 PM PDT 24 449953852 ps
T629 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3616223793 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:14 PM PDT 24 59224983 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2846530984 Aug 16 05:41:41 PM PDT 24 Aug 16 05:41:42 PM PDT 24 46255194 ps
T631 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2393829190 Aug 16 05:40:59 PM PDT 24 Aug 16 05:41:03 PM PDT 24 236214676 ps
T632 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2544256736 Aug 16 05:41:43 PM PDT 24 Aug 16 05:41:44 PM PDT 24 19081654 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3216798712 Aug 16 05:41:25 PM PDT 24 Aug 16 05:41:25 PM PDT 24 25827490 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2017502243 Aug 16 05:41:26 PM PDT 24 Aug 16 05:41:28 PM PDT 24 141889375 ps
T635 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1047563811 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:18 PM PDT 24 1186163055 ps
T636 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3506586602 Aug 16 05:41:18 PM PDT 24 Aug 16 05:41:19 PM PDT 24 155166138 ps
T637 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2688293680 Aug 16 05:41:20 PM PDT 24 Aug 16 05:41:31 PM PDT 24 14037390 ps
T638 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2605254370 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:17 PM PDT 24 13256032 ps
T639 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.578341055 Aug 16 05:41:06 PM PDT 24 Aug 16 05:41:07 PM PDT 24 104723199 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1703227909 Aug 16 05:41:11 PM PDT 24 Aug 16 05:41:20 PM PDT 24 212790542 ps
T641 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3482499381 Aug 16 05:41:48 PM PDT 24 Aug 16 05:41:51 PM PDT 24 12964377 ps
T642 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1017205870 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:16 PM PDT 24 354283899 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_intr_test.834389487 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 12330130 ps
T644 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1991015693 Aug 16 05:41:23 PM PDT 24 Aug 16 05:41:24 PM PDT 24 16953046 ps
T645 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3164097869 Aug 16 05:41:32 PM PDT 24 Aug 16 05:41:32 PM PDT 24 12300119 ps
T646 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2941604527 Aug 16 05:41:14 PM PDT 24 Aug 16 05:41:15 PM PDT 24 15411734 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.94096819 Aug 16 05:41:07 PM PDT 24 Aug 16 05:41:11 PM PDT 24 164705012 ps
T648 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1091780626 Aug 16 05:41:15 PM PDT 24 Aug 16 05:41:16 PM PDT 24 36177214 ps
T649 /workspace/coverage/cover_reg_top/33.hmac_intr_test.595089271 Aug 16 05:41:37 PM PDT 24 Aug 16 05:41:38 PM PDT 24 30460022 ps
T650 /workspace/coverage/cover_reg_top/17.hmac_intr_test.596108135 Aug 16 05:41:21 PM PDT 24 Aug 16 05:41:22 PM PDT 24 32366391 ps
T651 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2711709761 Aug 16 05:41:19 PM PDT 24 Aug 16 05:41:22 PM PDT 24 1112030037 ps
T652 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2907273911 Aug 16 05:41:16 PM PDT 24 Aug 16 05:41:22 PM PDT 24 15913017 ps
T653 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.579866380 Aug 16 05:41:17 PM PDT 24 Aug 16 05:41:20 PM PDT 24 626099796 ps
T654 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1006784268 Aug 16 05:41:12 PM PDT 24 Aug 16 05:58:39 PM PDT 24 122618021424 ps

Test location /workspace/coverage/default/14.hmac_stress_all.2099862719
Short name T8
Test name
Test status
Simulation time 49226797645 ps
CPU time 528 seconds
Started Aug 16 06:30:17 PM PDT 24
Finished Aug 16 06:39:05 PM PDT 24
Peak memory 200736 kb
Host smart-53cf9a7d-1fa0-4a74-9ffb-318cafbf0b86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099862719 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2099862719
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.283321306
Short name T3
Test name
Test status
Simulation time 9538655699 ps
CPU time 342.38 seconds
Started Aug 16 06:31:22 PM PDT 24
Finished Aug 16 06:37:05 PM PDT 24
Peak memory 658572 kb
Host smart-b27e7541-63b1-4b89-aa03-79148847059a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283321306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.283321306
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3629466676
Short name T10
Test name
Test status
Simulation time 8137728596 ps
CPU time 570.7 seconds
Started Aug 16 06:30:03 PM PDT 24
Finished Aug 16 06:39:34 PM PDT 24
Peak memory 467388 kb
Host smart-b309b956-efe5-498a-8f36-67fad153b447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3629466676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3629466676
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2862063467
Short name T12
Test name
Test status
Simulation time 30477712388 ps
CPU time 1143.11 seconds
Started Aug 16 06:31:17 PM PDT 24
Finished Aug 16 06:50:20 PM PDT 24
Peak memory 737660 kb
Host smart-cfe7cba6-12b2-4dc7-93f9-f9f36b4db9b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862063467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2862063467
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.627401334
Short name T57
Test name
Test status
Simulation time 324990597 ps
CPU time 2.99 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 199880 kb
Host smart-fc3e9071-46d5-4f56-b5ff-36b3829923c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627401334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.627401334
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1207769630
Short name T9
Test name
Test status
Simulation time 6920564113 ps
CPU time 64.45 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:31:05 PM PDT 24
Peak memory 217164 kb
Host smart-e4918972-bb6c-4b38-8d9b-46aefc296567
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1207769630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1207769630
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3817424042
Short name T35
Test name
Test status
Simulation time 91212833 ps
CPU time 0.9 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:29:36 PM PDT 24
Peak memory 219976 kb
Host smart-2723ac01-d066-4972-b27f-2c471311d9d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817424042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3817424042
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3673753645
Short name T90
Test name
Test status
Simulation time 270340802 ps
CPU time 0.9 seconds
Started Aug 16 05:40:58 PM PDT 24
Finished Aug 16 05:40:59 PM PDT 24
Peak memory 200080 kb
Host smart-419d77b5-a6bd-47b7-9dff-00641535c3b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673753645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3673753645
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2720640430
Short name T139
Test name
Test status
Simulation time 15666700760 ps
CPU time 882.29 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:46:36 PM PDT 24
Peak memory 208944 kb
Host smart-df8d5092-3311-4580-8e51-0e25c35e9066
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720640430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2720640430
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all.167253387
Short name T20
Test name
Test status
Simulation time 115130215517 ps
CPU time 1777.96 seconds
Started Aug 16 06:32:02 PM PDT 24
Finished Aug 16 07:01:40 PM PDT 24
Peak memory 525828 kb
Host smart-cf2496c8-b34e-4c8b-973d-cf35c67370bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167253387 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.167253387
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.275176294
Short name T56
Test name
Test status
Simulation time 52694204 ps
CPU time 1.72 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 200216 kb
Host smart-a45a8173-6ad9-464f-aa34-93b18368cb60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275176294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.275176294
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_long_msg.432039359
Short name T128
Test name
Test status
Simulation time 3419154697 ps
CPU time 210.68 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:33:45 PM PDT 24
Peak memory 200856 kb
Host smart-96abffb5-47b7-4093-9d64-8ad920b66b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432039359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.432039359
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3702700265
Short name T53
Test name
Test status
Simulation time 12737232 ps
CPU time 0.58 seconds
Started Aug 16 06:30:13 PM PDT 24
Finished Aug 16 06:30:14 PM PDT 24
Peak memory 196716 kb
Host smart-b2b5f592-bea5-449e-b67d-865714381a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702700265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3702700265
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4274877679
Short name T609
Test name
Test status
Simulation time 345964605 ps
CPU time 2.76 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 200184 kb
Host smart-e3a0b6c9-23f8-49d4-a65f-d2b7ebd815b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274877679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4274877679
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3092745298
Short name T175
Test name
Test status
Simulation time 150855195073 ps
CPU time 2097.92 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 07:04:37 PM PDT 24
Peak memory 216160 kb
Host smart-657abd00-0702-4ec4-adb6-653604754b01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3092745298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3092745298
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1227482532
Short name T60
Test name
Test status
Simulation time 226277082 ps
CPU time 4.4 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 200300 kb
Host smart-b63b8677-b3e0-4327-aa50-46dde622618d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227482532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1227482532
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1676681759
Short name T59
Test name
Test status
Simulation time 1155098249 ps
CPU time 4.47 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 200304 kb
Host smart-90578c4b-a3aa-486d-93b6-c44af778784d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676681759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1676681759
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3202456514
Short name T16
Test name
Test status
Simulation time 24762878482 ps
CPU time 344.45 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:35:20 PM PDT 24
Peak memory 607472 kb
Host smart-c41786b0-f017-4c88-94a4-66e2fec4c979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202456514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3202456514
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2957251212
Short name T137
Test name
Test status
Simulation time 69658801426 ps
CPU time 1707.55 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:58:38 PM PDT 24
Peak memory 683068 kb
Host smart-ac43dfef-f568-4e4d-9a8e-58d1cde9fede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957251212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2957251212
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3618377248
Short name T102
Test name
Test status
Simulation time 521250395 ps
CPU time 8.57 seconds
Started Aug 16 05:41:06 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 200188 kb
Host smart-bd523dfb-a1a1-4813-8964-b888edce5e8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618377248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3618377248
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3971595762
Short name T534
Test name
Test status
Simulation time 1158870808 ps
CPU time 9.41 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 199388 kb
Host smart-903a6668-3249-495b-8582-13618d0a7e19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971595762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3971595762
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1902167655
Short name T93
Test name
Test status
Simulation time 23523004 ps
CPU time 0.7 seconds
Started Aug 16 05:41:05 PM PDT 24
Finished Aug 16 05:41:06 PM PDT 24
Peak memory 198164 kb
Host smart-6c947925-0e80-4ac9-a371-c63f2a255a70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902167655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1902167655
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1006784268
Short name T654
Test name
Test status
Simulation time 122618021424 ps
CPU time 1046.52 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:58:39 PM PDT 24
Peak memory 224980 kb
Host smart-02261868-5b8a-49e3-8b06-ca6ca5101790
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006784268 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1006784268
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3503774268
Short name T558
Test name
Test status
Simulation time 15653203 ps
CPU time 0.7 seconds
Started Aug 16 05:41:06 PM PDT 24
Finished Aug 16 05:41:07 PM PDT 24
Peak memory 197868 kb
Host smart-cdd4e287-7c3c-426b-9c9a-63e1e80590e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503774268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3503774268
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3508845757
Short name T573
Test name
Test status
Simulation time 28585893 ps
CPU time 0.6 seconds
Started Aug 16 05:41:04 PM PDT 24
Finished Aug 16 05:41:05 PM PDT 24
Peak memory 195272 kb
Host smart-f20b993f-bf73-4e5b-9d4b-b4a16da23826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508845757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3508845757
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3834769385
Short name T562
Test name
Test status
Simulation time 22856639 ps
CPU time 1.03 seconds
Started Aug 16 05:41:02 PM PDT 24
Finished Aug 16 05:41:03 PM PDT 24
Peak memory 199984 kb
Host smart-6f995e33-7842-461d-b7c1-d88d2b776ee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834769385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3834769385
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.67747201
Short name T552
Test name
Test status
Simulation time 787694011 ps
CPU time 4.11 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 200284 kb
Host smart-6705f3c8-2bbe-452a-be61-4474380b43ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67747201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.67747201
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3141389669
Short name T92
Test name
Test status
Simulation time 1400828987 ps
CPU time 5.93 seconds
Started Aug 16 05:41:01 PM PDT 24
Finished Aug 16 05:41:07 PM PDT 24
Peak memory 200072 kb
Host smart-5d54ee94-ef53-4ac3-a5ed-32c770535750
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141389669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3141389669
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3410852204
Short name T91
Test name
Test status
Simulation time 18225878863 ps
CPU time 10.62 seconds
Started Aug 16 05:41:07 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200360 kb
Host smart-529ff538-27d9-4e7d-a95a-69f06fff3cc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410852204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3410852204
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.988856789
Short name T566
Test name
Test status
Simulation time 21035113 ps
CPU time 0.83 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 199496 kb
Host smart-ace1831e-9e19-42f6-bc68-63ecfd7884a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988856789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.988856789
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3801238595
Short name T626
Test name
Test status
Simulation time 243820869126 ps
CPU time 921.03 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:56:31 PM PDT 24
Peak memory 216760 kb
Host smart-faffc005-e429-4f6e-8671-0a40fa475c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801238595 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3801238595
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.457266895
Short name T96
Test name
Test status
Simulation time 17673857 ps
CPU time 0.73 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 198764 kb
Host smart-8f91d6ff-f4c6-43d6-8f0a-1a9fd145c60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457266895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.457266895
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3216798712
Short name T633
Test name
Test status
Simulation time 25827490 ps
CPU time 0.54 seconds
Started Aug 16 05:41:25 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 195296 kb
Host smart-fe037682-d1b2-43e8-b06b-0724a1cbdfac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216798712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3216798712
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2492054129
Short name T564
Test name
Test status
Simulation time 39189128 ps
CPU time 1.06 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 199860 kb
Host smart-3da7b801-4339-424a-b9df-e8f2539b2de7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492054129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2492054129
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3579795299
Short name T532
Test name
Test status
Simulation time 706681484 ps
CPU time 3.34 seconds
Started Aug 16 05:40:53 PM PDT 24
Finished Aug 16 05:40:57 PM PDT 24
Peak memory 200268 kb
Host smart-031bb482-e964-43cc-b7e4-b593d7a4167f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579795299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3579795299
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2634668602
Short name T628
Test name
Test status
Simulation time 449953852 ps
CPU time 4.03 seconds
Started Aug 16 05:40:55 PM PDT 24
Finished Aug 16 05:40:59 PM PDT 24
Peak memory 200100 kb
Host smart-2d25b2b5-851f-4b3e-a8c2-f007dc16aef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634668602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2634668602
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2149318157
Short name T600
Test name
Test status
Simulation time 79473927 ps
CPU time 2.54 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 208424 kb
Host smart-6db59cbb-112c-42af-9bdc-f4a82c659b97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149318157 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2149318157
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2941604527
Short name T646
Test name
Test status
Simulation time 15411734 ps
CPU time 0.8 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 200036 kb
Host smart-beee912b-8c9d-4137-a884-ae3348de227d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941604527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2941604527
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4260854593
Short name T591
Test name
Test status
Simulation time 29292806 ps
CPU time 0.58 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 195216 kb
Host smart-a2838338-e677-4fcb-9450-44a5f2f0eb40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260854593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4260854593
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3868600964
Short name T108
Test name
Test status
Simulation time 62953878 ps
CPU time 1.24 seconds
Started Aug 16 05:41:23 PM PDT 24
Finished Aug 16 05:41:24 PM PDT 24
Peak memory 200176 kb
Host smart-e9557a85-78af-4fd2-ab6b-cacf8dce7c71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868600964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3868600964
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.210499931
Short name T598
Test name
Test status
Simulation time 269645754 ps
CPU time 3.49 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:30 PM PDT 24
Peak memory 200328 kb
Host smart-5386378a-0df2-4f25-9dc0-4333ae30be1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210499931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.210499931
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1808057326
Short name T568
Test name
Test status
Simulation time 389567577 ps
CPU time 1.79 seconds
Started Aug 16 05:41:45 PM PDT 24
Finished Aug 16 05:41:46 PM PDT 24
Peak memory 200268 kb
Host smart-b17d4ccd-d7fa-4721-8f64-8f470bfaf459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808057326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1808057326
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.219918973
Short name T61
Test name
Test status
Simulation time 210688635 ps
CPU time 2.38 seconds
Started Aug 16 05:41:09 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 200228 kb
Host smart-2d5c2e1f-78f8-47a0-922a-895fe5bcf570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219918973 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.219918973
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3966032264
Short name T565
Test name
Test status
Simulation time 70397955 ps
CPU time 0.68 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 198208 kb
Host smart-b577fb09-656b-4b74-9b62-9efa0713fcba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966032264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3966032264
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3693172390
Short name T616
Test name
Test status
Simulation time 26478323 ps
CPU time 0.6 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 195308 kb
Host smart-c42d6380-a8c1-4e14-af91-1d81e5ba8d6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693172390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3693172390
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.126933078
Short name T107
Test name
Test status
Simulation time 87644180 ps
CPU time 2.2 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 200328 kb
Host smart-62cb4bbb-a0fa-4b3a-ab1f-831c98aeecf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126933078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.126933078
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.344899398
Short name T576
Test name
Test status
Simulation time 967092363 ps
CPU time 2.84 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200260 kb
Host smart-a6d522fc-e627-4853-8d06-c712c8c4a461
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344899398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.344899398
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.929175653
Short name T122
Test name
Test status
Simulation time 164444415 ps
CPU time 1.79 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 200248 kb
Host smart-9ee2cd74-0e8e-49e0-8c52-e325ec34b883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929175653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.929175653
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2110062324
Short name T560
Test name
Test status
Simulation time 4276226411 ps
CPU time 33.27 seconds
Started Aug 16 05:41:40 PM PDT 24
Finished Aug 16 05:42:13 PM PDT 24
Peak memory 216260 kb
Host smart-c3d45e86-8e92-429d-b98f-2367958f3142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110062324 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2110062324
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2817638672
Short name T94
Test name
Test status
Simulation time 122404846 ps
CPU time 0.89 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 199868 kb
Host smart-cfc260e8-23ec-4f0e-8e6f-b1392e297b8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817638672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2817638672
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1478284954
Short name T590
Test name
Test status
Simulation time 41531385 ps
CPU time 0.59 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 195308 kb
Host smart-7b85a825-bdb0-444d-82e5-0b191be840ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478284954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1478284954
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2642993871
Short name T579
Test name
Test status
Simulation time 62718850 ps
CPU time 1.19 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200128 kb
Host smart-7040754d-eb8c-46c8-b31c-6f0cca625d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642993871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2642993871
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.8719938
Short name T63
Test name
Test status
Simulation time 536746418 ps
CPU time 1.91 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200252 kb
Host smart-949a5129-a956-4db9-9a12-e811dce3086a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8719938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.8719938
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.161788913
Short name T119
Test name
Test status
Simulation time 386854843 ps
CPU time 1.89 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 200256 kb
Host smart-5df16b44-77bd-433d-97ca-eeffe6171cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161788913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.161788913
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2260464197
Short name T588
Test name
Test status
Simulation time 96782914 ps
CPU time 1.27 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 200260 kb
Host smart-72aec342-b8bb-4a65-aae2-c4f2e5996d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260464197 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2260464197
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.489085207
Short name T101
Test name
Test status
Simulation time 119346505 ps
CPU time 0.93 seconds
Started Aug 16 05:41:35 PM PDT 24
Finished Aug 16 05:41:36 PM PDT 24
Peak memory 200076 kb
Host smart-576f9159-f6c3-44cf-806a-edc6874dcbf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489085207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.489085207
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1172811999
Short name T572
Test name
Test status
Simulation time 15837592 ps
CPU time 0.59 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 195232 kb
Host smart-2b022f63-0aad-4922-aedc-08e724109da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172811999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1172811999
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3265391981
Short name T610
Test name
Test status
Simulation time 47007563 ps
CPU time 1.11 seconds
Started Aug 16 05:41:09 PM PDT 24
Finished Aug 16 05:41:10 PM PDT 24
Peak memory 200256 kb
Host smart-26b14af0-21d4-4ce9-a386-d4b8bdb0d5f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265391981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3265391981
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2463915074
Short name T586
Test name
Test status
Simulation time 66334727 ps
CPU time 3.34 seconds
Started Aug 16 05:41:52 PM PDT 24
Finished Aug 16 05:41:55 PM PDT 24
Peak memory 200252 kb
Host smart-fba775a2-9df7-4e81-9ec8-47cdd0020334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463915074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2463915074
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1371765535
Short name T118
Test name
Test status
Simulation time 96640037 ps
CPU time 1.83 seconds
Started Aug 16 05:41:09 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 200344 kb
Host smart-bfd2b0c0-5f14-4279-9a24-dca65b1e9c27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371765535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1371765535
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1017205870
Short name T642
Test name
Test status
Simulation time 354283899 ps
CPU time 2 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200016 kb
Host smart-37decfc1-2b35-4386-8be2-032aa5b1bdc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017205870 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1017205870
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2569852550
Short name T112
Test name
Test status
Simulation time 23502910 ps
CPU time 0.83 seconds
Started Aug 16 05:41:08 PM PDT 24
Finished Aug 16 05:41:09 PM PDT 24
Peak memory 200100 kb
Host smart-5ff81905-0396-452d-bedf-392625dbe157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569852550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2569852550
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1918389922
Short name T559
Test name
Test status
Simulation time 117502586 ps
CPU time 0.6 seconds
Started Aug 16 05:41:25 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 195312 kb
Host smart-5fdaba11-519e-42dd-856c-4fa736a11b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918389922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1918389922
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3233692389
Short name T105
Test name
Test status
Simulation time 372587860 ps
CPU time 1.69 seconds
Started Aug 16 05:41:08 PM PDT 24
Finished Aug 16 05:41:10 PM PDT 24
Peak memory 200216 kb
Host smart-c7fe68b1-3fb4-4bcb-a0a5-916e58dbd31f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233692389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3233692389
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1047563811
Short name T635
Test name
Test status
Simulation time 1186163055 ps
CPU time 3.88 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200332 kb
Host smart-c4b024b6-478a-4024-b23f-fca1f5e707bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047563811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1047563811
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.4104646314
Short name T554
Test name
Test status
Simulation time 323003107 ps
CPU time 1.09 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 200056 kb
Host smart-b1d654d8-37b3-427d-9475-ecc1c91644ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104646314 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.4104646314
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1094282766
Short name T97
Test name
Test status
Simulation time 19707070 ps
CPU time 0.92 seconds
Started Aug 16 05:41:33 PM PDT 24
Finished Aug 16 05:41:34 PM PDT 24
Peak memory 200052 kb
Host smart-2558d313-398a-4f0f-bf07-270d16a04300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094282766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1094282766
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3622094960
Short name T580
Test name
Test status
Simulation time 16992011 ps
CPU time 0.6 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 195332 kb
Host smart-e85a2f2e-4f55-4501-9711-d18cb51d38cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622094960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3622094960
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3136310291
Short name T104
Test name
Test status
Simulation time 167083433 ps
CPU time 1.07 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 200144 kb
Host smart-4e73c076-5ded-4eda-ab16-4b7403780f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136310291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3136310291
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2757317887
Short name T593
Test name
Test status
Simulation time 143870753 ps
CPU time 3.55 seconds
Started Aug 16 05:41:08 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 200328 kb
Host smart-19b06b58-f3e1-47d8-b7be-9dc11a01bb39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757317887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2757317887
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2711709761
Short name T651
Test name
Test status
Simulation time 1112030037 ps
CPU time 3.05 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 200272 kb
Host smart-2ac252e4-3d2c-415f-8356-2829e7db2055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711709761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2711709761
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.142486940
Short name T627
Test name
Test status
Simulation time 173032572 ps
CPU time 1.66 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200252 kb
Host smart-eaab2095-a9d6-467b-80e0-8bd22175bdba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142486940 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.142486940
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2810878518
Short name T103
Test name
Test status
Simulation time 64862907 ps
CPU time 0.89 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:41:38 PM PDT 24
Peak memory 200044 kb
Host smart-1b995876-03e6-4bc0-8d02-b18de9eb3d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810878518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2810878518
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1575303311
Short name T622
Test name
Test status
Simulation time 30859850 ps
CPU time 0.56 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 195208 kb
Host smart-c3d4f365-0d82-408f-be76-1421601c6a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575303311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1575303311
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2017502243
Short name T634
Test name
Test status
Simulation time 141889375 ps
CPU time 2.04 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 200252 kb
Host smart-99677e2f-37d2-4529-863f-c3b6dbfb1ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017502243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2017502243
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2618042443
Short name T577
Test name
Test status
Simulation time 73315980 ps
CPU time 1.76 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200280 kb
Host smart-0c2c6d22-7f55-461d-b7e3-b1d936e66763
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618042443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2618042443
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.16348613
Short name T571
Test name
Test status
Simulation time 206895266 ps
CPU time 1.63 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:41:34 PM PDT 24
Peak memory 200360 kb
Host smart-81e54314-5d55-423d-9301-36de1ee71476
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16348613 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.16348613
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2544256736
Short name T632
Test name
Test status
Simulation time 19081654 ps
CPU time 0.69 seconds
Started Aug 16 05:41:43 PM PDT 24
Finished Aug 16 05:41:44 PM PDT 24
Peak memory 198232 kb
Host smart-3637d7ca-c361-4244-9402-bf3f8046fea6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544256736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2544256736
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.596108135
Short name T650
Test name
Test status
Simulation time 32366391 ps
CPU time 0.58 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 195384 kb
Host smart-89ffff32-5aca-48d2-a034-91058831cff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596108135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.596108135
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4245919749
Short name T106
Test name
Test status
Simulation time 147559119 ps
CPU time 1.75 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 200220 kb
Host smart-bb7b29d0-d5a8-4c76-955b-20fbc9de5310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245919749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4245919749
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3907800297
Short name T563
Test name
Test status
Simulation time 3247736470 ps
CPU time 4.53 seconds
Started Aug 16 05:41:06 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 200420 kb
Host smart-bc09af26-79f2-4ee6-8c05-826c8113634c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907800297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3907800297
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1667987326
Short name T121
Test name
Test status
Simulation time 527533408 ps
CPU time 3.97 seconds
Started Aug 16 05:41:19 PM PDT 24
Finished Aug 16 05:41:24 PM PDT 24
Peak memory 200196 kb
Host smart-951b72f6-c8f2-4c72-9636-78804a996cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667987326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1667987326
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3424471621
Short name T585
Test name
Test status
Simulation time 49101664 ps
CPU time 1.28 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200256 kb
Host smart-171feee3-db70-4a82-a6cc-b5c6497621d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424471621 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3424471621
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3997356884
Short name T619
Test name
Test status
Simulation time 52282706 ps
CPU time 0.72 seconds
Started Aug 16 05:41:06 PM PDT 24
Finished Aug 16 05:41:07 PM PDT 24
Peak memory 198320 kb
Host smart-f335d1d9-9ced-4c15-8cd9-08e3db98f335
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997356884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3997356884
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.162856352
Short name T535
Test name
Test status
Simulation time 13645534 ps
CPU time 0.58 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 195396 kb
Host smart-2393191a-1dc0-4f09-84f3-aef20a323666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162856352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.162856352
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.236220106
Short name T546
Test name
Test status
Simulation time 231735096 ps
CPU time 2.31 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 200204 kb
Host smart-6b4df157-c70e-4204-8944-0c13f3b2688a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236220106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.236220106
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3662094419
Short name T539
Test name
Test status
Simulation time 87009339 ps
CPU time 4.17 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 200208 kb
Host smart-b2e3898e-c18b-47b0-b30d-1c849dfb1583
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662094419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3662094419
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2659711001
Short name T58
Test name
Test status
Simulation time 97933572 ps
CPU time 1.81 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200236 kb
Host smart-f74e1ee5-1eaa-42b0-b899-c282fca507c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659711001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2659711001
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3572409123
Short name T561
Test name
Test status
Simulation time 38529734 ps
CPU time 1.25 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 200316 kb
Host smart-3a3dbc6a-eb0a-4fa9-95e0-ce9458eb72a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572409123 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3572409123
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.780765743
Short name T99
Test name
Test status
Simulation time 68202676 ps
CPU time 0.69 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 198232 kb
Host smart-c46cf78f-a54d-42b5-978d-37da977aab87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780765743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.780765743
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.841309639
Short name T614
Test name
Test status
Simulation time 31225509 ps
CPU time 0.62 seconds
Started Aug 16 05:41:40 PM PDT 24
Finished Aug 16 05:41:41 PM PDT 24
Peak memory 195368 kb
Host smart-5c11e38e-fba8-49ad-bdb2-408effa64827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841309639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.841309639
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3348758974
Short name T578
Test name
Test status
Simulation time 145898541 ps
CPU time 1.04 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 200224 kb
Host smart-33b41a61-2cb2-440c-bbb9-37b5ee35dc98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348758974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3348758974
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3340811491
Short name T599
Test name
Test status
Simulation time 798411695 ps
CPU time 3.66 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 200260 kb
Host smart-43043350-4b2e-43ca-a79e-6b4955eb58a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340811491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3340811491
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4253002166
Short name T574
Test name
Test status
Simulation time 243471941 ps
CPU time 3.82 seconds
Started Aug 16 05:41:23 PM PDT 24
Finished Aug 16 05:41:27 PM PDT 24
Peak memory 200212 kb
Host smart-f8058582-c11c-44be-8ab7-e6abd9825f32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253002166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4253002166
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2032705384
Short name T100
Test name
Test status
Simulation time 1078470272 ps
CPU time 6.33 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 200200 kb
Host smart-31bf9247-50a1-459d-b49f-f020fa1a9853
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032705384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2032705384
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4102736493
Short name T583
Test name
Test status
Simulation time 1581342380 ps
CPU time 16.44 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 200248 kb
Host smart-a241b652-f8e6-4746-bfe3-0b2b7ad15ecf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102736493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4102736493
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2264155561
Short name T95
Test name
Test status
Simulation time 35737309 ps
CPU time 0.93 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 199732 kb
Host smart-d8a272fc-95f0-46f6-988c-aebbd150408d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264155561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2264155561
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3983406635
Short name T84
Test name
Test status
Simulation time 515153597 ps
CPU time 1.57 seconds
Started Aug 16 05:41:07 PM PDT 24
Finished Aug 16 05:41:08 PM PDT 24
Peak memory 200336 kb
Host smart-f65d6579-313e-4b26-a7c0-88216c88dcf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983406635 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3983406635
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3636797080
Short name T623
Test name
Test status
Simulation time 19290557 ps
CPU time 0.7 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 198308 kb
Host smart-b052a195-ce88-4e4b-aeb1-e45de0f050b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636797080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3636797080
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2688293680
Short name T637
Test name
Test status
Simulation time 14037390 ps
CPU time 0.58 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:31 PM PDT 24
Peak memory 195160 kb
Host smart-60f269ac-2fd1-4ef1-84ef-aafc50f7bc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688293680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2688293680
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3379572925
Short name T624
Test name
Test status
Simulation time 26866255 ps
CPU time 1.2 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200240 kb
Host smart-6a0fa1ac-f077-4033-b110-91da6d5e2806
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379572925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3379572925
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3362301208
Short name T597
Test name
Test status
Simulation time 139373914 ps
CPU time 1.61 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200180 kb
Host smart-f8f188f9-51e8-4607-b3c3-323f8ba60010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362301208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3362301208
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3272524141
Short name T117
Test name
Test status
Simulation time 52377995 ps
CPU time 1.66 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 200248 kb
Host smart-92bd3ed6-dec5-41af-95e4-2fd5728e1951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272524141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3272524141
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2561635923
Short name T575
Test name
Test status
Simulation time 11614078 ps
CPU time 0.58 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 195264 kb
Host smart-77ce2f4a-c05c-4768-bad6-17cb751d7946
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561635923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2561635923
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3922207965
Short name T567
Test name
Test status
Simulation time 34049090 ps
CPU time 0.56 seconds
Started Aug 16 05:41:09 PM PDT 24
Finished Aug 16 05:41:10 PM PDT 24
Peak memory 195220 kb
Host smart-e68095d1-f59c-431b-859a-ee822b1d82ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922207965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3922207965
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3164097869
Short name T645
Test name
Test status
Simulation time 12300119 ps
CPU time 0.57 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:41:32 PM PDT 24
Peak memory 195328 kb
Host smart-09e2a9a0-ea1e-4d69-a33c-8b27396fee3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164097869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3164097869
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1160224282
Short name T607
Test name
Test status
Simulation time 12271508 ps
CPU time 0.58 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 195296 kb
Host smart-473faf14-06f6-42a1-bbfa-be3aeae41368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160224282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1160224282
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1091780626
Short name T648
Test name
Test status
Simulation time 36177214 ps
CPU time 0.56 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 195192 kb
Host smart-1dd1f21a-46c6-44e2-bba9-50fef5f2fbd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091780626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1091780626
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2832971576
Short name T612
Test name
Test status
Simulation time 47744894 ps
CPU time 0.61 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 195312 kb
Host smart-514507ad-98d1-4f79-b231-f0aa96c0e317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832971576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2832971576
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1995127744
Short name T611
Test name
Test status
Simulation time 15493078 ps
CPU time 0.61 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 195416 kb
Host smart-fe80204c-74d1-4066-a0b8-684196720f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995127744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1995127744
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1991015693
Short name T644
Test name
Test status
Simulation time 16953046 ps
CPU time 0.59 seconds
Started Aug 16 05:41:23 PM PDT 24
Finished Aug 16 05:41:24 PM PDT 24
Peak memory 195300 kb
Host smart-41e053e6-a8b4-4755-be17-d1ad8b91ba65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991015693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1991015693
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3124127194
Short name T550
Test name
Test status
Simulation time 33195450 ps
CPU time 0.55 seconds
Started Aug 16 05:41:46 PM PDT 24
Finished Aug 16 05:41:46 PM PDT 24
Peak memory 195240 kb
Host smart-a0d1534c-cbd7-4b39-ba16-d6a67f9d8225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124127194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3124127194
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3369168886
Short name T531
Test name
Test status
Simulation time 149159665 ps
CPU time 0.59 seconds
Started Aug 16 05:41:36 PM PDT 24
Finished Aug 16 05:41:37 PM PDT 24
Peak memory 195288 kb
Host smart-02e0d133-b84c-4c22-8c11-5f19165c23b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369168886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3369168886
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1632651680
Short name T88
Test name
Test status
Simulation time 4605540942 ps
CPU time 9.04 seconds
Started Aug 16 05:41:00 PM PDT 24
Finished Aug 16 05:41:09 PM PDT 24
Peak memory 200328 kb
Host smart-0ad1c3c6-9593-4dbe-a89b-c3ebbd616586
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632651680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1632651680
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2126088002
Short name T98
Test name
Test status
Simulation time 113196542 ps
CPU time 5.06 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:31 PM PDT 24
Peak memory 200260 kb
Host smart-7d1472f1-ce81-4f27-a9da-e6ec4601bfd8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126088002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2126088002
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.2598220769
Short name T89
Test name
Test status
Simulation time 19443308 ps
CPU time 0.82 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 199468 kb
Host smart-3a718926-9020-45f3-9b85-70958034b642
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598220769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.2598220769
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1983645586
Short name T555
Test name
Test status
Simulation time 37017803 ps
CPU time 1.19 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 200128 kb
Host smart-58d68c51-5fb6-4a2e-860b-7c4365a7ba9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983645586 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1983645586
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.18108731
Short name T549
Test name
Test status
Simulation time 11286699 ps
CPU time 0.55 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 195168 kb
Host smart-850a82bc-56ae-4ed0-9331-c2eb89ca10f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18108731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.18108731
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4059923973
Short name T608
Test name
Test status
Simulation time 175687192 ps
CPU time 2.21 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 200312 kb
Host smart-2c8668d9-5465-43ea-bc6c-737008058f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059923973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4059923973
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1691347699
Short name T62
Test name
Test status
Simulation time 46705449 ps
CPU time 1.57 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 200240 kb
Host smart-1fd6e9ea-42b6-4d50-8962-501b229c2306
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691347699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1691347699
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.579866380
Short name T653
Test name
Test status
Simulation time 626099796 ps
CPU time 3.15 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 200196 kb
Host smart-e0666b07-aa7d-4506-a75e-f3b0512bc731
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579866380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.579866380
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4038862115
Short name T602
Test name
Test status
Simulation time 20951197 ps
CPU time 0.58 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:27 PM PDT 24
Peak memory 195248 kb
Host smart-7926c7b6-7f09-48a6-bf4a-d2f49e89aa82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038862115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4038862115
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.412199154
Short name T606
Test name
Test status
Simulation time 116056463 ps
CPU time 0.58 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:41:33 PM PDT 24
Peak memory 195304 kb
Host smart-a03455d0-26e8-417d-b653-c481cd85bd97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412199154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.412199154
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3948190352
Short name T589
Test name
Test status
Simulation time 272338850 ps
CPU time 0.61 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 195220 kb
Host smart-f48b8e5a-dbb2-446b-87c2-010ba0f443e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948190352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3948190352
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.595089271
Short name T649
Test name
Test status
Simulation time 30460022 ps
CPU time 0.56 seconds
Started Aug 16 05:41:37 PM PDT 24
Finished Aug 16 05:41:38 PM PDT 24
Peak memory 195308 kb
Host smart-55473a87-ee73-4c8e-8d7c-645c102ec49b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595089271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.595089271
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.462736564
Short name T613
Test name
Test status
Simulation time 55345356 ps
CPU time 0.68 seconds
Started Aug 16 05:41:35 PM PDT 24
Finished Aug 16 05:41:36 PM PDT 24
Peak memory 195280 kb
Host smart-a368afcd-f166-47af-89cc-46f271607486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462736564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.462736564
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.231476900
Short name T538
Test name
Test status
Simulation time 16075271 ps
CPU time 0.58 seconds
Started Aug 16 05:41:56 PM PDT 24
Finished Aug 16 05:41:57 PM PDT 24
Peak memory 195328 kb
Host smart-8f492e28-77c9-49b9-b678-8fd838324a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231476900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.231476900
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4222436827
Short name T547
Test name
Test status
Simulation time 14589050 ps
CPU time 0.58 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 195232 kb
Host smart-1f441298-f997-41d7-a894-d10913cebb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222436827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4222436827
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3078250859
Short name T544
Test name
Test status
Simulation time 30400296 ps
CPU time 0.63 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 195272 kb
Host smart-9a15a319-ad14-40d1-af45-549caeac545f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078250859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3078250859
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3004122452
Short name T605
Test name
Test status
Simulation time 43046269 ps
CPU time 0.59 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 195144 kb
Host smart-fc1011cf-91d8-462b-a0a6-719feab0d735
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004122452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3004122452
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.2428238647
Short name T545
Test name
Test status
Simulation time 36892982 ps
CPU time 0.58 seconds
Started Aug 16 05:41:17 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 195340 kb
Host smart-32aa0965-e908-44ec-a999-3f812ddf08dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428238647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.2428238647
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.94096819
Short name T647
Test name
Test status
Simulation time 164705012 ps
CPU time 3.34 seconds
Started Aug 16 05:41:07 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 200228 kb
Host smart-f36ff305-28f8-4b5a-9c80-af09b975cb94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94096819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.94096819
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1703227909
Short name T640
Test name
Test status
Simulation time 212790542 ps
CPU time 9.61 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:20 PM PDT 24
Peak memory 200324 kb
Host smart-25d21235-57fe-4c26-b644-8bd023b98fb2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703227909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1703227909
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1215366534
Short name T542
Test name
Test status
Simulation time 83535251 ps
CPU time 0.73 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 198324 kb
Host smart-b95a6491-36a8-4ce8-8965-797fae97ba3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215366534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1215366534
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.16261744
Short name T587
Test name
Test status
Simulation time 102437351 ps
CPU time 3.62 seconds
Started Aug 16 05:41:07 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 216108 kb
Host smart-e81add7e-c59f-4a2d-9d73-11e13d29f08d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16261744 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.16261744
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.578341055
Short name T639
Test name
Test status
Simulation time 104723199 ps
CPU time 0.84 seconds
Started Aug 16 05:41:06 PM PDT 24
Finished Aug 16 05:41:07 PM PDT 24
Peak memory 200044 kb
Host smart-d71c2595-ba76-40af-a921-438cca03f5f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578341055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.578341055
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3855241974
Short name T625
Test name
Test status
Simulation time 13274449 ps
CPU time 0.56 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:10 PM PDT 24
Peak memory 195140 kb
Host smart-0774acb6-eda1-422b-a25f-c8f19744e51e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855241974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3855241974
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3616223793
Short name T629
Test name
Test status
Simulation time 59224983 ps
CPU time 1.18 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 200108 kb
Host smart-3a72f085-1042-40aa-b30e-5f36be9c9b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616223793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3616223793
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.881360670
Short name T548
Test name
Test status
Simulation time 211984338 ps
CPU time 1.58 seconds
Started Aug 16 05:40:58 PM PDT 24
Finished Aug 16 05:41:00 PM PDT 24
Peak memory 200316 kb
Host smart-ae456326-20fd-4094-be2d-2088628e3ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881360670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.881360670
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2393829190
Short name T631
Test name
Test status
Simulation time 236214676 ps
CPU time 4.24 seconds
Started Aug 16 05:40:59 PM PDT 24
Finished Aug 16 05:41:03 PM PDT 24
Peak memory 200300 kb
Host smart-d4b40f12-addf-4e61-b2b9-c53a9e902e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393829190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2393829190
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1462740059
Short name T533
Test name
Test status
Simulation time 14026331 ps
CPU time 0.59 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 195400 kb
Host smart-8a0ccb79-b734-45af-a84f-4a36a0be73d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462740059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1462740059
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.4117820074
Short name T615
Test name
Test status
Simulation time 17014431 ps
CPU time 0.59 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 195240 kb
Host smart-d1e2ddd1-6490-40d0-a835-4e9483d8b24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117820074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.4117820074
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2605254370
Short name T638
Test name
Test status
Simulation time 13256032 ps
CPU time 0.56 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 195324 kb
Host smart-b6d23cd3-44b0-4528-9ffb-89693b298139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605254370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2605254370
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1976720257
Short name T595
Test name
Test status
Simulation time 93827053 ps
CPU time 0.55 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 195320 kb
Host smart-04ce90c2-f835-4f5c-bdb4-00a0b919445e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976720257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1976720257
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1788440960
Short name T537
Test name
Test status
Simulation time 87630110 ps
CPU time 0.6 seconds
Started Aug 16 05:41:28 PM PDT 24
Finished Aug 16 05:41:29 PM PDT 24
Peak memory 195396 kb
Host smart-c7f25b40-5398-4bec-ab04-969aa50019aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788440960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1788440960
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3482499381
Short name T641
Test name
Test status
Simulation time 12964377 ps
CPU time 0.61 seconds
Started Aug 16 05:41:48 PM PDT 24
Finished Aug 16 05:41:51 PM PDT 24
Peak memory 195352 kb
Host smart-56e030fa-56f2-4d66-8d79-19d30360b32f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482499381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3482499381
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3610255960
Short name T536
Test name
Test status
Simulation time 25782765 ps
CPU time 0.58 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:14 PM PDT 24
Peak memory 195316 kb
Host smart-8cdabaca-b263-4aab-b5d1-359569477ab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610255960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3610255960
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3987997847
Short name T569
Test name
Test status
Simulation time 39382163 ps
CPU time 0.63 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:42 PM PDT 24
Peak memory 195232 kb
Host smart-70d8e60b-132b-4438-8474-9c87ccf58f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987997847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3987997847
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3021990132
Short name T541
Test name
Test status
Simulation time 18112855 ps
CPU time 0.6 seconds
Started Aug 16 05:41:20 PM PDT 24
Finished Aug 16 05:41:21 PM PDT 24
Peak memory 195264 kb
Host smart-138039b9-a45f-497f-b836-a1d2d308bfd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021990132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3021990132
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2907273911
Short name T652
Test name
Test status
Simulation time 15913017 ps
CPU time 0.58 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:22 PM PDT 24
Peak memory 195244 kb
Host smart-d2ffee6a-6f1f-40ea-845e-52c4ab9ffd37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907273911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2907273911
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1278199328
Short name T603
Test name
Test status
Simulation time 184369477 ps
CPU time 2.98 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 216624 kb
Host smart-dd4c6df2-e31b-4a1b-9fad-a322702d737b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278199328 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1278199328
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.3506586602
Short name T636
Test name
Test status
Simulation time 155166138 ps
CPU time 0.77 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 199844 kb
Host smart-3973c381-60ae-4cf1-be68-423d301c63dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506586602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.3506586602
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1154993925
Short name T540
Test name
Test status
Simulation time 26713709 ps
CPU time 0.6 seconds
Started Aug 16 05:41:24 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 195360 kb
Host smart-ed94272f-62a7-4363-bd46-65638a98a57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154993925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1154993925
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4006797530
Short name T551
Test name
Test status
Simulation time 175566856 ps
CPU time 1.74 seconds
Started Aug 16 05:41:26 PM PDT 24
Finished Aug 16 05:41:28 PM PDT 24
Peak memory 200208 kb
Host smart-e1fc2ce7-1c95-452f-903c-5aab7305b194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006797530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4006797530
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1527672397
Short name T556
Test name
Test status
Simulation time 645635035 ps
CPU time 2.72 seconds
Started Aug 16 05:41:10 PM PDT 24
Finished Aug 16 05:41:18 PM PDT 24
Peak memory 200224 kb
Host smart-d438d673-6448-454e-bb69-8f28f39b7d46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527672397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1527672397
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1291462297
Short name T557
Test name
Test status
Simulation time 204120156 ps
CPU time 3.34 seconds
Started Aug 16 05:41:12 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 215728 kb
Host smart-ce82da1d-315b-4695-9279-a009a368852a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291462297 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1291462297
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2846530984
Short name T630
Test name
Test status
Simulation time 46255194 ps
CPU time 0.8 seconds
Started Aug 16 05:41:41 PM PDT 24
Finished Aug 16 05:41:42 PM PDT 24
Peak memory 200076 kb
Host smart-b2a847ca-5c5b-47fa-bd9b-b9a954f6cc92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846530984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2846530984
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.4089226228
Short name T594
Test name
Test status
Simulation time 27695923 ps
CPU time 0.61 seconds
Started Aug 16 05:41:33 PM PDT 24
Finished Aug 16 05:41:34 PM PDT 24
Peak memory 195272 kb
Host smart-0acdf129-a739-4711-a4d2-b12aee954526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089226228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.4089226228
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2898221361
Short name T110
Test name
Test status
Simulation time 523641824 ps
CPU time 2.25 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:13 PM PDT 24
Peak memory 200220 kb
Host smart-9f27e1a5-b9de-41fb-b45e-d35ebf43037c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898221361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2898221361
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3597886005
Short name T592
Test name
Test status
Simulation time 261198441 ps
CPU time 1.76 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200160 kb
Host smart-f8c10697-b912-4113-8a3a-bcaa841c0812
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597886005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3597886005
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3865957675
Short name T120
Test name
Test status
Simulation time 128643602 ps
CPU time 3.78 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200240 kb
Host smart-d2842757-edb5-4ef6-b5ff-07c414e26dd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865957675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3865957675
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1090483787
Short name T543
Test name
Test status
Simulation time 551759158 ps
CPU time 2.39 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200312 kb
Host smart-b493dd81-b893-4023-bb44-8c18d9631dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090483787 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1090483787
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.833990798
Short name T109
Test name
Test status
Simulation time 240985507 ps
CPU time 0.8 seconds
Started Aug 16 05:41:18 PM PDT 24
Finished Aug 16 05:41:19 PM PDT 24
Peak memory 199328 kb
Host smart-6eceb2b2-b397-4087-ad5f-fd3dbcde9a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833990798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.833990798
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.834389487
Short name T643
Test name
Test status
Simulation time 12330130 ps
CPU time 0.56 seconds
Started Aug 16 05:41:15 PM PDT 24
Finished Aug 16 05:41:16 PM PDT 24
Peak memory 195164 kb
Host smart-08edbe0f-7cef-475d-bddb-6ca5581e2f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834389487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.834389487
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3727482457
Short name T617
Test name
Test status
Simulation time 120451815 ps
CPU time 2.23 seconds
Started Aug 16 05:41:09 PM PDT 24
Finished Aug 16 05:41:11 PM PDT 24
Peak memory 199876 kb
Host smart-a8487b85-1354-4c1f-a536-6826bc30fa78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727482457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3727482457
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1976160719
Short name T604
Test name
Test status
Simulation time 125875334 ps
CPU time 2.63 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200236 kb
Host smart-7a8532e2-2639-4d0f-8101-7396825868b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976160719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1976160719
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.4033950973
Short name T116
Test name
Test status
Simulation time 133779778 ps
CPU time 4.06 seconds
Started Aug 16 05:41:36 PM PDT 24
Finished Aug 16 05:41:40 PM PDT 24
Peak memory 200224 kb
Host smart-3951ae35-233c-40bb-b267-7b42450d8310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033950973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.4033950973
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3788849592
Short name T570
Test name
Test status
Simulation time 97689314949 ps
CPU time 1033.96 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:58:28 PM PDT 24
Peak memory 216804 kb
Host smart-5668e651-a222-467c-9005-60572a7f2eeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788849592 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3788849592
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.117300918
Short name T596
Test name
Test status
Simulation time 25866439 ps
CPU time 0.81 seconds
Started Aug 16 05:41:25 PM PDT 24
Finished Aug 16 05:41:26 PM PDT 24
Peak memory 199748 kb
Host smart-fe3f8b47-f0c8-4b66-841a-11cdde320ee2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117300918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.117300918
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2465236944
Short name T601
Test name
Test status
Simulation time 34514840 ps
CPU time 0.58 seconds
Started Aug 16 05:41:32 PM PDT 24
Finished Aug 16 05:41:32 PM PDT 24
Peak memory 195252 kb
Host smart-f3cbeeb5-fe7d-4898-9198-77fdd3205c34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465236944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2465236944
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3108834537
Short name T620
Test name
Test status
Simulation time 473146439 ps
CPU time 2.35 seconds
Started Aug 16 05:41:23 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 200168 kb
Host smart-cbcaa5b4-6141-466f-9036-97a3857d1a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108834537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3108834537
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3601854766
Short name T618
Test name
Test status
Simulation time 791306599 ps
CPU time 3.4 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:25 PM PDT 24
Peak memory 200204 kb
Host smart-eb2bcc8f-3c42-44c1-b5e3-1810f1e9ff56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601854766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3601854766
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3856305270
Short name T553
Test name
Test status
Simulation time 292804831 ps
CPU time 1.17 seconds
Started Aug 16 05:41:14 PM PDT 24
Finished Aug 16 05:41:15 PM PDT 24
Peak memory 200140 kb
Host smart-fc1842fb-8560-4e40-aac8-c7e5f8a21dd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856305270 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3856305270
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1750261587
Short name T111
Test name
Test status
Simulation time 58379597 ps
CPU time 0.84 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 200028 kb
Host smart-f808ea96-3395-4957-a848-74b677f8cae8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750261587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1750261587
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.633900008
Short name T582
Test name
Test status
Simulation time 17012330 ps
CPU time 0.61 seconds
Started Aug 16 05:41:11 PM PDT 24
Finished Aug 16 05:41:12 PM PDT 24
Peak memory 195240 kb
Host smart-81a560b1-5e38-4f05-90ad-4c05cb65318d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633900008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.633900008
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4062104625
Short name T581
Test name
Test status
Simulation time 222311598 ps
CPU time 1.29 seconds
Started Aug 16 05:41:16 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200068 kb
Host smart-f32a6479-4fcd-4044-b671-142ad828a373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062104625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4062104625
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.4006938515
Short name T584
Test name
Test status
Simulation time 45609846 ps
CPU time 2.26 seconds
Started Aug 16 05:41:21 PM PDT 24
Finished Aug 16 05:41:23 PM PDT 24
Peak memory 200232 kb
Host smart-c6655be6-d18e-41c7-8c57-8130b8a2bc5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006938515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4006938515
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2515647374
Short name T621
Test name
Test status
Simulation time 175646606 ps
CPU time 2.91 seconds
Started Aug 16 05:41:13 PM PDT 24
Finished Aug 16 05:41:17 PM PDT 24
Peak memory 200260 kb
Host smart-7d33c2e4-f3b4-44c2-9834-0caf6a3fdc7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515647374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2515647374
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3686609637
Short name T234
Test name
Test status
Simulation time 40443922 ps
CPU time 0.59 seconds
Started Aug 16 06:29:34 PM PDT 24
Finished Aug 16 06:29:35 PM PDT 24
Peak memory 195652 kb
Host smart-72248ec9-e7bc-4e84-a56b-337500b85bfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686609637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3686609637
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.995975313
Short name T267
Test name
Test status
Simulation time 999444025 ps
CPU time 14.21 seconds
Started Aug 16 06:29:41 PM PDT 24
Finished Aug 16 06:29:55 PM PDT 24
Peak memory 200672 kb
Host smart-fa79f30b-bd72-4c34-a890-681234a7209f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=995975313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.995975313
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3064364847
Short name T50
Test name
Test status
Simulation time 8574916826 ps
CPU time 28.99 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:29:58 PM PDT 24
Peak memory 200776 kb
Host smart-94272cc0-53c9-43a5-a931-59f445832203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064364847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3064364847
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2109199401
Short name T363
Test name
Test status
Simulation time 14818822040 ps
CPU time 1572.5 seconds
Started Aug 16 06:29:31 PM PDT 24
Finished Aug 16 06:55:43 PM PDT 24
Peak memory 786484 kb
Host smart-fa1e78bc-f644-494c-9653-51bccca306cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109199401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2109199401
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2415748783
Short name T18
Test name
Test status
Simulation time 483336768 ps
CPU time 24.86 seconds
Started Aug 16 06:29:30 PM PDT 24
Finished Aug 16 06:29:55 PM PDT 24
Peak memory 200580 kb
Host smart-da57337a-c82e-41bd-bcc5-2ddd68113b34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415748783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2415748783
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1386331821
Short name T253
Test name
Test status
Simulation time 1221038959 ps
CPU time 64.24 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:30:33 PM PDT 24
Peak memory 200700 kb
Host smart-a066aea1-d71c-4ac2-a635-54cfcd7230c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386331821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1386331821
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3657023248
Short name T44
Test name
Test status
Simulation time 352991285 ps
CPU time 0.97 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:29:37 PM PDT 24
Peak memory 220096 kb
Host smart-58a05a13-15e9-4ffb-82b4-3c27abf9df8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657023248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3657023248
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1508636343
Short name T258
Test name
Test status
Simulation time 212957153 ps
CPU time 9.74 seconds
Started Aug 16 06:29:32 PM PDT 24
Finished Aug 16 06:29:42 PM PDT 24
Peak memory 200676 kb
Host smart-d7d1cf56-4295-432d-b9e0-d4aa2c8d65f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508636343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1508636343
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2587549919
Short name T359
Test name
Test status
Simulation time 17771998759 ps
CPU time 270.6 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:34:00 PM PDT 24
Peak memory 217120 kb
Host smart-274d29bf-90a8-4b59-92d3-13d1d3f848dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587549919 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2587549919
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2579277224
Short name T334
Test name
Test status
Simulation time 20408034038 ps
CPU time 66.99 seconds
Started Aug 16 06:29:39 PM PDT 24
Finished Aug 16 06:30:47 PM PDT 24
Peak memory 200732 kb
Host smart-4e8648c7-f974-4d0a-8dba-7bb4a51f7fd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2579277224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2579277224
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1590443664
Short name T141
Test name
Test status
Simulation time 8578663670 ps
CPU time 91.76 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:31:00 PM PDT 24
Peak memory 200812 kb
Host smart-1351015a-55e9-4cd3-a2bf-0a9e5b8b9743
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1590443664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1590443664
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.405441541
Short name T230
Test name
Test status
Simulation time 13165091936 ps
CPU time 90.64 seconds
Started Aug 16 06:29:28 PM PDT 24
Finished Aug 16 06:30:59 PM PDT 24
Peak memory 200684 kb
Host smart-b0382375-ee95-4b3d-999f-ac0f73f74423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=405441541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.405441541
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2897783309
Short name T505
Test name
Test status
Simulation time 135559453904 ps
CPU time 543.62 seconds
Started Aug 16 06:29:32 PM PDT 24
Finished Aug 16 06:38:36 PM PDT 24
Peak memory 200736 kb
Host smart-496d0022-53c1-4138-9785-69cd768a1d0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2897783309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2897783309
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1871413449
Short name T231
Test name
Test status
Simulation time 140705764183 ps
CPU time 2496.42 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 07:11:06 PM PDT 24
Peak memory 216220 kb
Host smart-b33f4b65-1432-4265-9256-6f031209374e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1871413449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1871413449
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2417719021
Short name T459
Test name
Test status
Simulation time 145540364109 ps
CPU time 2395.74 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 07:09:25 PM PDT 24
Peak memory 216056 kb
Host smart-c4a0a6a5-2a73-4896-9299-1929b9f90841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2417719021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2417719021
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2859739027
Short name T381
Test name
Test status
Simulation time 7920770905 ps
CPU time 77.79 seconds
Started Aug 16 06:29:29 PM PDT 24
Finished Aug 16 06:30:47 PM PDT 24
Peak memory 200776 kb
Host smart-867bd8f0-3ad4-4c1c-aad3-a86af68eed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859739027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2859739027
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2076631221
Short name T248
Test name
Test status
Simulation time 15629948 ps
CPU time 0.6 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:29:38 PM PDT 24
Peak memory 196724 kb
Host smart-71af9288-113e-45f7-a3f9-0ea30ab60e35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076631221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2076631221
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.459983423
Short name T208
Test name
Test status
Simulation time 1301443070 ps
CPU time 37.55 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:30:14 PM PDT 24
Peak memory 200696 kb
Host smart-c218f9da-d184-4c93-b6c3-19680e9347a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459983423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.459983423
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2903302163
Short name T465
Test name
Test status
Simulation time 2176990159 ps
CPU time 28.64 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:30:06 PM PDT 24
Peak memory 200752 kb
Host smart-84a5013c-3aa5-439c-b156-3efd3d1e779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903302163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2903302163
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2993616357
Short name T200
Test name
Test status
Simulation time 8982391215 ps
CPU time 681.71 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 06:41:00 PM PDT 24
Peak memory 661924 kb
Host smart-e8c95f35-e4c9-4b1b-ae97-ec12fea30608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993616357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2993616357
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3880617462
Short name T193
Test name
Test status
Simulation time 16487193289 ps
CPU time 137.98 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:31:54 PM PDT 24
Peak memory 200812 kb
Host smart-8c03b8f5-7e6d-41da-99eb-ba515b2b2867
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880617462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3880617462
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2746206193
Short name T275
Test name
Test status
Simulation time 2900458920 ps
CPU time 163.58 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:32:20 PM PDT 24
Peak memory 200724 kb
Host smart-46c1e54b-1037-4bb4-bc05-8696ab95c17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746206193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2746206193
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.4163454805
Short name T177
Test name
Test status
Simulation time 364724841 ps
CPU time 2.69 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:29:39 PM PDT 24
Peak memory 200604 kb
Host smart-9200c741-44aa-4c8e-ba05-ff71d1f29096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163454805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4163454805
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.25869061
Short name T227
Test name
Test status
Simulation time 241694273636 ps
CPU time 1755.72 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:58:53 PM PDT 24
Peak memory 783460 kb
Host smart-8d14cee2-a5ff-4cf4-8a6c-a23a120f8899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869061 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.25869061
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1222775621
Short name T225
Test name
Test status
Simulation time 4927677121 ps
CPU time 79.34 seconds
Started Aug 16 06:29:39 PM PDT 24
Finished Aug 16 06:30:58 PM PDT 24
Peak memory 200676 kb
Host smart-9e608aef-053b-4758-a64e-efcf480ef9cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1222775621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1222775621
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2437985859
Short name T150
Test name
Test status
Simulation time 2459838484 ps
CPU time 96.38 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 06:31:14 PM PDT 24
Peak memory 200792 kb
Host smart-04c50afe-863a-46d8-9b70-a9161ce63d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2437985859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2437985859
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3486830678
Short name T526
Test name
Test status
Simulation time 2964998900 ps
CPU time 108.29 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:31:25 PM PDT 24
Peak memory 200696 kb
Host smart-850bda8f-a0ec-4c15-a0b5-ece0526789ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3486830678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3486830678
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.574982538
Short name T450
Test name
Test status
Simulation time 23608383495 ps
CPU time 577.88 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 06:39:16 PM PDT 24
Peak memory 200576 kb
Host smart-89efa182-6d38-4a67-bb31-b68cf1f77f54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=574982538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.574982538
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3699078282
Short name T467
Test name
Test status
Simulation time 1271049343422 ps
CPU time 2453.4 seconds
Started Aug 16 06:29:34 PM PDT 24
Finished Aug 16 07:10:28 PM PDT 24
Peak memory 217036 kb
Host smart-592f83b7-5a92-4ba7-9399-2eb1ccb87aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3699078282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3699078282
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.806199703
Short name T376
Test name
Test status
Simulation time 2657053232 ps
CPU time 46.56 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:30:21 PM PDT 24
Peak memory 200772 kb
Host smart-9afa87f6-6565-459c-bf1a-bd47b386b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806199703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.806199703
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1893054403
Short name T65
Test name
Test status
Simulation time 5724133083 ps
CPU time 52.76 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:31:02 PM PDT 24
Peak memory 200668 kb
Host smart-16af8b1a-f73f-4b31-9000-75c4832e5380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893054403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1893054403
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2899282806
Short name T172
Test name
Test status
Simulation time 5234439066 ps
CPU time 860.36 seconds
Started Aug 16 06:30:06 PM PDT 24
Finished Aug 16 06:44:27 PM PDT 24
Peak memory 747336 kb
Host smart-1a22a783-fceb-4977-be31-d4cc9e91a018
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899282806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2899282806
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1243258921
Short name T349
Test name
Test status
Simulation time 4944236743 ps
CPU time 12.19 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:30:21 PM PDT 24
Peak memory 200664 kb
Host smart-9ce12457-4b58-4529-85ad-be0c2e14a8d8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243258921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1243258921
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3211367130
Short name T266
Test name
Test status
Simulation time 23547693228 ps
CPU time 107.47 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 200764 kb
Host smart-975180c6-3611-4d7b-8e8c-44c17f9c65bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211367130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3211367130
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3907142175
Short name T239
Test name
Test status
Simulation time 588939897 ps
CPU time 6.6 seconds
Started Aug 16 06:30:08 PM PDT 24
Finished Aug 16 06:30:15 PM PDT 24
Peak memory 200636 kb
Host smart-e082f374-cae6-4256-a47a-1c3f18dc73aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907142175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3907142175
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.699457111
Short name T24
Test name
Test status
Simulation time 9982241333 ps
CPU time 545.65 seconds
Started Aug 16 06:30:07 PM PDT 24
Finished Aug 16 06:39:13 PM PDT 24
Peak memory 200744 kb
Host smart-36b10167-1547-43f8-9acb-fb1f08fe03b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699457111 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.699457111
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1581303964
Short name T509
Test name
Test status
Simulation time 1057771150 ps
CPU time 40.03 seconds
Started Aug 16 06:30:13 PM PDT 24
Finished Aug 16 06:30:53 PM PDT 24
Peak memory 200632 kb
Host smart-d35e438c-2294-44bc-851b-e2a139de31b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581303964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1581303964
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2962833581
Short name T409
Test name
Test status
Simulation time 21633320 ps
CPU time 0.6 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:30:10 PM PDT 24
Peak memory 196752 kb
Host smart-ab039afd-de96-465e-9f0e-7392f81a05b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962833581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2962833581
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2919958175
Short name T453
Test name
Test status
Simulation time 489241212 ps
CPU time 29.68 seconds
Started Aug 16 06:30:07 PM PDT 24
Finished Aug 16 06:30:37 PM PDT 24
Peak memory 200676 kb
Host smart-edd01f15-cb1a-434d-b031-87c1ec85219b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919958175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2919958175
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.680285761
Short name T513
Test name
Test status
Simulation time 7643520858 ps
CPU time 50.43 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:31:00 PM PDT 24
Peak memory 200816 kb
Host smart-31209c86-560d-488d-b762-161a5a57e88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680285761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.680285761
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1595793805
Short name T186
Test name
Test status
Simulation time 3894892691 ps
CPU time 783.95 seconds
Started Aug 16 06:30:11 PM PDT 24
Finished Aug 16 06:43:15 PM PDT 24
Peak memory 688720 kb
Host smart-509f5936-bbc4-455a-a5ba-72efb2761bc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1595793805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1595793805
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2910278511
Short name T344
Test name
Test status
Simulation time 5059361226 ps
CPU time 18.49 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:30:28 PM PDT 24
Peak memory 200680 kb
Host smart-dad01b6d-854a-42c4-83f9-eb74e2847534
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910278511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2910278511
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_smoke.283051563
Short name T83
Test name
Test status
Simulation time 903963214 ps
CPU time 4.35 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:30:15 PM PDT 24
Peak memory 200632 kb
Host smart-1a55cbec-77fb-4e08-a6c4-bad7ef29b571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283051563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.283051563
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2330934381
Short name T183
Test name
Test status
Simulation time 4286178308 ps
CPU time 48.78 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:30:58 PM PDT 24
Peak memory 200648 kb
Host smart-24d04b9b-b41d-44b9-89b4-8922f8720014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330934381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2330934381
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1324626811
Short name T324
Test name
Test status
Simulation time 49540199 ps
CPU time 0.56 seconds
Started Aug 16 06:30:08 PM PDT 24
Finished Aug 16 06:30:09 PM PDT 24
Peak memory 196804 kb
Host smart-28aca0cc-0896-469d-a000-34d54e124e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324626811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1324626811
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1115145612
Short name T19
Test name
Test status
Simulation time 4289752161 ps
CPU time 59.8 seconds
Started Aug 16 06:30:06 PM PDT 24
Finished Aug 16 06:31:06 PM PDT 24
Peak memory 200728 kb
Host smart-643f105c-84ec-4ddf-8372-fd250179cd8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115145612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1115145612
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.212929686
Short name T430
Test name
Test status
Simulation time 312069702 ps
CPU time 6.49 seconds
Started Aug 16 06:30:08 PM PDT 24
Finished Aug 16 06:30:14 PM PDT 24
Peak memory 200488 kb
Host smart-6326ad9c-3cff-4b9a-933a-ed26ca8f5aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212929686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.212929686
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3359398592
Short name T215
Test name
Test status
Simulation time 13639340722 ps
CPU time 1464.27 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:54:33 PM PDT 24
Peak memory 772688 kb
Host smart-56cc8b95-000b-4e5e-a58b-7eff1773f119
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359398592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3359398592
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1197392852
Short name T289
Test name
Test status
Simulation time 184977094 ps
CPU time 1.32 seconds
Started Aug 16 06:30:09 PM PDT 24
Finished Aug 16 06:30:10 PM PDT 24
Peak memory 200576 kb
Host smart-b2e8b9e5-4f1f-458c-95de-7708bf60a153
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197392852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1197392852
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2938247681
Short name T196
Test name
Test status
Simulation time 11497477266 ps
CPU time 85.05 seconds
Started Aug 16 06:30:11 PM PDT 24
Finished Aug 16 06:31:36 PM PDT 24
Peak memory 200856 kb
Host smart-5aa68ced-ecfe-485d-b32d-2357efa2ee0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938247681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2938247681
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1853232264
Short name T7
Test name
Test status
Simulation time 970850864 ps
CPU time 11.22 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:30:22 PM PDT 24
Peak memory 200668 kb
Host smart-35dd3c13-8e5d-4757-91fa-07e4c0160be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853232264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1853232264
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4129735283
Short name T250
Test name
Test status
Simulation time 2993316285 ps
CPU time 177.36 seconds
Started Aug 16 06:30:07 PM PDT 24
Finished Aug 16 06:33:05 PM PDT 24
Peak memory 201188 kb
Host smart-4869c99b-d19d-4de9-bf56-200de47c6999
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129735283 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4129735283
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1801788546
Short name T293
Test name
Test status
Simulation time 20886102854 ps
CPU time 144.96 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:32:35 PM PDT 24
Peak memory 200804 kb
Host smart-4fc457ee-9d7c-4d12-827d-9859e4270686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801788546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1801788546
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2613468679
Short name T455
Test name
Test status
Simulation time 20223937 ps
CPU time 0.58 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:30:15 PM PDT 24
Peak memory 196364 kb
Host smart-53832727-db95-46ac-87de-a604220c38ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613468679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2613468679
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.140052324
Short name T443
Test name
Test status
Simulation time 688474780 ps
CPU time 36.26 seconds
Started Aug 16 06:30:06 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 200668 kb
Host smart-ae961e33-0a2f-4e8d-87c3-5eab7dd0f820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=140052324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.140052324
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3593466358
Short name T341
Test name
Test status
Simulation time 172740426 ps
CPU time 3.85 seconds
Started Aug 16 06:30:12 PM PDT 24
Finished Aug 16 06:30:16 PM PDT 24
Peak memory 200656 kb
Host smart-6f5fb215-bc89-4894-b428-34acb828a253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593466358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3593466358
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.797900130
Short name T397
Test name
Test status
Simulation time 20372748181 ps
CPU time 851.58 seconds
Started Aug 16 06:30:08 PM PDT 24
Finished Aug 16 06:44:20 PM PDT 24
Peak memory 655532 kb
Host smart-e55f8bb6-1146-45ca-8d56-b012a58336b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797900130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.797900130
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1996097066
Short name T523
Test name
Test status
Simulation time 1356070853 ps
CPU time 69.33 seconds
Started Aug 16 06:30:07 PM PDT 24
Finished Aug 16 06:31:17 PM PDT 24
Peak memory 200696 kb
Host smart-3959f822-65bb-46bf-a70d-ab8b7da0993b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996097066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1996097066
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1689481159
Short name T304
Test name
Test status
Simulation time 14057867417 ps
CPU time 179.31 seconds
Started Aug 16 06:30:10 PM PDT 24
Finished Aug 16 06:33:09 PM PDT 24
Peak memory 200656 kb
Host smart-45d46888-026b-44f1-9cb5-b4c3596a8063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689481159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1689481159
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.22505855
Short name T32
Test name
Test status
Simulation time 621077315 ps
CPU time 5.68 seconds
Started Aug 16 06:30:12 PM PDT 24
Finished Aug 16 06:30:17 PM PDT 24
Peak memory 200736 kb
Host smart-4c27b0eb-b4f1-4e1f-a871-f9212e1be94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22505855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.22505855
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2510730164
Short name T132
Test name
Test status
Simulation time 17080054217 ps
CPU time 1336.83 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:52:31 PM PDT 24
Peak memory 690208 kb
Host smart-23dc98cf-824a-4ae9-9d0e-2ebe0d694c0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510730164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2510730164
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1348521556
Short name T350
Test name
Test status
Simulation time 8809348041 ps
CPU time 72.83 seconds
Started Aug 16 06:30:08 PM PDT 24
Finished Aug 16 06:31:21 PM PDT 24
Peak memory 200748 kb
Host smart-b2326a09-7d0e-47b8-aff6-e8df4d8897cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348521556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1348521556
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.373145921
Short name T41
Test name
Test status
Simulation time 45018336 ps
CPU time 0.57 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:30:15 PM PDT 24
Peak memory 196680 kb
Host smart-0eacb317-4a19-4c31-9e18-388fbb9e6aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373145921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.373145921
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1551248456
Short name T315
Test name
Test status
Simulation time 3194810797 ps
CPU time 43.14 seconds
Started Aug 16 06:30:15 PM PDT 24
Finished Aug 16 06:30:58 PM PDT 24
Peak memory 200760 kb
Host smart-dab2e0b1-cbf9-4d00-8c6c-7c7cd5e1c782
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1551248456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1551248456
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3158409027
Short name T380
Test name
Test status
Simulation time 4566934844 ps
CPU time 21.31 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 200648 kb
Host smart-a43b74b9-4a90-4d9e-9bde-f914a6da5f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158409027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3158409027
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3984057578
Short name T494
Test name
Test status
Simulation time 5916634362 ps
CPU time 593.02 seconds
Started Aug 16 06:30:15 PM PDT 24
Finished Aug 16 06:40:08 PM PDT 24
Peak memory 697124 kb
Host smart-ae3d0f3d-45a0-412e-8848-65128efd168e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3984057578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3984057578
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.372944786
Short name T310
Test name
Test status
Simulation time 8167913942 ps
CPU time 142.78 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:32:37 PM PDT 24
Peak memory 200740 kb
Host smart-e5e7137d-d27e-49ad-99a1-f922a10cea61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372944786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.372944786
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.162588205
Short name T477
Test name
Test status
Simulation time 1470642758 ps
CPU time 27.55 seconds
Started Aug 16 06:30:15 PM PDT 24
Finished Aug 16 06:30:42 PM PDT 24
Peak memory 200616 kb
Host smart-87207b52-cc1b-44b8-8711-93450d0d8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162588205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.162588205
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1644466508
Short name T468
Test name
Test status
Simulation time 1659303954 ps
CPU time 10.08 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:30:24 PM PDT 24
Peak memory 200716 kb
Host smart-a86be466-7eb3-4df2-88c6-a5d65c79575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644466508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1644466508
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3619153650
Short name T328
Test name
Test status
Simulation time 1345950658 ps
CPU time 7.56 seconds
Started Aug 16 06:30:16 PM PDT 24
Finished Aug 16 06:30:24 PM PDT 24
Peak memory 200612 kb
Host smart-f7b31ea5-5626-41d9-b47e-855fb5c378b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619153650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3619153650
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.848685352
Short name T257
Test name
Test status
Simulation time 18653953 ps
CPU time 0.59 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:19 PM PDT 24
Peak memory 196416 kb
Host smart-387473e9-ab00-4361-8bca-a4d5b7856fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848685352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.848685352
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1873365482
Short name T205
Test name
Test status
Simulation time 681893417 ps
CPU time 9.55 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 200716 kb
Host smart-8a9062fc-3f30-4d99-83cd-700ffd14224c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1873365482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1873365482
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.4032256917
Short name T326
Test name
Test status
Simulation time 2573006250 ps
CPU time 24.72 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 200764 kb
Host smart-f291f03b-8243-469c-a1b4-33529b09f1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032256917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.4032256917
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.913648711
Short name T166
Test name
Test status
Simulation time 11589127197 ps
CPU time 602.16 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:40:20 PM PDT 24
Peak memory 643956 kb
Host smart-499a1f91-2a61-4764-8062-2f07f6ed4eeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913648711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.913648711
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3099268088
Short name T49
Test name
Test status
Simulation time 23545178978 ps
CPU time 198.55 seconds
Started Aug 16 06:30:14 PM PDT 24
Finished Aug 16 06:33:33 PM PDT 24
Peak memory 200712 kb
Host smart-94670c5b-fdd6-43bf-827b-c2949e02e2df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099268088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3099268088
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3275937786
Short name T501
Test name
Test status
Simulation time 1704408171 ps
CPU time 48.62 seconds
Started Aug 16 06:30:17 PM PDT 24
Finished Aug 16 06:31:06 PM PDT 24
Peak memory 200728 kb
Host smart-5d6b8f25-cbbb-4c0f-a295-6accf58ca056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275937786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3275937786
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3619005539
Short name T167
Test name
Test status
Simulation time 355758086 ps
CPU time 8.29 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 200712 kb
Host smart-e9dc08e3-1b00-48e2-90bd-49ff00f09a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619005539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3619005539
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3716928786
Short name T472
Test name
Test status
Simulation time 36195879526 ps
CPU time 5101.93 seconds
Started Aug 16 06:30:16 PM PDT 24
Finished Aug 16 07:55:19 PM PDT 24
Peak memory 825020 kb
Host smart-6c8e8f31-997d-4c12-a8c3-4f833272967e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716928786 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3716928786
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1724299789
Short name T221
Test name
Test status
Simulation time 576836827 ps
CPU time 25.26 seconds
Started Aug 16 06:30:18 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 200644 kb
Host smart-5d38dd3e-62f8-4521-9673-a3b8ccf85fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724299789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1724299789
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2764204717
Short name T340
Test name
Test status
Simulation time 27830165 ps
CPU time 0.62 seconds
Started Aug 16 06:30:24 PM PDT 24
Finished Aug 16 06:30:25 PM PDT 24
Peak memory 196688 kb
Host smart-7a4c604f-cdf3-46d8-8165-169660ba5fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764204717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2764204717
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3758075952
Short name T165
Test name
Test status
Simulation time 953829161 ps
CPU time 30.4 seconds
Started Aug 16 06:30:25 PM PDT 24
Finished Aug 16 06:30:55 PM PDT 24
Peak memory 200640 kb
Host smart-ff6cba71-86e9-49af-9b89-66adba17d1b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3758075952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3758075952
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3617632133
Short name T171
Test name
Test status
Simulation time 5659439928 ps
CPU time 50.62 seconds
Started Aug 16 06:30:22 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 200804 kb
Host smart-d81e09dc-8a95-4150-a72f-bdcb6a843b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617632133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3617632133
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1672199233
Short name T292
Test name
Test status
Simulation time 14957625494 ps
CPU time 655.16 seconds
Started Aug 16 06:30:22 PM PDT 24
Finished Aug 16 06:41:17 PM PDT 24
Peak memory 676868 kb
Host smart-bda46f8e-edd9-4f6c-a5cd-94cf74eecc16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1672199233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1672199233
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3134250164
Short name T201
Test name
Test status
Simulation time 122232928951 ps
CPU time 299.55 seconds
Started Aug 16 06:30:26 PM PDT 24
Finished Aug 16 06:35:25 PM PDT 24
Peak memory 200720 kb
Host smart-3cfb2941-d1e2-4f0e-a195-d6dc47d17fc7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134250164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3134250164
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.894904206
Short name T411
Test name
Test status
Simulation time 34789856194 ps
CPU time 149.54 seconds
Started Aug 16 06:30:22 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 200808 kb
Host smart-e0fc408b-a8d5-486a-a16e-26d210cb1672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894904206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.894904206
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4082837678
Short name T294
Test name
Test status
Simulation time 294985006 ps
CPU time 12.97 seconds
Started Aug 16 06:30:16 PM PDT 24
Finished Aug 16 06:30:30 PM PDT 24
Peak memory 200692 kb
Host smart-94003900-2705-4353-8f12-9eb4af1cdfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082837678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4082837678
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.873566090
Short name T77
Test name
Test status
Simulation time 41656486293 ps
CPU time 508.59 seconds
Started Aug 16 06:30:21 PM PDT 24
Finished Aug 16 06:38:49 PM PDT 24
Peak memory 217212 kb
Host smart-9cc7b1b7-f0a4-4718-9750-933949ab4810
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873566090 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.873566090
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1295896287
Short name T1
Test name
Test status
Simulation time 476511889 ps
CPU time 22.56 seconds
Started Aug 16 06:30:23 PM PDT 24
Finished Aug 16 06:30:46 PM PDT 24
Peak memory 200612 kb
Host smart-b67e9fe7-feaf-4f49-aefa-e45ce8eb5cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295896287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1295896287
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3913558287
Short name T502
Test name
Test status
Simulation time 115947378 ps
CPU time 0.59 seconds
Started Aug 16 06:30:33 PM PDT 24
Finished Aug 16 06:30:34 PM PDT 24
Peak memory 196736 kb
Host smart-1b9670a4-1581-491b-982e-90342d1dfb90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913558287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3913558287
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3075921452
Short name T67
Test name
Test status
Simulation time 287884859 ps
CPU time 16.38 seconds
Started Aug 16 06:30:29 PM PDT 24
Finished Aug 16 06:30:46 PM PDT 24
Peak memory 200632 kb
Host smart-7a17aa40-9b88-4fec-8f21-ebe0350964d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3075921452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3075921452
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.879099616
Short name T145
Test name
Test status
Simulation time 1257514921 ps
CPU time 3.95 seconds
Started Aug 16 06:30:31 PM PDT 24
Finished Aug 16 06:30:35 PM PDT 24
Peak memory 200724 kb
Host smart-13ef1424-46eb-4835-abc5-c7265f7e86bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879099616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.879099616
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1264116411
Short name T332
Test name
Test status
Simulation time 15518909394 ps
CPU time 562.42 seconds
Started Aug 16 06:30:30 PM PDT 24
Finished Aug 16 06:39:52 PM PDT 24
Peak memory 713600 kb
Host smart-27b7ad0a-e0e1-4124-9bc9-1dfc3b43d7a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1264116411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1264116411
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.161636711
Short name T189
Test name
Test status
Simulation time 10512676684 ps
CPU time 146.5 seconds
Started Aug 16 06:30:31 PM PDT 24
Finished Aug 16 06:32:57 PM PDT 24
Peak memory 200708 kb
Host smart-6379fd03-bec9-4643-aae5-1e03015fe03b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161636711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.161636711
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2383301496
Short name T487
Test name
Test status
Simulation time 7585160816 ps
CPU time 133.87 seconds
Started Aug 16 06:30:28 PM PDT 24
Finished Aug 16 06:32:42 PM PDT 24
Peak memory 200728 kb
Host smart-1dcb00a0-0e6d-4f07-ae10-b1fbdaf684f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383301496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2383301496
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.558009180
Short name T245
Test name
Test status
Simulation time 377941390 ps
CPU time 6.7 seconds
Started Aug 16 06:30:22 PM PDT 24
Finished Aug 16 06:30:29 PM PDT 24
Peak memory 200808 kb
Host smart-52cfdb7b-e090-478a-8078-e797e3e3f22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558009180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.558009180
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.242029855
Short name T444
Test name
Test status
Simulation time 682568475222 ps
CPU time 2605.09 seconds
Started Aug 16 06:30:26 PM PDT 24
Finished Aug 16 07:13:52 PM PDT 24
Peak memory 759636 kb
Host smart-e2a88f60-70f5-42e3-a734-4b14e863e627
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242029855 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.242029855
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4144750701
Short name T209
Test name
Test status
Simulation time 165581430 ps
CPU time 9.05 seconds
Started Aug 16 06:30:28 PM PDT 24
Finished Aug 16 06:30:37 PM PDT 24
Peak memory 200676 kb
Host smart-20a9874a-0f8c-42e8-897a-37e42fd0a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144750701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4144750701
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2722697859
Short name T514
Test name
Test status
Simulation time 15242311 ps
CPU time 0.61 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:30:36 PM PDT 24
Peak memory 196720 kb
Host smart-5b6da75f-f200-412e-bad2-86acf008c557
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722697859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2722697859
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.100836571
Short name T442
Test name
Test status
Simulation time 2468103650 ps
CPU time 70.53 seconds
Started Aug 16 06:30:31 PM PDT 24
Finished Aug 16 06:31:41 PM PDT 24
Peak memory 200724 kb
Host smart-609516c3-d821-4f70-a467-5b8c0778e3e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100836571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.100836571
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1751040783
Short name T199
Test name
Test status
Simulation time 2400911514 ps
CPU time 43.94 seconds
Started Aug 16 06:30:31 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 200868 kb
Host smart-8a333942-4422-4b2d-b6f1-fc1d631e68a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751040783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1751040783
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2272876445
Short name T419
Test name
Test status
Simulation time 715581554 ps
CPU time 21.59 seconds
Started Aug 16 06:30:29 PM PDT 24
Finished Aug 16 06:30:50 PM PDT 24
Peak memory 241892 kb
Host smart-044ca2a2-8849-4aa3-bd01-33aa72f5126d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272876445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2272876445
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1256078638
Short name T437
Test name
Test status
Simulation time 51886950266 ps
CPU time 145.64 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:33:01 PM PDT 24
Peak memory 200740 kb
Host smart-ec62fa85-7136-42fe-a69b-7fe124676f4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256078638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1256078638
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1998777083
Short name T55
Test name
Test status
Simulation time 4626708651 ps
CPU time 159.39 seconds
Started Aug 16 06:30:27 PM PDT 24
Finished Aug 16 06:33:07 PM PDT 24
Peak memory 216852 kb
Host smart-b721c23a-a494-4cbd-bf40-960d2f5df922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998777083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1998777083
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3526947554
Short name T297
Test name
Test status
Simulation time 491363828 ps
CPU time 4.35 seconds
Started Aug 16 06:30:43 PM PDT 24
Finished Aug 16 06:30:47 PM PDT 24
Peak memory 200668 kb
Host smart-58e552ae-4667-469a-8715-cabfa56edb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526947554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3526947554
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1274437766
Short name T417
Test name
Test status
Simulation time 25349996428 ps
CPU time 605.85 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:40:42 PM PDT 24
Peak memory 476260 kb
Host smart-dbfa0b10-6318-4c4f-ac9e-67a64c4afc92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274437766 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1274437766
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.446535992
Short name T242
Test name
Test status
Simulation time 2221579536 ps
CPU time 53.95 seconds
Started Aug 16 06:30:37 PM PDT 24
Finished Aug 16 06:31:31 PM PDT 24
Peak memory 200772 kb
Host smart-bda419e9-8fbd-42a3-b872-33635a52b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446535992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.446535992
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3237955221
Short name T454
Test name
Test status
Simulation time 37902864 ps
CPU time 0.6 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:30:37 PM PDT 24
Peak memory 196328 kb
Host smart-7c3c062f-de60-458d-868e-54331e94230b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237955221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3237955221
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3791673358
Short name T511
Test name
Test status
Simulation time 2691564211 ps
CPU time 39.07 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 200756 kb
Host smart-7fdc5c77-c954-4325-9788-2d7e974cac6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791673358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3791673358
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4130597702
Short name T140
Test name
Test status
Simulation time 2591339812 ps
CPU time 10.72 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:30:47 PM PDT 24
Peak memory 200784 kb
Host smart-0071f51e-0da3-48fa-91df-0823f67d9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130597702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4130597702
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2974613986
Short name T474
Test name
Test status
Simulation time 41205120297 ps
CPU time 580.32 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:40:16 PM PDT 24
Peak memory 664908 kb
Host smart-949dfcd8-cba4-4b7f-96ed-89b91d165a36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974613986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2974613986
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4028033220
Short name T283
Test name
Test status
Simulation time 13294212643 ps
CPU time 120.38 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:32:36 PM PDT 24
Peak memory 200784 kb
Host smart-700ef11b-41d3-4eaf-9d14-108fec93260e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028033220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4028033220
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2514111683
Short name T383
Test name
Test status
Simulation time 9616215274 ps
CPU time 129.51 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:32:46 PM PDT 24
Peak memory 217040 kb
Host smart-486853b8-a23b-43af-abd9-0586476ab237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514111683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2514111683
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.304707916
Short name T251
Test name
Test status
Simulation time 547343546 ps
CPU time 2.33 seconds
Started Aug 16 06:30:37 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 200664 kb
Host smart-96fe685b-05ce-4287-80f2-07c29cd4c449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304707916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.304707916
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.4205019592
Short name T135
Test name
Test status
Simulation time 94308554420 ps
CPU time 1472.34 seconds
Started Aug 16 06:30:38 PM PDT 24
Finished Aug 16 06:55:11 PM PDT 24
Peak memory 768952 kb
Host smart-707ebb1b-db77-49b9-8253-9e8344fa6abb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205019592 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.4205019592
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3953786660
Short name T303
Test name
Test status
Simulation time 376974223 ps
CPU time 5.74 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:30:41 PM PDT 24
Peak memory 200712 kb
Host smart-e8b127bd-5f6e-4544-8df6-c973398139dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953786660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3953786660
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1997000305
Short name T144
Test name
Test status
Simulation time 14685870 ps
CPU time 0.61 seconds
Started Aug 16 06:29:44 PM PDT 24
Finished Aug 16 06:29:45 PM PDT 24
Peak memory 196808 kb
Host smart-7fc26809-726b-4888-9f5c-fbd5ad878c27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997000305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1997000305
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3731655758
Short name T339
Test name
Test status
Simulation time 10030063554 ps
CPU time 100.83 seconds
Started Aug 16 06:29:45 PM PDT 24
Finished Aug 16 06:31:25 PM PDT 24
Peak memory 217028 kb
Host smart-1daef8b0-1078-43cc-a6de-a8c024cc7e3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3731655758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3731655758
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.275730038
Short name T237
Test name
Test status
Simulation time 850354204 ps
CPU time 14.77 seconds
Started Aug 16 06:29:34 PM PDT 24
Finished Aug 16 06:29:49 PM PDT 24
Peak memory 200680 kb
Host smart-d33ca9f6-e36f-4fc9-9ae9-fbb36b8cf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275730038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.275730038
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2975495384
Short name T483
Test name
Test status
Simulation time 9742159081 ps
CPU time 942.68 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:45:19 PM PDT 24
Peak memory 606028 kb
Host smart-7135cace-28c6-41a7-99c5-6079bce31c90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975495384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2975495384
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3555928434
Short name T394
Test name
Test status
Simulation time 7952293992 ps
CPU time 141.38 seconds
Started Aug 16 06:29:36 PM PDT 24
Finished Aug 16 06:31:58 PM PDT 24
Peak memory 200720 kb
Host smart-87f70c00-8dbb-49ce-9fd0-adf035caf008
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555928434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3555928434
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1904875853
Short name T311
Test name
Test status
Simulation time 39645503865 ps
CPU time 120.41 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:31:36 PM PDT 24
Peak memory 200756 kb
Host smart-2993f6fe-c2f4-4e23-8c9f-6ac55b6f92ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904875853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1904875853
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.175447847
Short name T43
Test name
Test status
Simulation time 234507408 ps
CPU time 0.9 seconds
Started Aug 16 06:29:45 PM PDT 24
Finished Aug 16 06:29:46 PM PDT 24
Peak memory 218932 kb
Host smart-9776101d-cd94-4513-8d81-5bf31c2f1056
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175447847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.175447847
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4078085602
Short name T353
Test name
Test status
Simulation time 2306446063 ps
CPU time 13.45 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:29:48 PM PDT 24
Peak memory 200668 kb
Host smart-433a9067-5513-4fed-acec-5496b75be00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078085602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4078085602
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2313676881
Short name T71
Test name
Test status
Simulation time 49868539887 ps
CPU time 1711.48 seconds
Started Aug 16 06:29:42 PM PDT 24
Finished Aug 16 06:58:14 PM PDT 24
Peak memory 761820 kb
Host smart-16239028-f133-4ff3-afd2-0244cd981045
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313676881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2313676881
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2340538581
Short name T285
Test name
Test status
Simulation time 2725669504 ps
CPU time 41.85 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:30:19 PM PDT 24
Peak memory 200640 kb
Host smart-af0792d5-08f8-4e9c-9754-d2950ef744f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2340538581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2340538581
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.181975416
Short name T521
Test name
Test status
Simulation time 9985207121 ps
CPU time 97.61 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 06:31:16 PM PDT 24
Peak memory 200444 kb
Host smart-c78e26e9-abb6-4dc3-9494-9ab7271e51dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=181975416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.181975416
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2250401105
Short name T330
Test name
Test status
Simulation time 13278214388 ps
CPU time 122.72 seconds
Started Aug 16 06:29:37 PM PDT 24
Finished Aug 16 06:31:39 PM PDT 24
Peak memory 200724 kb
Host smart-1b7091f4-b767-4e64-b787-17deaac250ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2250401105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2250401105
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1953609811
Short name T125
Test name
Test status
Simulation time 43854789127 ps
CPU time 558.96 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:38:54 PM PDT 24
Peak memory 200672 kb
Host smart-e6ba7dce-8fbb-4b1f-8f2e-8a2f82d51a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1953609811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1953609811
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3479213618
Short name T124
Test name
Test status
Simulation time 37650314870 ps
CPU time 2062 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 07:03:58 PM PDT 24
Peak memory 216676 kb
Host smart-e8dc1666-2419-4596-9bf2-c5916815ac8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3479213618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3479213618
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.3806648010
Short name T219
Test name
Test status
Simulation time 42497737532 ps
CPU time 2312.92 seconds
Started Aug 16 06:29:38 PM PDT 24
Finished Aug 16 07:08:12 PM PDT 24
Peak memory 215816 kb
Host smart-c71413a1-acba-4fda-9ab6-d4a6da62f5cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3806648010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.3806648010
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.934545190
Short name T520
Test name
Test status
Simulation time 1686564775 ps
CPU time 20.92 seconds
Started Aug 16 06:29:35 PM PDT 24
Finished Aug 16 06:29:56 PM PDT 24
Peak memory 200728 kb
Host smart-75ec59ba-0de6-4fdb-b27c-3ab3f84fee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934545190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.934545190
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3617397170
Short name T261
Test name
Test status
Simulation time 12971512 ps
CPU time 0.59 seconds
Started Aug 16 06:30:43 PM PDT 24
Finished Aug 16 06:30:44 PM PDT 24
Peak memory 196416 kb
Host smart-254c11da-3221-482f-8897-d0424e0c1982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617397170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3617397170
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1557052467
Short name T296
Test name
Test status
Simulation time 1280477823 ps
CPU time 71.54 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:31:47 PM PDT 24
Peak memory 200660 kb
Host smart-6f0fefb7-39ee-44f1-97b7-2165a82f1774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557052467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1557052467
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2240653582
Short name T136
Test name
Test status
Simulation time 2295882265 ps
CPU time 75.18 seconds
Started Aug 16 06:30:45 PM PDT 24
Finished Aug 16 06:32:00 PM PDT 24
Peak memory 200736 kb
Host smart-345aae7f-2afd-4b1d-8c43-27c106456ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240653582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2240653582
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3944894586
Short name T460
Test name
Test status
Simulation time 3422100831 ps
CPU time 282.71 seconds
Started Aug 16 06:30:35 PM PDT 24
Finished Aug 16 06:35:18 PM PDT 24
Peak memory 486428 kb
Host smart-d709d1ce-b574-4c36-a9ff-0c98906a122a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944894586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3944894586
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1892532915
Short name T42
Test name
Test status
Simulation time 18655613085 ps
CPU time 179.37 seconds
Started Aug 16 06:30:54 PM PDT 24
Finished Aug 16 06:33:54 PM PDT 24
Peak memory 200712 kb
Host smart-9106180f-8dfe-4d08-89f0-30de6ef518a3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892532915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1892532915
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2081549550
Short name T351
Test name
Test status
Simulation time 24995309762 ps
CPU time 61.6 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:31:38 PM PDT 24
Peak memory 200736 kb
Host smart-87dbae53-b615-46eb-81d2-bad441f8d9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081549550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2081549550
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3419182225
Short name T480
Test name
Test status
Simulation time 217369350 ps
CPU time 2.63 seconds
Started Aug 16 06:30:36 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 200748 kb
Host smart-08885bc7-58e9-422d-882a-f95de5708da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419182225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3419182225
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.431255445
Short name T366
Test name
Test status
Simulation time 33579213781 ps
CPU time 535.27 seconds
Started Aug 16 06:30:43 PM PDT 24
Finished Aug 16 06:39:39 PM PDT 24
Peak memory 388628 kb
Host smart-ece43f37-4b49-438a-87ba-d1746c061088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431255445 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.431255445
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3816450690
Short name T319
Test name
Test status
Simulation time 2339470098 ps
CPU time 56.93 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:31:47 PM PDT 24
Peak memory 200708 kb
Host smart-9b033ac3-76ec-4dcc-a5fd-88ef81e758d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816450690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3816450690
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1453667173
Short name T263
Test name
Test status
Simulation time 50846675 ps
CPU time 0.58 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:30:51 PM PDT 24
Peak memory 196772 kb
Host smart-7ca83663-fe88-4710-bb71-d6269c83bce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453667173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1453667173
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.38351486
Short name T192
Test name
Test status
Simulation time 866779900 ps
CPU time 43.87 seconds
Started Aug 16 06:30:45 PM PDT 24
Finished Aug 16 06:31:29 PM PDT 24
Peak memory 200640 kb
Host smart-5f1d2b03-bb20-496c-8546-7499d97e17c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38351486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.38351486
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4228287260
Short name T392
Test name
Test status
Simulation time 793748762 ps
CPU time 14.66 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:31:04 PM PDT 24
Peak memory 200640 kb
Host smart-3ee9fd58-dd0a-401e-bfe0-4dc81c42cb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228287260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4228287260
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4245757253
Short name T206
Test name
Test status
Simulation time 72927651910 ps
CPU time 1520.59 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:56:11 PM PDT 24
Peak memory 723348 kb
Host smart-9debc39b-ff2e-4f6a-a72d-5af9a184451a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245757253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4245757253
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2042530949
Short name T276
Test name
Test status
Simulation time 6051745566 ps
CPU time 160.86 seconds
Started Aug 16 06:30:44 PM PDT 24
Finished Aug 16 06:33:25 PM PDT 24
Peak memory 200712 kb
Host smart-47039b81-13cd-425f-8399-8fbd77258ff2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042530949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2042530949
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.912485285
Short name T274
Test name
Test status
Simulation time 1332669902 ps
CPU time 76.82 seconds
Started Aug 16 06:30:43 PM PDT 24
Finished Aug 16 06:32:00 PM PDT 24
Peak memory 200608 kb
Host smart-61f79451-b072-4f92-aa44-2383c0c9a190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912485285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.912485285
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3226221452
Short name T329
Test name
Test status
Simulation time 681581975 ps
CPU time 11.09 seconds
Started Aug 16 06:30:43 PM PDT 24
Finished Aug 16 06:30:54 PM PDT 24
Peak memory 200672 kb
Host smart-2561507f-c5b1-4252-bb51-b54d1c262351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226221452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3226221452
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3864825129
Short name T302
Test name
Test status
Simulation time 302960529291 ps
CPU time 1121.26 seconds
Started Aug 16 06:30:49 PM PDT 24
Finished Aug 16 06:49:31 PM PDT 24
Peak memory 451552 kb
Host smart-74370e73-33c8-43e7-9aa6-b317ce3d70c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864825129 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3864825129
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.589018232
Short name T115
Test name
Test status
Simulation time 1970992212 ps
CPU time 50.75 seconds
Started Aug 16 06:30:45 PM PDT 24
Finished Aug 16 06:31:36 PM PDT 24
Peak memory 200672 kb
Host smart-8b619dd2-7b53-49a2-942b-31236eb66c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589018232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.589018232
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1685651820
Short name T449
Test name
Test status
Simulation time 19106119 ps
CPU time 0.56 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:30:53 PM PDT 24
Peak memory 195708 kb
Host smart-bdf1b61f-ce9b-427c-a9d8-885173df807a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685651820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1685651820
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2000143043
Short name T284
Test name
Test status
Simulation time 8167020784 ps
CPU time 112.86 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:32:45 PM PDT 24
Peak memory 200760 kb
Host smart-7ee57fbe-a087-4879-99a4-32c7d7f052cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2000143043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2000143043
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3872909959
Short name T155
Test name
Test status
Simulation time 4624639550 ps
CPU time 19.08 seconds
Started Aug 16 06:31:27 PM PDT 24
Finished Aug 16 06:31:46 PM PDT 24
Peak memory 200736 kb
Host smart-1306dda7-7cca-4645-ac55-e8592282507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872909959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3872909959
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1356123766
Short name T243
Test name
Test status
Simulation time 3687607512 ps
CPU time 321.97 seconds
Started Aug 16 06:30:49 PM PDT 24
Finished Aug 16 06:36:12 PM PDT 24
Peak memory 611636 kb
Host smart-8507b608-16cb-49cf-b73d-eba2b42d52ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1356123766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1356123766
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.193334118
Short name T517
Test name
Test status
Simulation time 81180491155 ps
CPU time 199.98 seconds
Started Aug 16 06:30:55 PM PDT 24
Finished Aug 16 06:34:15 PM PDT 24
Peak memory 200716 kb
Host smart-64375b3f-e556-422a-990d-ac1253e74977
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193334118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.193334118
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2340839641
Short name T158
Test name
Test status
Simulation time 6624279501 ps
CPU time 82.45 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:32:14 PM PDT 24
Peak memory 200732 kb
Host smart-d5f374f7-14d4-41a4-a481-805bdd17cb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340839641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2340839641
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2527540576
Short name T240
Test name
Test status
Simulation time 32389369 ps
CPU time 1.62 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:30:52 PM PDT 24
Peak memory 200668 kb
Host smart-eab7ed90-24a9-48cd-b66f-21035980db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527540576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2527540576
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.274170624
Short name T76
Test name
Test status
Simulation time 30624638696 ps
CPU time 160.78 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:33:33 PM PDT 24
Peak memory 217104 kb
Host smart-824e0a7e-87b6-45e1-be5a-c14dbf389d24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274170624 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.274170624
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1619476080
Short name T223
Test name
Test status
Simulation time 2425127003 ps
CPU time 62.68 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:31:54 PM PDT 24
Peak memory 200800 kb
Host smart-ee5aeb39-1958-4f07-83a5-9ed29f7f5ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619476080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1619476080
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2866706057
Short name T367
Test name
Test status
Simulation time 11890723 ps
CPU time 0.6 seconds
Started Aug 16 06:30:54 PM PDT 24
Finished Aug 16 06:30:55 PM PDT 24
Peak memory 197416 kb
Host smart-b57571c0-e234-4ddd-97dd-1f59fedc1bdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866706057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2866706057
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2486788019
Short name T272
Test name
Test status
Simulation time 3128375847 ps
CPU time 51.25 seconds
Started Aug 16 06:30:49 PM PDT 24
Finished Aug 16 06:31:40 PM PDT 24
Peak memory 200668 kb
Host smart-dcd92f55-1e3d-4daf-b0aa-b477c8d693b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486788019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2486788019
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1249438363
Short name T131
Test name
Test status
Simulation time 1191168959 ps
CPU time 31.16 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:31:22 PM PDT 24
Peak memory 200744 kb
Host smart-d025a00c-8405-43f6-9b53-81eea0a2a7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249438363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1249438363
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1663322589
Short name T185
Test name
Test status
Simulation time 27962822208 ps
CPU time 362.38 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:36:53 PM PDT 24
Peak memory 467956 kb
Host smart-5a9de3c4-70da-45f8-93e3-c3b7e8710206
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1663322589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1663322589
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1678215269
Short name T235
Test name
Test status
Simulation time 29239479342 ps
CPU time 87.75 seconds
Started Aug 16 06:30:55 PM PDT 24
Finished Aug 16 06:32:22 PM PDT 24
Peak memory 200724 kb
Host smart-ccf76e9c-1c6c-4c62-b36d-3ab057a6f1cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678215269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1678215269
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3751523158
Short name T488
Test name
Test status
Simulation time 1281356149 ps
CPU time 6.75 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:30:59 PM PDT 24
Peak memory 200596 kb
Host smart-302be8b4-0de7-4de7-ac00-07eff73d58a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751523158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3751523158
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.163729730
Short name T33
Test name
Test status
Simulation time 1412691453 ps
CPU time 9.45 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:31:00 PM PDT 24
Peak memory 200704 kb
Host smart-bcf617eb-4a23-4f0a-8bb3-100c4db7f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163729730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.163729730
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.581082628
Short name T13
Test name
Test status
Simulation time 92466493066 ps
CPU time 1331.25 seconds
Started Aug 16 06:30:52 PM PDT 24
Finished Aug 16 06:53:04 PM PDT 24
Peak memory 726388 kb
Host smart-e8c838fa-8f0a-40b4-8dcf-75411f155375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581082628 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.581082628
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2674384954
Short name T416
Test name
Test status
Simulation time 8625112874 ps
CPU time 118.53 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:32:49 PM PDT 24
Peak memory 200800 kb
Host smart-694ee598-87a2-4e0b-9b3c-782f8211beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674384954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2674384954
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4173434367
Short name T69
Test name
Test status
Simulation time 145965014 ps
CPU time 0.62 seconds
Started Aug 16 06:31:03 PM PDT 24
Finished Aug 16 06:31:04 PM PDT 24
Peak memory 196752 kb
Host smart-7fc84d48-9eed-47f2-b105-54bbf15b354c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173434367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4173434367
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2916453911
Short name T519
Test name
Test status
Simulation time 408792296 ps
CPU time 21.01 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 200648 kb
Host smart-8f07f72d-d5e7-4214-8cda-930ee02c02c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2916453911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2916453911
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3406338577
Short name T236
Test name
Test status
Simulation time 6225507303 ps
CPU time 50.47 seconds
Started Aug 16 06:30:54 PM PDT 24
Finished Aug 16 06:31:45 PM PDT 24
Peak memory 200792 kb
Host smart-6e86bcdc-c480-4d6e-ac1e-8ea7f298c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406338577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3406338577
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3974608370
Short name T5
Test name
Test status
Simulation time 39113689253 ps
CPU time 921.99 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:46:14 PM PDT 24
Peak memory 757128 kb
Host smart-68d08ce6-e74b-4065-a8f9-c270dbc165ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974608370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3974608370
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3810403305
Short name T64
Test name
Test status
Simulation time 20689550942 ps
CPU time 280.54 seconds
Started Aug 16 06:30:50 PM PDT 24
Finished Aug 16 06:35:31 PM PDT 24
Peak memory 200760 kb
Host smart-53ce7306-fbfd-4534-b5ae-12a22f759d1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810403305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3810403305
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3992771627
Short name T479
Test name
Test status
Simulation time 9630889014 ps
CPU time 158.34 seconds
Started Aug 16 06:30:51 PM PDT 24
Finished Aug 16 06:33:29 PM PDT 24
Peak memory 208952 kb
Host smart-10f0d7d4-7def-492f-b27d-75edd3b9810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992771627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3992771627
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.552587856
Short name T259
Test name
Test status
Simulation time 1171379929 ps
CPU time 17.02 seconds
Started Aug 16 06:30:55 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 200796 kb
Host smart-7bc2dca4-a1a4-4d28-8863-7021d1f56e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552587856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.552587856
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.694870116
Short name T75
Test name
Test status
Simulation time 106823844936 ps
CPU time 2165.75 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 07:07:07 PM PDT 24
Peak memory 710288 kb
Host smart-163b0061-2043-4946-b2c4-984e39fc5475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694870116 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.694870116
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.661483638
Short name T21
Test name
Test status
Simulation time 6861213611 ps
CPU time 92.08 seconds
Started Aug 16 06:30:58 PM PDT 24
Finished Aug 16 06:32:31 PM PDT 24
Peak memory 200680 kb
Host smart-f3642c75-9483-476e-9c29-ea40e9d64bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661483638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.661483638
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2426323339
Short name T299
Test name
Test status
Simulation time 14850232 ps
CPU time 0.61 seconds
Started Aug 16 06:31:01 PM PDT 24
Finished Aug 16 06:31:01 PM PDT 24
Peak memory 196632 kb
Host smart-2a9db905-8791-4086-a360-4959549244f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426323339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2426323339
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2190331264
Short name T70
Test name
Test status
Simulation time 23397519 ps
CPU time 1.11 seconds
Started Aug 16 06:31:02 PM PDT 24
Finished Aug 16 06:31:03 PM PDT 24
Peak memory 200488 kb
Host smart-86fe3840-318e-42b9-939f-2a145c4670d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190331264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2190331264
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1526157854
Short name T81
Test name
Test status
Simulation time 3712805875 ps
CPU time 46.83 seconds
Started Aug 16 06:30:59 PM PDT 24
Finished Aug 16 06:31:46 PM PDT 24
Peak memory 200664 kb
Host smart-35dcfa6f-19fc-42eb-8d2b-0cdd7413531f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526157854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1526157854
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.329649087
Short name T321
Test name
Test status
Simulation time 26913751963 ps
CPU time 1081.75 seconds
Started Aug 16 06:30:58 PM PDT 24
Finished Aug 16 06:49:00 PM PDT 24
Peak memory 756912 kb
Host smart-72b96b56-973a-4a56-bf38-aa3f3429c47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329649087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.329649087
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1976585672
Short name T492
Test name
Test status
Simulation time 87677877625 ps
CPU time 90.91 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:32:31 PM PDT 24
Peak memory 200708 kb
Host smart-3f5b59e8-cce9-4fb2-93a7-17bc79e37497
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976585672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1976585672
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2881716571
Short name T149
Test name
Test status
Simulation time 802393218 ps
CPU time 7.81 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:31:08 PM PDT 24
Peak memory 200692 kb
Host smart-b3cd0dbe-3a6f-4e6e-bd1a-439731147bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881716571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2881716571
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.650949268
Short name T338
Test name
Test status
Simulation time 1560866924 ps
CPU time 3.5 seconds
Started Aug 16 06:31:01 PM PDT 24
Finished Aug 16 06:31:04 PM PDT 24
Peak memory 200760 kb
Host smart-0b812e2e-4515-4808-a94a-e28e4c388e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650949268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.650949268
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.5817212
Short name T506
Test name
Test status
Simulation time 16874575897 ps
CPU time 483.62 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:39:04 PM PDT 24
Peak memory 217080 kb
Host smart-6e43cb25-a172-4b75-8130-6068057d6f59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5817212 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.5817212
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2955682789
Short name T352
Test name
Test status
Simulation time 6791919308 ps
CPU time 90.02 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:32:31 PM PDT 24
Peak memory 200676 kb
Host smart-167749bb-730a-43b8-91ea-293d44f8f482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955682789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2955682789
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3723796751
Short name T2
Test name
Test status
Simulation time 46579780 ps
CPU time 0.6 seconds
Started Aug 16 06:31:09 PM PDT 24
Finished Aug 16 06:31:09 PM PDT 24
Peak memory 196360 kb
Host smart-ed557691-3842-468b-bf64-73384e8bae04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723796751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3723796751
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2367128637
Short name T129
Test name
Test status
Simulation time 3420973202 ps
CPU time 46.92 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:31:47 PM PDT 24
Peak memory 200772 kb
Host smart-a4c01b34-a1f2-48b6-a7db-133e58fb4c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367128637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2367128637
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1561121124
Short name T337
Test name
Test status
Simulation time 1718996872 ps
CPU time 20.09 seconds
Started Aug 16 06:31:11 PM PDT 24
Finished Aug 16 06:31:32 PM PDT 24
Peak memory 200672 kb
Host smart-2cbd4b4f-a116-49dc-857a-8b8dbf457640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561121124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1561121124
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.287186025
Short name T226
Test name
Test status
Simulation time 7612362328 ps
CPU time 256.62 seconds
Started Aug 16 06:30:59 PM PDT 24
Finished Aug 16 06:35:16 PM PDT 24
Peak memory 452440 kb
Host smart-79fc854a-e527-4167-952f-cbdcefd35eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=287186025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.287186025
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.905421023
Short name T160
Test name
Test status
Simulation time 11560798219 ps
CPU time 198.91 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:34:27 PM PDT 24
Peak memory 200744 kb
Host smart-42049620-7fb7-4920-a962-8e183eecbd29
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905421023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.905421023
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3044019993
Short name T36
Test name
Test status
Simulation time 2741771042 ps
CPU time 148.43 seconds
Started Aug 16 06:30:58 PM PDT 24
Finished Aug 16 06:33:27 PM PDT 24
Peak memory 200848 kb
Host smart-f058eb34-6e68-4c84-83c0-0d4439934b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044019993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3044019993
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3044695279
Short name T512
Test name
Test status
Simulation time 149706011 ps
CPU time 6.8 seconds
Started Aug 16 06:31:00 PM PDT 24
Finished Aug 16 06:31:07 PM PDT 24
Peak memory 200680 kb
Host smart-0c4e3ae0-c02e-473b-8bb7-2563634c8cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044695279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3044695279
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.43011899
Short name T384
Test name
Test status
Simulation time 14637366533 ps
CPU time 1189.66 seconds
Started Aug 16 06:31:09 PM PDT 24
Finished Aug 16 06:50:59 PM PDT 24
Peak memory 656140 kb
Host smart-299e1d75-4711-41c0-8949-5015bbec6e85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43011899 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.43011899
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.955130102
Short name T113
Test name
Test status
Simulation time 6521074660 ps
CPU time 61.41 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:32:10 PM PDT 24
Peak memory 200832 kb
Host smart-3e832417-9903-4d04-b366-cfc23c652b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955130102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.955130102
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.966128667
Short name T452
Test name
Test status
Simulation time 18153871 ps
CPU time 0.6 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:31:11 PM PDT 24
Peak memory 195700 kb
Host smart-31d3ee25-ef6a-400d-99e0-072379a6a143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966128667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.966128667
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1929367731
Short name T34
Test name
Test status
Simulation time 117111146 ps
CPU time 6.76 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 200680 kb
Host smart-f025ab10-ce53-4256-9f4e-b49d07473fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1929367731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1929367731
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.820118281
Short name T410
Test name
Test status
Simulation time 334624206 ps
CPU time 17.75 seconds
Started Aug 16 06:31:06 PM PDT 24
Finished Aug 16 06:31:24 PM PDT 24
Peak memory 200688 kb
Host smart-0f097769-e99c-4dfc-8dd3-18333846eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820118281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.820118281
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.888630009
Short name T262
Test name
Test status
Simulation time 1502912742 ps
CPU time 246.95 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:35:17 PM PDT 24
Peak memory 637992 kb
Host smart-00061df7-ee7e-441f-af93-57da85afbc2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888630009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.888630009
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4232413466
Short name T168
Test name
Test status
Simulation time 7056817176 ps
CPU time 103.85 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:32:54 PM PDT 24
Peak memory 200752 kb
Host smart-ffaac450-519b-4264-b841-f5f5bcc66ed9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232413466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4232413466
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2748678475
Short name T387
Test name
Test status
Simulation time 355637640 ps
CPU time 5.5 seconds
Started Aug 16 06:31:09 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 200648 kb
Host smart-7e3e68df-d3e1-4663-adba-7de8028591df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748678475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2748678475
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2250287515
Short name T357
Test name
Test status
Simulation time 388184754 ps
CPU time 6.52 seconds
Started Aug 16 06:31:09 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 200604 kb
Host smart-e0c7400d-5ec3-455d-9306-c2314e958f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250287515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2250287515
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2424930660
Short name T133
Test name
Test status
Simulation time 25778310324 ps
CPU time 3328.36 seconds
Started Aug 16 06:31:11 PM PDT 24
Finished Aug 16 07:26:40 PM PDT 24
Peak memory 815296 kb
Host smart-bef0777c-2e19-46cb-a735-7e3a1a2f27eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424930660 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2424930660
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3535161651
Short name T504
Test name
Test status
Simulation time 3660712565 ps
CPU time 62 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:32:12 PM PDT 24
Peak memory 200748 kb
Host smart-0f2c2fec-e3bb-4bf6-9cd6-9e852a88bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535161651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3535161651
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2174492991
Short name T232
Test name
Test status
Simulation time 47547072 ps
CPU time 0.58 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:31:09 PM PDT 24
Peak memory 196756 kb
Host smart-3c9a72ea-2e03-46d8-b565-77c42ca6bbd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174492991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2174492991
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3333476482
Short name T244
Test name
Test status
Simulation time 208129380 ps
CPU time 3.37 seconds
Started Aug 16 06:31:09 PM PDT 24
Finished Aug 16 06:31:13 PM PDT 24
Peak memory 200524 kb
Host smart-8798a2e9-aea4-42e4-b77b-7f1d869f0da3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3333476482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3333476482
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3636118106
Short name T51
Test name
Test status
Simulation time 5334765253 ps
CPU time 49.3 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 217040 kb
Host smart-4f061cbb-d8d5-4994-aaef-2e9139e52cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636118106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3636118106
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3701247146
Short name T495
Test name
Test status
Simulation time 5291660340 ps
CPU time 906.17 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:46:16 PM PDT 24
Peak memory 684160 kb
Host smart-23f7f5f8-5bfe-4df2-b207-a4796cd7eae3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701247146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3701247146
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2102459587
Short name T229
Test name
Test status
Simulation time 1872141230 ps
CPU time 54.09 seconds
Started Aug 16 06:31:12 PM PDT 24
Finished Aug 16 06:32:06 PM PDT 24
Peak memory 200608 kb
Host smart-03903253-0621-466b-b4df-f54d121907c6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102459587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2102459587
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2344437267
Short name T498
Test name
Test status
Simulation time 3011311627 ps
CPU time 84.26 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:32:33 PM PDT 24
Peak memory 200724 kb
Host smart-cd264d64-e1d8-42dc-b4e3-fdcc3ce32eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344437267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2344437267
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3324563166
Short name T123
Test name
Test status
Simulation time 458016730 ps
CPU time 6.47 seconds
Started Aug 16 06:31:12 PM PDT 24
Finished Aug 16 06:31:18 PM PDT 24
Peak memory 200660 kb
Host smart-16d3da5f-a5d8-46cf-8ad1-f0880b8a3c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324563166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3324563166
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2745578853
Short name T217
Test name
Test status
Simulation time 263942093096 ps
CPU time 1698.02 seconds
Started Aug 16 06:31:08 PM PDT 24
Finished Aug 16 06:59:27 PM PDT 24
Peak memory 653492 kb
Host smart-9ddd3c19-af9a-4dd6-8239-f739f3b0bfd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745578853 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2745578853
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.182064720
Short name T385
Test name
Test status
Simulation time 6215157790 ps
CPU time 78.99 seconds
Started Aug 16 06:31:20 PM PDT 24
Finished Aug 16 06:32:39 PM PDT 24
Peak memory 200768 kb
Host smart-3137dd1a-0590-4664-9ebf-c1463d61cb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182064720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.182064720
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.675454656
Short name T354
Test name
Test status
Simulation time 10998667 ps
CPU time 0.58 seconds
Started Aug 16 06:31:14 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 195744 kb
Host smart-8e6365f0-56b9-4ea0-baa4-d2fc156f9bf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675454656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.675454656
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2550309919
Short name T423
Test name
Test status
Simulation time 533718993 ps
CPU time 14.24 seconds
Started Aug 16 06:31:07 PM PDT 24
Finished Aug 16 06:31:21 PM PDT 24
Peak memory 200588 kb
Host smart-7b43794b-98eb-4873-b200-404b5b761fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550309919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2550309919
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2795486274
Short name T317
Test name
Test status
Simulation time 4373652519 ps
CPU time 11.3 seconds
Started Aug 16 06:31:14 PM PDT 24
Finished Aug 16 06:31:25 PM PDT 24
Peak memory 200756 kb
Host smart-2b7b395f-1f50-473c-88e9-8d8872b9589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795486274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2795486274
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4278244131
Short name T68
Test name
Test status
Simulation time 5447493120 ps
CPU time 1034.11 seconds
Started Aug 16 06:31:19 PM PDT 24
Finished Aug 16 06:48:34 PM PDT 24
Peak memory 687932 kb
Host smart-058bc5df-d27c-4617-9c4e-fb1deb8ebb81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4278244131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4278244131
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.706863055
Short name T343
Test name
Test status
Simulation time 10568781111 ps
CPU time 91.1 seconds
Started Aug 16 06:31:20 PM PDT 24
Finished Aug 16 06:32:52 PM PDT 24
Peak memory 200724 kb
Host smart-28fef6bc-e35f-49bb-80ed-0645042fe652
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706863055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.706863055
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.352771149
Short name T38
Test name
Test status
Simulation time 45040779412 ps
CPU time 117.73 seconds
Started Aug 16 06:31:07 PM PDT 24
Finished Aug 16 06:33:05 PM PDT 24
Peak memory 200912 kb
Host smart-502498f7-bb37-4e19-a559-ffea9db0503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352771149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.352771149
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2932849461
Short name T268
Test name
Test status
Simulation time 210180496 ps
CPU time 9.61 seconds
Started Aug 16 06:31:10 PM PDT 24
Finished Aug 16 06:31:19 PM PDT 24
Peak memory 200668 kb
Host smart-2cf4923e-9dfe-47e5-b634-435ad72ef908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932849461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2932849461
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2686194637
Short name T26
Test name
Test status
Simulation time 20565043208 ps
CPU time 1706.38 seconds
Started Aug 16 06:31:15 PM PDT 24
Finished Aug 16 06:59:42 PM PDT 24
Peak memory 698864 kb
Host smart-43ab4f4e-a215-4967-82c0-a187e3586331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686194637 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2686194637
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4202190393
Short name T79
Test name
Test status
Simulation time 27787325236 ps
CPU time 87.63 seconds
Started Aug 16 06:31:17 PM PDT 24
Finished Aug 16 06:32:45 PM PDT 24
Peak memory 200732 kb
Host smart-c8e7f2df-b090-4008-abb8-461077ae9eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202190393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4202190393
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1812165291
Short name T433
Test name
Test status
Simulation time 83005170 ps
CPU time 0.58 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:29:57 PM PDT 24
Peak memory 197396 kb
Host smart-91ba8a88-d26f-40ae-9a6b-2888b51d169a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812165291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1812165291
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4256865543
Short name T184
Test name
Test status
Simulation time 133078019 ps
CPU time 6.87 seconds
Started Aug 16 06:29:45 PM PDT 24
Finished Aug 16 06:29:52 PM PDT 24
Peak memory 200724 kb
Host smart-7fe939bf-1162-4ba8-a785-a614f73d1051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4256865543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4256865543
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.578302072
Short name T222
Test name
Test status
Simulation time 5024400878 ps
CPU time 16.55 seconds
Started Aug 16 06:29:43 PM PDT 24
Finished Aug 16 06:30:00 PM PDT 24
Peak memory 200720 kb
Host smart-5954cf4e-6c0d-4f69-990f-d414f30d64f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578302072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.578302072
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2045267956
Short name T401
Test name
Test status
Simulation time 3754874950 ps
CPU time 622.2 seconds
Started Aug 16 06:29:43 PM PDT 24
Finished Aug 16 06:40:06 PM PDT 24
Peak memory 696360 kb
Host smart-dd20d7a5-6013-49d1-b7fc-e3289cf35222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2045267956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2045267956
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3740075424
Short name T252
Test name
Test status
Simulation time 19142127605 ps
CPU time 60.24 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:30:57 PM PDT 24
Peak memory 200776 kb
Host smart-680c409e-7989-451d-9fb5-9cb5906f5556
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740075424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3740075424
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1851849978
Short name T279
Test name
Test status
Simulation time 15047535134 ps
CPU time 181.56 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:32:59 PM PDT 24
Peak memory 200740 kb
Host smart-8be8f6ea-c6cd-4bce-aa4f-ae0cb2b8bffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851849978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1851849978
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4212702380
Short name T45
Test name
Test status
Simulation time 210952341 ps
CPU time 0.88 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:29:58 PM PDT 24
Peak memory 219024 kb
Host smart-fd291ee3-88c3-4f49-8416-fa746b3d5df5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212702380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4212702380
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2227505081
Short name T510
Test name
Test status
Simulation time 1083673410 ps
CPU time 5.14 seconds
Started Aug 16 06:29:43 PM PDT 24
Finished Aug 16 06:29:48 PM PDT 24
Peak memory 200680 kb
Host smart-e9db6e47-23d2-4217-b145-f745777170d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227505081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2227505081
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3446713474
Short name T346
Test name
Test status
Simulation time 66425410258 ps
CPU time 862.02 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:44:18 PM PDT 24
Peak memory 200764 kb
Host smart-1fb01f49-16df-4b07-8e35-b7129b6625d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446713474 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3446713474
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2812873138
Short name T176
Test name
Test status
Simulation time 4469220485 ps
CPU time 66.11 seconds
Started Aug 16 06:29:46 PM PDT 24
Finished Aug 16 06:30:52 PM PDT 24
Peak memory 200816 kb
Host smart-00ee7d37-b79a-4f36-ba51-3a8f1576fcee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2812873138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2812873138
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1839332042
Short name T163
Test name
Test status
Simulation time 17205147615 ps
CPU time 66.09 seconds
Started Aug 16 06:29:44 PM PDT 24
Finished Aug 16 06:30:50 PM PDT 24
Peak memory 200732 kb
Host smart-9524843d-d080-4cdd-8d8a-9720f17eb55f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1839332042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1839332042
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1273516307
Short name T436
Test name
Test status
Simulation time 5561521025 ps
CPU time 85.48 seconds
Started Aug 16 06:29:44 PM PDT 24
Finished Aug 16 06:31:10 PM PDT 24
Peak memory 200796 kb
Host smart-08083261-ab8b-4966-856a-752206d39b93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1273516307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1273516307
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2937741700
Short name T174
Test name
Test status
Simulation time 203426419864 ps
CPU time 662.7 seconds
Started Aug 16 06:29:55 PM PDT 24
Finished Aug 16 06:40:58 PM PDT 24
Peak memory 200744 kb
Host smart-e10e1b65-7553-4f63-9ea4-6e6aa9bdebc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2937741700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2937741700
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1531339008
Short name T414
Test name
Test status
Simulation time 209865525940 ps
CPU time 2738.34 seconds
Started Aug 16 06:29:45 PM PDT 24
Finished Aug 16 07:15:24 PM PDT 24
Peak memory 216220 kb
Host smart-fd683894-98b4-4c5b-8778-4d51b5fc593d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1531339008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1531339008
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2652344568
Short name T286
Test name
Test status
Simulation time 799321798058 ps
CPU time 2687.95 seconds
Started Aug 16 06:29:46 PM PDT 24
Finished Aug 16 07:14:35 PM PDT 24
Peak memory 216204 kb
Host smart-639edb67-1fde-4913-8aa1-2d8071d022c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2652344568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2652344568
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1179178109
Short name T439
Test name
Test status
Simulation time 5929066046 ps
CPU time 48.2 seconds
Started Aug 16 06:29:55 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 200728 kb
Host smart-1cb6ae96-7d31-4b6d-b8ff-98a36a64cf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179178109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1179178109
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2693141255
Short name T280
Test name
Test status
Simulation time 58848298 ps
CPU time 0.57 seconds
Started Aug 16 06:31:17 PM PDT 24
Finished Aug 16 06:31:17 PM PDT 24
Peak memory 195732 kb
Host smart-a6ee4c6a-a19c-4ce1-970f-e4c160bb6e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693141255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2693141255
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2302196232
Short name T25
Test name
Test status
Simulation time 6278634197 ps
CPU time 92.62 seconds
Started Aug 16 06:31:14 PM PDT 24
Finished Aug 16 06:32:47 PM PDT 24
Peak memory 200700 kb
Host smart-4bb7d38b-2570-4dc1-8563-2964ee544819
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2302196232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2302196232
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3998186986
Short name T362
Test name
Test status
Simulation time 13265740891 ps
CPU time 40.64 seconds
Started Aug 16 06:31:20 PM PDT 24
Finished Aug 16 06:32:01 PM PDT 24
Peak memory 200744 kb
Host smart-336a47e1-9afe-4e68-9e91-3a61149d911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998186986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3998186986
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.948962484
Short name T373
Test name
Test status
Simulation time 3066097763 ps
CPU time 604.73 seconds
Started Aug 16 06:31:19 PM PDT 24
Finished Aug 16 06:41:24 PM PDT 24
Peak memory 698164 kb
Host smart-da72de86-be46-4a2f-98c8-ee2a59017eec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948962484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.948962484
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1841799737
Short name T322
Test name
Test status
Simulation time 988409740 ps
CPU time 53.85 seconds
Started Aug 16 06:31:18 PM PDT 24
Finished Aug 16 06:32:12 PM PDT 24
Peak memory 200632 kb
Host smart-fd3dac02-1e2d-4784-95e5-2e1dc85be6dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841799737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1841799737
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3595614454
Short name T364
Test name
Test status
Simulation time 3069064677 ps
CPU time 51.78 seconds
Started Aug 16 06:31:15 PM PDT 24
Finished Aug 16 06:32:07 PM PDT 24
Peak memory 200720 kb
Host smart-e7c51a3e-9d8a-4298-8dc6-a4613d9bec85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595614454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3595614454
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.300448735
Short name T395
Test name
Test status
Simulation time 952555731 ps
CPU time 11.34 seconds
Started Aug 16 06:31:14 PM PDT 24
Finished Aug 16 06:31:26 PM PDT 24
Peak memory 200720 kb
Host smart-a1779362-d3c2-4851-8a4a-d91cc8d08f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300448735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.300448735
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3933915584
Short name T173
Test name
Test status
Simulation time 6166120887 ps
CPU time 38.9 seconds
Started Aug 16 06:31:16 PM PDT 24
Finished Aug 16 06:31:55 PM PDT 24
Peak memory 200620 kb
Host smart-d7094b17-adbb-4c4b-b16d-91f0901c56de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933915584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3933915584
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3319047385
Short name T441
Test name
Test status
Simulation time 87765125 ps
CPU time 0.62 seconds
Started Aug 16 06:31:15 PM PDT 24
Finished Aug 16 06:31:16 PM PDT 24
Peak memory 196376 kb
Host smart-60e6969a-74d5-4f3a-96e9-80d0a2a18577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319047385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3319047385
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.472908282
Short name T278
Test name
Test status
Simulation time 1209510809 ps
CPU time 67.36 seconds
Started Aug 16 06:31:20 PM PDT 24
Finished Aug 16 06:32:28 PM PDT 24
Peak memory 200664 kb
Host smart-af7227ab-0806-4f41-92ef-83440bcce167
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472908282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.472908282
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3308040027
Short name T220
Test name
Test status
Simulation time 15068203655 ps
CPU time 45.37 seconds
Started Aug 16 06:31:15 PM PDT 24
Finished Aug 16 06:32:00 PM PDT 24
Peak memory 200700 kb
Host smart-fae7f9fc-2ff5-4646-b5f3-1ef4c56550bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308040027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3308040027
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2308565677
Short name T382
Test name
Test status
Simulation time 345610681 ps
CPU time 33.56 seconds
Started Aug 16 06:31:17 PM PDT 24
Finished Aug 16 06:31:51 PM PDT 24
Peak memory 248204 kb
Host smart-1c45dad9-443a-4780-9103-93cf271e3eff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308565677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2308565677
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.71666659
Short name T265
Test name
Test status
Simulation time 2496892608 ps
CPU time 91.24 seconds
Started Aug 16 06:31:18 PM PDT 24
Finished Aug 16 06:32:49 PM PDT 24
Peak memory 200732 kb
Host smart-d2f93543-2b90-4d1d-98a7-902d2288597d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71666659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.71666659
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.685034203
Short name T269
Test name
Test status
Simulation time 7936188559 ps
CPU time 35.7 seconds
Started Aug 16 06:31:16 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 200716 kb
Host smart-c088b6a2-9f67-4e2a-ad19-350f57db3a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685034203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.685034203
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2350768503
Short name T462
Test name
Test status
Simulation time 50379850 ps
CPU time 0.74 seconds
Started Aug 16 06:31:19 PM PDT 24
Finished Aug 16 06:31:19 PM PDT 24
Peak memory 198456 kb
Host smart-333b6be3-26f4-4899-865b-6663f0dbfc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350768503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2350768503
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2548352322
Short name T37
Test name
Test status
Simulation time 15235833402 ps
CPU time 179.93 seconds
Started Aug 16 06:31:17 PM PDT 24
Finished Aug 16 06:34:17 PM PDT 24
Peak memory 217076 kb
Host smart-5a02d04a-5a17-4289-8c99-c3c1b6c9f840
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548352322 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2548352322
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4249153597
Short name T114
Test name
Test status
Simulation time 3066975034 ps
CPU time 31.7 seconds
Started Aug 16 06:31:20 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 200740 kb
Host smart-d2cedcd9-9b32-473a-9998-a9c25db4b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249153597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4249153597
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.4047498512
Short name T256
Test name
Test status
Simulation time 13879494 ps
CPU time 0.6 seconds
Started Aug 16 06:31:21 PM PDT 24
Finished Aug 16 06:31:22 PM PDT 24
Peak memory 196476 kb
Host smart-af94b339-3307-4577-9f66-eb9e2efa8572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047498512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4047498512
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.4022493564
Short name T478
Test name
Test status
Simulation time 613667350 ps
CPU time 34.12 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 200648 kb
Host smart-42a572e3-3885-4d06-9f75-e7fb55c3b998
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022493564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.4022493564
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2478251897
Short name T82
Test name
Test status
Simulation time 6351221957 ps
CPU time 55.33 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 06:32:18 PM PDT 24
Peak memory 200752 kb
Host smart-5b150ce2-2239-4500-bd81-432e9f0c9dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478251897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2478251897
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_error.1376865186
Short name T418
Test name
Test status
Simulation time 9417188234 ps
CPU time 122.73 seconds
Started Aug 16 06:31:21 PM PDT 24
Finished Aug 16 06:33:23 PM PDT 24
Peak memory 200680 kb
Host smart-bfe92d60-4976-4b70-8da4-a0f4f0e93f6d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376865186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1376865186
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1381415831
Short name T481
Test name
Test status
Simulation time 1838740803 ps
CPU time 29.56 seconds
Started Aug 16 06:31:14 PM PDT 24
Finished Aug 16 06:31:43 PM PDT 24
Peak memory 200688 kb
Host smart-c7d7d1a0-38be-4378-ad4d-a6b93d0150e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381415831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1381415831
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2531090905
Short name T277
Test name
Test status
Simulation time 533907515 ps
CPU time 8.69 seconds
Started Aug 16 06:31:15 PM PDT 24
Finished Aug 16 06:31:24 PM PDT 24
Peak memory 200668 kb
Host smart-6197f28b-a1d4-4478-b6de-97b815bafb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531090905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2531090905
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1146911175
Short name T493
Test name
Test status
Simulation time 114049517516 ps
CPU time 3630.6 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 07:31:55 PM PDT 24
Peak memory 807044 kb
Host smart-b00b2224-a9d6-46a7-a4ab-d94a232ec49c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146911175 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1146911175
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1312848328
Short name T388
Test name
Test status
Simulation time 32841186341 ps
CPU time 142.72 seconds
Started Aug 16 06:31:21 PM PDT 24
Finished Aug 16 06:33:44 PM PDT 24
Peak memory 200732 kb
Host smart-d2bd1eda-98fe-45bd-b85b-0b122a61b2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312848328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1312848328
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.923514116
Short name T476
Test name
Test status
Simulation time 43186575 ps
CPU time 0.58 seconds
Started Aug 16 06:31:22 PM PDT 24
Finished Aug 16 06:31:23 PM PDT 24
Peak memory 196728 kb
Host smart-45ea9d18-1d1b-40b9-97ef-1bdf0e288bf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923514116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.923514116
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1836982324
Short name T400
Test name
Test status
Simulation time 776331440 ps
CPU time 48.91 seconds
Started Aug 16 06:31:21 PM PDT 24
Finished Aug 16 06:32:10 PM PDT 24
Peak memory 200736 kb
Host smart-c513c888-e238-4949-b56d-d14ae55c2e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836982324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1836982324
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3736665694
Short name T134
Test name
Test status
Simulation time 8046907130 ps
CPU time 54.96 seconds
Started Aug 16 06:31:22 PM PDT 24
Finished Aug 16 06:32:17 PM PDT 24
Peak memory 200732 kb
Host smart-7e2fbcc2-387f-4012-9949-d959b99509ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736665694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3736665694
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.3455668606
Short name T198
Test name
Test status
Simulation time 1906175130 ps
CPU time 51.7 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 06:32:15 PM PDT 24
Peak memory 306880 kb
Host smart-e35302e7-b352-485c-9790-8676d4302159
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3455668606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3455668606
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.947221851
Short name T432
Test name
Test status
Simulation time 1784977146 ps
CPU time 101.28 seconds
Started Aug 16 06:31:22 PM PDT 24
Finished Aug 16 06:33:03 PM PDT 24
Peak memory 200612 kb
Host smart-8e6c7163-7052-417f-b2c8-9c95cfec73b2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947221851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.947221851
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2951644788
Short name T530
Test name
Test status
Simulation time 2084080902 ps
CPU time 114.01 seconds
Started Aug 16 06:31:22 PM PDT 24
Finished Aug 16 06:33:16 PM PDT 24
Peak memory 200636 kb
Host smart-02df9277-eeea-46c9-af71-fd4a0bf09cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951644788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2951644788
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1165122687
Short name T233
Test name
Test status
Simulation time 741896650 ps
CPU time 3.41 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 06:31:26 PM PDT 24
Peak memory 200616 kb
Host smart-78a67b27-51f3-45d1-88bf-37fd5e4c1550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165122687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1165122687
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2483490676
Short name T241
Test name
Test status
Simulation time 11537825846 ps
CPU time 218.78 seconds
Started Aug 16 06:31:24 PM PDT 24
Finished Aug 16 06:35:03 PM PDT 24
Peak memory 208944 kb
Host smart-aee86302-2f79-4369-9aaa-4000885c26da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483490676 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2483490676
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4206617851
Short name T27
Test name
Test status
Simulation time 4554603335 ps
CPU time 45.78 seconds
Started Aug 16 06:31:23 PM PDT 24
Finished Aug 16 06:32:09 PM PDT 24
Peak memory 200772 kb
Host smart-e9e139bf-f1ba-4bcd-b200-637ee66deb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206617851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4206617851
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.122048747
Short name T525
Test name
Test status
Simulation time 72717382 ps
CPU time 0.61 seconds
Started Aug 16 06:31:33 PM PDT 24
Finished Aug 16 06:31:34 PM PDT 24
Peak memory 196792 kb
Host smart-703217c3-600b-462c-9f93-f4ccb3b1dd03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122048747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.122048747
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2443010908
Short name T407
Test name
Test status
Simulation time 513726009 ps
CPU time 30.07 seconds
Started Aug 16 06:31:32 PM PDT 24
Finished Aug 16 06:32:02 PM PDT 24
Peak memory 208832 kb
Host smart-36130d84-b040-4a75-95f0-e800ee37c138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443010908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2443010908
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2380115724
Short name T282
Test name
Test status
Simulation time 2693244668 ps
CPU time 40.77 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:32:12 PM PDT 24
Peak memory 200776 kb
Host smart-62ada64f-37ab-4e6b-b99e-ffbb39e24ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380115724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2380115724
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2120357903
Short name T170
Test name
Test status
Simulation time 6104200716 ps
CPU time 1316.87 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:53:28 PM PDT 24
Peak memory 746184 kb
Host smart-b7fc0596-d740-400e-a7bd-2bfd87878697
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2120357903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2120357903
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3818904284
Short name T458
Test name
Test status
Simulation time 10858897269 ps
CPU time 187.09 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:34:38 PM PDT 24
Peak memory 200808 kb
Host smart-6ffa7081-02c7-48b5-9521-18682ecafdbe
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818904284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3818904284
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4003233081
Short name T486
Test name
Test status
Simulation time 33063218444 ps
CPU time 81.18 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:32:53 PM PDT 24
Peak memory 200728 kb
Host smart-2eb2e285-8384-459e-9100-41f9acf449dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003233081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4003233081
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1659052710
Short name T316
Test name
Test status
Simulation time 133949429 ps
CPU time 6.17 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:31:38 PM PDT 24
Peak memory 200672 kb
Host smart-751df13a-afda-4b76-ac8d-288b3099bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659052710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1659052710
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.697340839
Short name T466
Test name
Test status
Simulation time 6950136827 ps
CPU time 99.69 seconds
Started Aug 16 06:31:48 PM PDT 24
Finished Aug 16 06:33:28 PM PDT 24
Peak memory 200788 kb
Host smart-cdf12a52-3272-43b3-a81d-bcbda76f08f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697340839 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.697340839
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4097527859
Short name T403
Test name
Test status
Simulation time 5710924538 ps
CPU time 106.57 seconds
Started Aug 16 06:31:34 PM PDT 24
Finished Aug 16 06:33:21 PM PDT 24
Peak memory 200728 kb
Host smart-2c09cbd7-77fd-4b7f-abbd-1c4b985d72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097527859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4097527859
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3634432552
Short name T148
Test name
Test status
Simulation time 16527883 ps
CPU time 0.61 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:31:39 PM PDT 24
Peak memory 196752 kb
Host smart-82622cc6-bd51-4ac6-88e9-b84009fced2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634432552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3634432552
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2531201070
Short name T429
Test name
Test status
Simulation time 668494949 ps
CPU time 14.04 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:31:46 PM PDT 24
Peak memory 200564 kb
Host smart-bac995f3-17b1-415c-82cd-d5198bdcd178
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531201070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2531201070
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3230541064
Short name T412
Test name
Test status
Simulation time 2286065320 ps
CPU time 10.84 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:31:42 PM PDT 24
Peak memory 200740 kb
Host smart-ba780fd7-550b-4819-9cd7-9f2cb7bdae81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230541064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3230541064
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1636460048
Short name T147
Test name
Test status
Simulation time 9090944160 ps
CPU time 129.02 seconds
Started Aug 16 06:31:30 PM PDT 24
Finished Aug 16 06:33:39 PM PDT 24
Peak memory 600032 kb
Host smart-dfe94ba4-7398-4fba-a581-214a67c510e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1636460048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1636460048
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3600956543
Short name T40
Test name
Test status
Simulation time 13872387318 ps
CPU time 178.19 seconds
Started Aug 16 06:31:33 PM PDT 24
Finished Aug 16 06:34:32 PM PDT 24
Peak memory 200720 kb
Host smart-1e933b41-dbd5-40b7-9b3f-a05a2e9604a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600956543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3600956543
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3013000518
Short name T291
Test name
Test status
Simulation time 6060577101 ps
CPU time 17.39 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:31:48 PM PDT 24
Peak memory 200732 kb
Host smart-9d3de3f6-4022-4638-9332-bd79d3086d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013000518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3013000518
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.4120150400
Short name T518
Test name
Test status
Simulation time 1371521975 ps
CPU time 9.01 seconds
Started Aug 16 06:31:31 PM PDT 24
Finished Aug 16 06:31:41 PM PDT 24
Peak memory 200672 kb
Host smart-2f3cec14-f25e-412c-8c59-26de54af5469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120150400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.4120150400
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2920474203
Short name T361
Test name
Test status
Simulation time 356837258713 ps
CPU time 3626.45 seconds
Started Aug 16 06:31:38 PM PDT 24
Finished Aug 16 07:32:05 PM PDT 24
Peak memory 749248 kb
Host smart-75faa4a8-7b91-4bbe-84d7-6e5c783b3b97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920474203 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2920474203
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1972644095
Short name T402
Test name
Test status
Simulation time 2072079665 ps
CPU time 86.94 seconds
Started Aug 16 06:31:35 PM PDT 24
Finished Aug 16 06:33:02 PM PDT 24
Peak memory 200668 kb
Host smart-d896a306-975b-4472-9016-ec21270e497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972644095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1972644095
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1525301435
Short name T211
Test name
Test status
Simulation time 21509631 ps
CPU time 0.63 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:31:40 PM PDT 24
Peak memory 196728 kb
Host smart-726aefa0-bf89-4951-aa81-ff3585c61152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525301435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1525301435
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.133218413
Short name T318
Test name
Test status
Simulation time 971433096 ps
CPU time 29.58 seconds
Started Aug 16 06:31:40 PM PDT 24
Finished Aug 16 06:32:10 PM PDT 24
Peak memory 200688 kb
Host smart-9f29f9f0-8eac-4181-98e6-46cfa22bd874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133218413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.133218413
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2812125535
Short name T169
Test name
Test status
Simulation time 3982744406 ps
CPU time 38.49 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:32:17 PM PDT 24
Peak memory 200712 kb
Host smart-1bac7fdf-a21c-482b-8ea9-8d9ecde8a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812125535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2812125535
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1141515543
Short name T375
Test name
Test status
Simulation time 628927133 ps
CPU time 88.64 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:33:08 PM PDT 24
Peak memory 439148 kb
Host smart-800763fe-49ea-4099-9812-51ca24ad0df2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141515543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1141515543
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1343450792
Short name T151
Test name
Test status
Simulation time 3929731373 ps
CPU time 46.95 seconds
Started Aug 16 06:31:40 PM PDT 24
Finished Aug 16 06:32:27 PM PDT 24
Peak memory 200748 kb
Host smart-2f53c6b9-80e1-4b3b-a196-077777999f4f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343450792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1343450792
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3552678366
Short name T408
Test name
Test status
Simulation time 17310515857 ps
CPU time 225.07 seconds
Started Aug 16 06:31:40 PM PDT 24
Finished Aug 16 06:35:25 PM PDT 24
Peak memory 217120 kb
Host smart-9d4b65fe-0248-4940-a574-a3660b9ff850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552678366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3552678366
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.24685884
Short name T287
Test name
Test status
Simulation time 72483290 ps
CPU time 0.68 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:31:40 PM PDT 24
Peak memory 197524 kb
Host smart-00f6f7ca-1c5c-4097-9797-7171437fcd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24685884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.24685884
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.413767100
Short name T78
Test name
Test status
Simulation time 751917865484 ps
CPU time 481.48 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:39:41 PM PDT 24
Peak memory 200620 kb
Host smart-933a7b3b-5cfd-4a07-90b6-d5c7949690f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413767100 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.413767100
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.521440391
Short name T52
Test name
Test status
Simulation time 5839351212 ps
CPU time 100.26 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:33:19 PM PDT 24
Peak memory 200792 kb
Host smart-1818f7bd-0beb-4942-aa62-021029598f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521440391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.521440391
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3368402577
Short name T377
Test name
Test status
Simulation time 15972696 ps
CPU time 0.58 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:31:40 PM PDT 24
Peak memory 196756 kb
Host smart-f80e64de-1e88-47c7-a729-1d5fbe93c213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368402577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3368402577
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.285182755
Short name T426
Test name
Test status
Simulation time 5439249663 ps
CPU time 83.15 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:33:03 PM PDT 24
Peak memory 200732 kb
Host smart-468f5683-8def-4068-8305-1ea816d5d8bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285182755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.285182755
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4043697334
Short name T138
Test name
Test status
Simulation time 199341416 ps
CPU time 10.59 seconds
Started Aug 16 06:31:38 PM PDT 24
Finished Aug 16 06:31:49 PM PDT 24
Peak memory 200644 kb
Host smart-c79ae64c-98e4-424f-bc9a-5fb71a72bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043697334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4043697334
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1141292868
Short name T348
Test name
Test status
Simulation time 4393130121 ps
CPU time 819.46 seconds
Started Aug 16 06:31:40 PM PDT 24
Finished Aug 16 06:45:20 PM PDT 24
Peak memory 757052 kb
Host smart-54179e53-b650-4d0e-8c58-9ac9a5186c8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1141292868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1141292868
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4064567650
Short name T47
Test name
Test status
Simulation time 267970884 ps
CPU time 4.45 seconds
Started Aug 16 06:31:38 PM PDT 24
Finished Aug 16 06:31:42 PM PDT 24
Peak memory 200624 kb
Host smart-9ce2deb2-1f2b-4606-b7d0-15e42cdcaeaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064567650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4064567650
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2865885759
Short name T356
Test name
Test status
Simulation time 3889014117 ps
CPU time 48.75 seconds
Started Aug 16 06:31:38 PM PDT 24
Finished Aug 16 06:32:27 PM PDT 24
Peak memory 200792 kb
Host smart-fb47e46f-0629-402b-a8b6-090c4bd5ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865885759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2865885759
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.266489688
Short name T300
Test name
Test status
Simulation time 1001567870 ps
CPU time 6.62 seconds
Started Aug 16 06:31:47 PM PDT 24
Finished Aug 16 06:31:54 PM PDT 24
Peak memory 200684 kb
Host smart-4fa6691a-9211-429c-b339-5f873177b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266489688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.266489688
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.1929253476
Short name T72
Test name
Test status
Simulation time 129181899120 ps
CPU time 3702.12 seconds
Started Aug 16 06:31:41 PM PDT 24
Finished Aug 16 07:33:24 PM PDT 24
Peak memory 801156 kb
Host smart-824713bf-bb1d-4eab-8106-8029b9647915
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929253476 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.1929253476
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2941801412
Short name T254
Test name
Test status
Simulation time 248318548 ps
CPU time 9.43 seconds
Started Aug 16 06:31:39 PM PDT 24
Finished Aug 16 06:31:49 PM PDT 24
Peak memory 200564 kb
Host smart-113a41ea-8559-43df-83fe-eb4515cbe95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941801412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2941801412
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.641904011
Short name T396
Test name
Test status
Simulation time 10914256 ps
CPU time 0.57 seconds
Started Aug 16 06:31:51 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 195580 kb
Host smart-a126ab47-7ce0-4d64-8114-00f306ca4dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641904011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.641904011
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2405873446
Short name T191
Test name
Test status
Simulation time 620665599 ps
CPU time 17.26 seconds
Started Aug 16 06:31:38 PM PDT 24
Finished Aug 16 06:31:55 PM PDT 24
Peak memory 200624 kb
Host smart-d78812a2-7951-4b8d-960c-997007dcb4a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405873446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2405873446
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1973744519
Short name T216
Test name
Test status
Simulation time 762024284 ps
CPU time 10.46 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 200656 kb
Host smart-8aead64d-e440-4df5-90c6-2bd8e277647f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973744519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1973744519
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.954581610
Short name T246
Test name
Test status
Simulation time 7240228957 ps
CPU time 236.14 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 06:35:42 PM PDT 24
Peak memory 623128 kb
Host smart-0142d227-291c-43a6-93ad-295d58e904d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954581610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.954581610
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2438377901
Short name T312
Test name
Test status
Simulation time 34354211871 ps
CPU time 193.22 seconds
Started Aug 16 06:31:48 PM PDT 24
Finished Aug 16 06:35:02 PM PDT 24
Peak memory 200788 kb
Host smart-e06b63b1-849d-470d-998b-0db6653595fb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438377901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2438377901
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1692367090
Short name T260
Test name
Test status
Simulation time 15398572549 ps
CPU time 139.99 seconds
Started Aug 16 06:31:37 PM PDT 24
Finished Aug 16 06:33:58 PM PDT 24
Peak memory 200768 kb
Host smart-73ff44e8-9ed2-4269-8630-e7fea743614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692367090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1692367090
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1204210370
Short name T438
Test name
Test status
Simulation time 561374964 ps
CPU time 7.36 seconds
Started Aug 16 06:31:41 PM PDT 24
Finished Aug 16 06:31:48 PM PDT 24
Peak memory 200660 kb
Host smart-09aef4e6-753e-413c-9374-ca479ffe9a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204210370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1204210370
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1746326440
Short name T74
Test name
Test status
Simulation time 99480064033 ps
CPU time 1868.61 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 07:02:55 PM PDT 24
Peak memory 715984 kb
Host smart-16f98935-74ac-4c2c-be05-54334450d53b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746326440 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1746326440
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.830247978
Short name T85
Test name
Test status
Simulation time 7336053105 ps
CPU time 97.02 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 06:33:23 PM PDT 24
Peak memory 200636 kb
Host smart-b47fbc36-2d92-4a1e-b87d-06bb03798ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830247978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.830247978
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3304563849
Short name T447
Test name
Test status
Simulation time 84437799 ps
CPU time 0.58 seconds
Started Aug 16 06:31:51 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 196404 kb
Host smart-b0111aa8-da89-4c06-ab72-442c3cf0ee75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304563849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3304563849
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1115729357
Short name T336
Test name
Test status
Simulation time 946992143 ps
CPU time 55.3 seconds
Started Aug 16 06:31:47 PM PDT 24
Finished Aug 16 06:32:43 PM PDT 24
Peak memory 200660 kb
Host smart-92c854e5-69cd-4d57-bbe2-fc0b12c04016
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115729357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1115729357
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.202712776
Short name T224
Test name
Test status
Simulation time 656496254 ps
CPU time 9.08 seconds
Started Aug 16 06:31:45 PM PDT 24
Finished Aug 16 06:31:54 PM PDT 24
Peak memory 200632 kb
Host smart-b50211d8-461f-4ee7-9d8a-f2c5494e9f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202712776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.202712776
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1617384733
Short name T164
Test name
Test status
Simulation time 7851430760 ps
CPU time 382.88 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 06:38:09 PM PDT 24
Peak memory 483368 kb
Host smart-4ed13e68-7016-4605-baf7-9c2ba874cc75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617384733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1617384733
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3184792743
Short name T464
Test name
Test status
Simulation time 8130778244 ps
CPU time 74.7 seconds
Started Aug 16 06:31:48 PM PDT 24
Finished Aug 16 06:33:03 PM PDT 24
Peak memory 200740 kb
Host smart-ec633415-b383-4e06-a35d-20deadc0370e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184792743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3184792743
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1030586990
Short name T529
Test name
Test status
Simulation time 10884856384 ps
CPU time 208.01 seconds
Started Aug 16 06:31:47 PM PDT 24
Finished Aug 16 06:35:15 PM PDT 24
Peak memory 217208 kb
Host smart-5b27cc87-365f-4cff-8445-9a2fd68b9705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030586990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1030586990
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1254499844
Short name T507
Test name
Test status
Simulation time 1434536134 ps
CPU time 12.54 seconds
Started Aug 16 06:31:51 PM PDT 24
Finished Aug 16 06:32:04 PM PDT 24
Peak memory 200692 kb
Host smart-e4917d2e-6e85-404b-8615-047796fdd611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254499844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1254499844
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4133190993
Short name T445
Test name
Test status
Simulation time 136006901242 ps
CPU time 781.44 seconds
Started Aug 16 06:31:49 PM PDT 24
Finished Aug 16 06:44:50 PM PDT 24
Peak memory 451268 kb
Host smart-ce93bdb4-f79d-40b4-8f7b-a575792d9574
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133190993 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4133190993
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.964532940
Short name T86
Test name
Test status
Simulation time 15375904881 ps
CPU time 53.48 seconds
Started Aug 16 06:31:46 PM PDT 24
Finished Aug 16 06:32:39 PM PDT 24
Peak memory 200712 kb
Host smart-dade7017-37e2-448d-8545-806eddd3bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964532940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.964532940
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2192054520
Short name T428
Test name
Test status
Simulation time 21352139 ps
CPU time 0.59 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:29:57 PM PDT 24
Peak memory 196484 kb
Host smart-1c493f13-e736-488e-bfb1-ca628ac089dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192054520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2192054520
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1657221482
Short name T204
Test name
Test status
Simulation time 2715081519 ps
CPU time 37.02 seconds
Started Aug 16 06:29:54 PM PDT 24
Finished Aug 16 06:30:31 PM PDT 24
Peak memory 200780 kb
Host smart-115feef3-eb60-4b99-a29c-6075f26bdfc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657221482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1657221482
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1117316414
Short name T30
Test name
Test status
Simulation time 4715080169 ps
CPU time 26.78 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 200704 kb
Host smart-e1c2556a-8672-4a8a-8012-de387378a085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117316414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1117316414
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.468996281
Short name T522
Test name
Test status
Simulation time 12336263463 ps
CPU time 1081.75 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:48:00 PM PDT 24
Peak memory 745856 kb
Host smart-d229c64d-0c88-446b-ad21-7bc0e16dcc53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=468996281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.468996281
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1214464048
Short name T369
Test name
Test status
Simulation time 8251250815 ps
CPU time 246.05 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:34:02 PM PDT 24
Peak memory 200740 kb
Host smart-1475a405-7ed8-4d89-b59e-0d497f7452d9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214464048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1214464048
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3232799162
Short name T371
Test name
Test status
Simulation time 5811755011 ps
CPU time 100.21 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:31:38 PM PDT 24
Peak memory 200740 kb
Host smart-8869fa01-83eb-4fa9-9bb4-e0af7e96e13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232799162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3232799162
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3801197757
Short name T46
Test name
Test status
Simulation time 63263422 ps
CPU time 0.89 seconds
Started Aug 16 06:29:55 PM PDT 24
Finished Aug 16 06:29:56 PM PDT 24
Peak memory 219024 kb
Host smart-369f2590-0963-45cf-a1d4-e11fb337d807
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801197757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3801197757
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1737933761
Short name T48
Test name
Test status
Simulation time 268434896 ps
CPU time 12.02 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:30:09 PM PDT 24
Peak memory 200692 kb
Host smart-ace223d7-140c-4d34-9cab-8a9909a483cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737933761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1737933761
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2346960512
Short name T499
Test name
Test status
Simulation time 234313428 ps
CPU time 0.95 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:29:57 PM PDT 24
Peak memory 199396 kb
Host smart-96347a96-a801-4ef6-a91b-111d90b33606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346960512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2346960512
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2680930717
Short name T22
Test name
Test status
Simulation time 6439421508 ps
CPU time 171.01 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 209064 kb
Host smart-eeffc8c8-21e0-4442-8829-e4ec51f717b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2680930717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2680930717
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1422276684
Short name T370
Test name
Test status
Simulation time 6987152343 ps
CPU time 63.73 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:31:00 PM PDT 24
Peak memory 200696 kb
Host smart-40cb630c-8061-452f-8b68-790a74579a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1422276684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1422276684
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.3501400583
Short name T448
Test name
Test status
Simulation time 53602009934 ps
CPU time 100.51 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:31:39 PM PDT 24
Peak memory 200724 kb
Host smart-0eca2899-cd41-43ff-9d3a-ab144b528149
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3501400583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3501400583
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.56380981
Short name T374
Test name
Test status
Simulation time 37610107304 ps
CPU time 93.17 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:31:32 PM PDT 24
Peak memory 200712 kb
Host smart-72bd3571-31de-43da-87be-2c3beb975661
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=56380981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.56380981
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3112838464
Short name T203
Test name
Test status
Simulation time 9633977014 ps
CPU time 548.24 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:39:04 PM PDT 24
Peak memory 200720 kb
Host smart-23da776d-a624-4aa5-916a-7474e94b0ba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3112838464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3112838464
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.4151306126
Short name T271
Test name
Test status
Simulation time 589823400387 ps
CPU time 2413.83 seconds
Started Aug 16 06:29:55 PM PDT 24
Finished Aug 16 07:10:09 PM PDT 24
Peak memory 216220 kb
Host smart-21fd3603-d012-445f-a1a7-47f20c37e1c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4151306126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.4151306126
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3561095584
Short name T80
Test name
Test status
Simulation time 434151201802 ps
CPU time 2546.02 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 07:12:29 PM PDT 24
Peak memory 216976 kb
Host smart-f32f983c-4faa-4d89-8cfa-1aa6c8244fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3561095584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3561095584
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1031185425
Short name T451
Test name
Test status
Simulation time 5134556182 ps
CPU time 31.05 seconds
Started Aug 16 06:29:55 PM PDT 24
Finished Aug 16 06:30:26 PM PDT 24
Peak memory 200732 kb
Host smart-f7f5118f-16a1-4c9b-9573-e5ac529e9985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031185425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1031185425
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2786031086
Short name T404
Test name
Test status
Simulation time 12588103 ps
CPU time 0.57 seconds
Started Aug 16 06:31:52 PM PDT 24
Finished Aug 16 06:31:53 PM PDT 24
Peak memory 196400 kb
Host smart-857a2f3d-6a34-4c06-b232-cbe8c17e3ff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786031086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2786031086
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.727676622
Short name T4
Test name
Test status
Simulation time 1148211000 ps
CPU time 60.08 seconds
Started Aug 16 06:32:00 PM PDT 24
Finished Aug 16 06:33:00 PM PDT 24
Peak memory 200648 kb
Host smart-fb44e2b0-a2c6-40d1-9e03-51ac14ba071f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=727676622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.727676622
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4160107552
Short name T503
Test name
Test status
Simulation time 357813206 ps
CPU time 19.33 seconds
Started Aug 16 06:31:56 PM PDT 24
Finished Aug 16 06:32:15 PM PDT 24
Peak memory 200612 kb
Host smart-9c70d6d4-9a44-4ed7-84c3-4444b5d0df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160107552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4160107552
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3019583899
Short name T194
Test name
Test status
Simulation time 10794337950 ps
CPU time 388.07 seconds
Started Aug 16 06:31:52 PM PDT 24
Finished Aug 16 06:38:21 PM PDT 24
Peak memory 491400 kb
Host smart-ad784960-5710-4cd3-8460-8ed2d900d7d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019583899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3019583899
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3326609286
Short name T152
Test name
Test status
Simulation time 3999268402 ps
CPU time 105.85 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:33:39 PM PDT 24
Peak memory 200728 kb
Host smart-a7af813f-176a-4e81-8315-a5bd6b67a6f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326609286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3326609286
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.516756429
Short name T23
Test name
Test status
Simulation time 28212219410 ps
CPU time 39.62 seconds
Started Aug 16 06:31:45 PM PDT 24
Finished Aug 16 06:32:25 PM PDT 24
Peak memory 200776 kb
Host smart-e6ddd275-5f41-468f-9bbf-ade370385c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516756429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.516756429
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1694367704
Short name T389
Test name
Test status
Simulation time 1806868788 ps
CPU time 15.13 seconds
Started Aug 16 06:31:51 PM PDT 24
Finished Aug 16 06:32:06 PM PDT 24
Peak memory 200684 kb
Host smart-b26da2c1-1e4c-4e9b-827c-cb587b631b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694367704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1694367704
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2171901042
Short name T508
Test name
Test status
Simulation time 7502663783 ps
CPU time 308.56 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:37:03 PM PDT 24
Peak memory 367732 kb
Host smart-c4700511-9a56-4006-b86e-7daa79a15542
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171901042 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2171901042
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3362063248
Short name T425
Test name
Test status
Simulation time 59763440805 ps
CPU time 130.73 seconds
Started Aug 16 06:31:55 PM PDT 24
Finished Aug 16 06:34:06 PM PDT 24
Peak memory 200832 kb
Host smart-f0bc41ed-1872-4027-9e69-6ee4d60f0477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362063248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3362063248
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.6009657
Short name T17
Test name
Test status
Simulation time 48450791 ps
CPU time 0.59 seconds
Started Aug 16 06:31:59 PM PDT 24
Finished Aug 16 06:32:00 PM PDT 24
Peak memory 196488 kb
Host smart-89f9fded-9ff3-458e-b0cd-e5f15d27f796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6009657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.6009657
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3601164812
Short name T130
Test name
Test status
Simulation time 2324193798 ps
CPU time 67.16 seconds
Started Aug 16 06:31:58 PM PDT 24
Finished Aug 16 06:33:06 PM PDT 24
Peak memory 200664 kb
Host smart-b234fff2-ad34-482a-9725-3450f7091cfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601164812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3601164812
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2147758898
Short name T156
Test name
Test status
Simulation time 3160461676 ps
CPU time 54.87 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:32:49 PM PDT 24
Peak memory 200744 kb
Host smart-23c8ade7-f7b2-463d-a9de-e6534dd79bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147758898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2147758898
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2228317771
Short name T485
Test name
Test status
Simulation time 19690319319 ps
CPU time 1053.12 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:49:27 PM PDT 24
Peak memory 768424 kb
Host smart-5d510b23-4f69-4b05-95c0-fffea86ca381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228317771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2228317771
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3250845056
Short name T331
Test name
Test status
Simulation time 2789882170 ps
CPU time 151 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:34:25 PM PDT 24
Peak memory 200720 kb
Host smart-ec939e98-e74a-437b-9f5e-65fd2a96ef0f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250845056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3250845056
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.28444295
Short name T379
Test name
Test status
Simulation time 14013209804 ps
CPU time 191.13 seconds
Started Aug 16 06:31:55 PM PDT 24
Finished Aug 16 06:35:06 PM PDT 24
Peak memory 217084 kb
Host smart-18ded361-af0b-400a-bc56-80a6d11eefa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28444295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.28444295
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.124563510
Short name T127
Test name
Test status
Simulation time 4616064745 ps
CPU time 11.81 seconds
Started Aug 16 06:32:19 PM PDT 24
Finished Aug 16 06:32:31 PM PDT 24
Peak memory 200680 kb
Host smart-3f974b7b-4880-4fc2-80e6-d2055bd5a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124563510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.124563510
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2576710347
Short name T305
Test name
Test status
Simulation time 75202900833 ps
CPU time 146.31 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:34:20 PM PDT 24
Peak memory 200736 kb
Host smart-c5ae22e7-8227-40b4-9615-7cda5844ce99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576710347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2576710347
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.608749476
Short name T335
Test name
Test status
Simulation time 47758976 ps
CPU time 0.57 seconds
Started Aug 16 06:31:56 PM PDT 24
Finished Aug 16 06:31:56 PM PDT 24
Peak memory 195776 kb
Host smart-5ad74980-b745-4395-a12a-ec463802810a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608749476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.608749476
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.628773017
Short name T360
Test name
Test status
Simulation time 2620793864 ps
CPU time 31.1 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:32:24 PM PDT 24
Peak memory 200664 kb
Host smart-8ff51cb2-7486-4a37-9723-a2d6c4ac34d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=628773017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.628773017
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.162003851
Short name T491
Test name
Test status
Simulation time 15614217750 ps
CPU time 48.49 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:32:42 PM PDT 24
Peak memory 200708 kb
Host smart-382ca0a6-630f-4d3d-8959-405911fe168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162003851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.162003851
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.119659429
Short name T288
Test name
Test status
Simulation time 28787017141 ps
CPU time 686.06 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:43:20 PM PDT 24
Peak memory 500964 kb
Host smart-ec4d0bbc-3eef-4261-b741-7092dad028ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119659429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.119659429
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.351395604
Short name T475
Test name
Test status
Simulation time 39858961413 ps
CPU time 301.01 seconds
Started Aug 16 06:31:52 PM PDT 24
Finished Aug 16 06:36:54 PM PDT 24
Peak memory 200776 kb
Host smart-0de0f275-27a0-401b-a7c5-77a9b0aa1096
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351395604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.351395604
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2469802389
Short name T527
Test name
Test status
Simulation time 935706242 ps
CPU time 53.04 seconds
Started Aug 16 06:31:53 PM PDT 24
Finished Aug 16 06:32:46 PM PDT 24
Peak memory 200644 kb
Host smart-2d1a25c2-7511-4d84-9233-f4e1cfad54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469802389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2469802389
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1715793680
Short name T457
Test name
Test status
Simulation time 1232113378 ps
CPU time 11.29 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:32:05 PM PDT 24
Peak memory 200664 kb
Host smart-d6823375-959d-41cc-a5b3-79eadad08eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715793680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1715793680
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3579861075
Short name T421
Test name
Test status
Simulation time 46643433658 ps
CPU time 1101.87 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:50:16 PM PDT 24
Peak memory 702808 kb
Host smart-41104eeb-f8d6-432e-ac75-4952f46dc892
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579861075 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3579861075
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.949369418
Short name T28
Test name
Test status
Simulation time 6538450113 ps
CPU time 121.62 seconds
Started Aug 16 06:31:55 PM PDT 24
Finished Aug 16 06:33:56 PM PDT 24
Peak memory 200732 kb
Host smart-c278815d-a3b1-4d7e-84d3-6a938c904b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949369418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.949369418
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2180483229
Short name T456
Test name
Test status
Simulation time 12562738 ps
CPU time 0.61 seconds
Started Aug 16 06:32:00 PM PDT 24
Finished Aug 16 06:32:00 PM PDT 24
Peak memory 195652 kb
Host smart-baf1f149-4c27-4582-a0f0-0a54fd698da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180483229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2180483229
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3058333166
Short name T470
Test name
Test status
Simulation time 1007014393 ps
CPU time 58.56 seconds
Started Aug 16 06:31:55 PM PDT 24
Finished Aug 16 06:32:54 PM PDT 24
Peak memory 200752 kb
Host smart-e8248746-36ea-42af-9067-0f1a1b2461ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058333166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3058333166
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3193518685
Short name T461
Test name
Test status
Simulation time 11954310514 ps
CPU time 41.38 seconds
Started Aug 16 06:31:52 PM PDT 24
Finished Aug 16 06:32:33 PM PDT 24
Peak memory 217120 kb
Host smart-52eb6ca0-8e26-40cc-843f-1f185553904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193518685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3193518685
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2242584074
Short name T422
Test name
Test status
Simulation time 848020668 ps
CPU time 24.76 seconds
Started Aug 16 06:31:56 PM PDT 24
Finished Aug 16 06:32:21 PM PDT 24
Peak memory 252420 kb
Host smart-19980cf4-af37-4b51-80fd-5d5094eee330
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242584074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2242584074
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.607883611
Short name T290
Test name
Test status
Simulation time 70513476176 ps
CPU time 133.37 seconds
Started Aug 16 06:31:52 PM PDT 24
Finished Aug 16 06:34:06 PM PDT 24
Peak memory 200732 kb
Host smart-b132996f-ed3b-497f-8936-e497c1d6de33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607883611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.607883611
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2947142506
Short name T323
Test name
Test status
Simulation time 7922974973 ps
CPU time 111.97 seconds
Started Aug 16 06:31:56 PM PDT 24
Finished Aug 16 06:33:48 PM PDT 24
Peak memory 200808 kb
Host smart-e0bbcda8-8294-4492-8a14-524b3777678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947142506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2947142506
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2387742161
Short name T273
Test name
Test status
Simulation time 144091623 ps
CPU time 3.58 seconds
Started Aug 16 06:31:54 PM PDT 24
Finished Aug 16 06:31:58 PM PDT 24
Peak memory 200672 kb
Host smart-1fc11896-33eb-4e4b-87eb-2876698a64ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387742161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2387742161
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3372384131
Short name T391
Test name
Test status
Simulation time 270597081 ps
CPU time 3.59 seconds
Started Aug 16 06:32:00 PM PDT 24
Finished Aug 16 06:32:04 PM PDT 24
Peak memory 200612 kb
Host smart-1b3fa182-396e-40a2-8b52-427939241e71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372384131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3372384131
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.34752504
Short name T434
Test name
Test status
Simulation time 2517686059 ps
CPU time 45.02 seconds
Started Aug 16 06:32:09 PM PDT 24
Finished Aug 16 06:32:55 PM PDT 24
Peak memory 200728 kb
Host smart-3a773c82-e1d0-4b83-933f-7cfcf6a12d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34752504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.34752504
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2946525664
Short name T406
Test name
Test status
Simulation time 41569013 ps
CPU time 0.58 seconds
Started Aug 16 06:32:04 PM PDT 24
Finished Aug 16 06:32:04 PM PDT 24
Peak memory 197416 kb
Host smart-c766289f-353e-4559-98a3-1616bf090f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946525664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2946525664
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3502425345
Short name T295
Test name
Test status
Simulation time 1319421159 ps
CPU time 41.35 seconds
Started Aug 16 06:32:09 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 200640 kb
Host smart-8e9bbef3-b08c-43a7-a0f2-a72512350af9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502425345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3502425345
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2239664381
Short name T197
Test name
Test status
Simulation time 4677094205 ps
CPU time 15.76 seconds
Started Aug 16 06:32:02 PM PDT 24
Finished Aug 16 06:32:18 PM PDT 24
Peak memory 200676 kb
Host smart-39ffe2fd-2622-4883-868e-25dbd1263db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239664381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2239664381
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4273294687
Short name T345
Test name
Test status
Simulation time 2260673079 ps
CPU time 210.76 seconds
Started Aug 16 06:32:03 PM PDT 24
Finished Aug 16 06:35:34 PM PDT 24
Peak memory 646540 kb
Host smart-78d5d360-9eaf-4786-a798-137458a7aad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4273294687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4273294687
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2939168986
Short name T31
Test name
Test status
Simulation time 15914256518 ps
CPU time 103.36 seconds
Started Aug 16 06:32:01 PM PDT 24
Finished Aug 16 06:33:45 PM PDT 24
Peak memory 200728 kb
Host smart-2cafe478-6fe9-4f95-9089-eff313e5cae1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939168986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2939168986
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1264252899
Short name T181
Test name
Test status
Simulation time 647682954 ps
CPU time 35.4 seconds
Started Aug 16 06:32:02 PM PDT 24
Finished Aug 16 06:32:37 PM PDT 24
Peak memory 200672 kb
Host smart-280ede40-e894-40ed-8744-3198b649e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264252899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1264252899
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3761187355
Short name T212
Test name
Test status
Simulation time 917915562 ps
CPU time 15.73 seconds
Started Aug 16 06:32:03 PM PDT 24
Finished Aug 16 06:32:19 PM PDT 24
Peak memory 200660 kb
Host smart-95634bc0-b917-4803-bf77-3bb8d780f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761187355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3761187355
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.621936554
Short name T473
Test name
Test status
Simulation time 2767251667 ps
CPU time 50.5 seconds
Started Aug 16 06:32:10 PM PDT 24
Finished Aug 16 06:33:00 PM PDT 24
Peak memory 200740 kb
Host smart-be368405-07dd-437a-98f1-09892f7feca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621936554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.621936554
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2056128983
Short name T180
Test name
Test status
Simulation time 19114251 ps
CPU time 0.55 seconds
Started Aug 16 06:32:08 PM PDT 24
Finished Aug 16 06:32:09 PM PDT 24
Peak memory 195708 kb
Host smart-ea963c84-2693-4378-b7fd-537189a4261d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056128983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2056128983
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.896107196
Short name T393
Test name
Test status
Simulation time 102209250 ps
CPU time 2.82 seconds
Started Aug 16 06:32:03 PM PDT 24
Finished Aug 16 06:32:05 PM PDT 24
Peak memory 200564 kb
Host smart-bfe468b6-a872-44d0-8308-6b9bf8863d1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896107196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.896107196
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1109575357
Short name T463
Test name
Test status
Simulation time 1449383933 ps
CPU time 138.69 seconds
Started Aug 16 06:32:00 PM PDT 24
Finished Aug 16 06:34:19 PM PDT 24
Peak memory 445988 kb
Host smart-2e1e11e3-2465-4ac0-a3ba-bfea05ade1d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1109575357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1109575357
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2419794035
Short name T270
Test name
Test status
Simulation time 4600854485 ps
CPU time 29.77 seconds
Started Aug 16 06:32:08 PM PDT 24
Finished Aug 16 06:32:38 PM PDT 24
Peak memory 200744 kb
Host smart-890ba781-bf4f-43fd-a7be-8da9f31f6597
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419794035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2419794035
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.126701460
Short name T182
Test name
Test status
Simulation time 42409677367 ps
CPU time 143.04 seconds
Started Aug 16 06:32:02 PM PDT 24
Finished Aug 16 06:34:25 PM PDT 24
Peak memory 200676 kb
Host smart-5c318d9e-5a2b-4588-8404-c760461a8592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126701460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.126701460
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1180054726
Short name T333
Test name
Test status
Simulation time 4956862345 ps
CPU time 7.97 seconds
Started Aug 16 06:32:02 PM PDT 24
Finished Aug 16 06:32:10 PM PDT 24
Peak memory 200744 kb
Host smart-7ad2a1d7-03d2-4785-a1d7-c58d84cec424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180054726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1180054726
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3426694584
Short name T202
Test name
Test status
Simulation time 15258275657 ps
CPU time 172.06 seconds
Started Aug 16 06:32:10 PM PDT 24
Finished Aug 16 06:35:02 PM PDT 24
Peak memory 200788 kb
Host smart-8d8703b8-80d2-4838-ab29-1695c93f8485
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426694584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3426694584
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3451514626
Short name T469
Test name
Test status
Simulation time 5837680840 ps
CPU time 47.19 seconds
Started Aug 16 06:32:07 PM PDT 24
Finished Aug 16 06:32:55 PM PDT 24
Peak memory 200680 kb
Host smart-45a51a86-3571-4481-ad01-c6f12c616e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451514626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3451514626
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.48317239
Short name T238
Test name
Test status
Simulation time 41393069 ps
CPU time 0.61 seconds
Started Aug 16 06:32:09 PM PDT 24
Finished Aug 16 06:32:10 PM PDT 24
Peak memory 196716 kb
Host smart-f9ef604d-db01-4b8e-8270-ea4727f1a339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48317239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.48317239
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3082080195
Short name T524
Test name
Test status
Simulation time 5248955977 ps
CPU time 46.59 seconds
Started Aug 16 06:32:08 PM PDT 24
Finished Aug 16 06:32:55 PM PDT 24
Peak memory 216996 kb
Host smart-fcdf28e2-afa5-448b-bf79-ea8b5a168e33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082080195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3082080195
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3076948723
Short name T515
Test name
Test status
Simulation time 2397116559 ps
CPU time 25.23 seconds
Started Aug 16 06:32:12 PM PDT 24
Finished Aug 16 06:32:37 PM PDT 24
Peak memory 200720 kb
Host smart-0697ec70-d399-47c4-9b9d-213678dca61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076948723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3076948723
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2443317372
Short name T146
Test name
Test status
Simulation time 3314291986 ps
CPU time 637.21 seconds
Started Aug 16 06:32:08 PM PDT 24
Finished Aug 16 06:42:45 PM PDT 24
Peak memory 716236 kb
Host smart-a03851e9-a2ab-4984-8581-80596760803f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2443317372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2443317372
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.70406509
Short name T497
Test name
Test status
Simulation time 2851124816 ps
CPU time 31.84 seconds
Started Aug 16 06:32:07 PM PDT 24
Finished Aug 16 06:32:39 PM PDT 24
Peak memory 200756 kb
Host smart-4227a1d3-b3bc-4fe5-bf4b-a9ceccd74087
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70406509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.70406509
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2109180821
Short name T161
Test name
Test status
Simulation time 26867868395 ps
CPU time 111.82 seconds
Started Aug 16 06:32:07 PM PDT 24
Finished Aug 16 06:33:59 PM PDT 24
Peak memory 200728 kb
Host smart-fb795388-6606-4850-809e-3492de9797ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109180821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2109180821
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1342641479
Short name T471
Test name
Test status
Simulation time 1043064132 ps
CPU time 13.6 seconds
Started Aug 16 06:32:09 PM PDT 24
Finished Aug 16 06:32:23 PM PDT 24
Peak memory 200668 kb
Host smart-0354d8ec-b51b-4b53-a8b8-257a02b72e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342641479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1342641479
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3058864896
Short name T301
Test name
Test status
Simulation time 107962984627 ps
CPU time 284.31 seconds
Started Aug 16 06:32:09 PM PDT 24
Finished Aug 16 06:36:53 PM PDT 24
Peak memory 217128 kb
Host smart-20489416-879d-41f1-a95d-a2944d38e0e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058864896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3058864896
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.122106560
Short name T489
Test name
Test status
Simulation time 2603596410 ps
CPU time 25.16 seconds
Started Aug 16 06:32:12 PM PDT 24
Finished Aug 16 06:32:37 PM PDT 24
Peak memory 200680 kb
Host smart-361957b3-087b-4590-80a9-b859d9a9395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122106560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.122106560
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.380088198
Short name T327
Test name
Test status
Simulation time 146122990 ps
CPU time 0.59 seconds
Started Aug 16 06:32:21 PM PDT 24
Finished Aug 16 06:32:22 PM PDT 24
Peak memory 196760 kb
Host smart-ab46f8e1-75d2-4d9c-a6aa-616e9cc09f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380088198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.380088198
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2244337676
Short name T162
Test name
Test status
Simulation time 1572618893 ps
CPU time 88.05 seconds
Started Aug 16 06:32:17 PM PDT 24
Finished Aug 16 06:33:45 PM PDT 24
Peak memory 200732 kb
Host smart-8a6c1627-1c3b-42a4-b2a4-91a9cdb700ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244337676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2244337676
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3295804131
Short name T142
Test name
Test status
Simulation time 841865335 ps
CPU time 12.48 seconds
Started Aug 16 06:32:21 PM PDT 24
Finished Aug 16 06:32:34 PM PDT 24
Peak memory 200704 kb
Host smart-ecf2275d-844c-451f-9f5d-b0170c74e658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295804131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3295804131
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.698810300
Short name T386
Test name
Test status
Simulation time 42348779699 ps
CPU time 407.79 seconds
Started Aug 16 06:32:18 PM PDT 24
Finished Aug 16 06:39:06 PM PDT 24
Peak memory 650212 kb
Host smart-91729b58-86f5-41cb-a09d-3bc81d2d4720
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=698810300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.698810300
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4055166641
Short name T6
Test name
Test status
Simulation time 11202909031 ps
CPU time 35.36 seconds
Started Aug 16 06:32:17 PM PDT 24
Finished Aug 16 06:32:53 PM PDT 24
Peak memory 200704 kb
Host smart-69ab27fb-a8e9-4832-a0b2-c9324de9a5cb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055166641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4055166641
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2968766152
Short name T159
Test name
Test status
Simulation time 8365077846 ps
CPU time 99.44 seconds
Started Aug 16 06:32:15 PM PDT 24
Finished Aug 16 06:33:55 PM PDT 24
Peak memory 200728 kb
Host smart-bb224dca-b6c8-4052-ab12-65c92264e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968766152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2968766152
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1102377828
Short name T126
Test name
Test status
Simulation time 1058911568 ps
CPU time 4.5 seconds
Started Aug 16 06:32:07 PM PDT 24
Finished Aug 16 06:32:12 PM PDT 24
Peak memory 200668 kb
Host smart-2cc2130c-4501-4e74-83cc-ac7dff16d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102377828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1102377828
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3991554066
Short name T210
Test name
Test status
Simulation time 46728244892 ps
CPU time 497.06 seconds
Started Aug 16 06:32:17 PM PDT 24
Finished Aug 16 06:40:34 PM PDT 24
Peak memory 263968 kb
Host smart-ff15210f-ac63-4e17-9095-3e85f041b54a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991554066 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3991554066
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2371441370
Short name T358
Test name
Test status
Simulation time 10259038147 ps
CPU time 70.6 seconds
Started Aug 16 06:32:15 PM PDT 24
Finished Aug 16 06:33:26 PM PDT 24
Peak memory 200804 kb
Host smart-2fc6572f-b949-4c0a-afed-baaebaa23bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371441370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2371441370
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.179060181
Short name T496
Test name
Test status
Simulation time 13880553 ps
CPU time 0.58 seconds
Started Aug 16 06:32:17 PM PDT 24
Finished Aug 16 06:32:18 PM PDT 24
Peak memory 196368 kb
Host smart-65ac7743-5f87-438f-b093-44adee12a510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179060181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.179060181
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1330322428
Short name T424
Test name
Test status
Simulation time 2557359356 ps
CPU time 38.84 seconds
Started Aug 16 06:32:16 PM PDT 24
Finished Aug 16 06:32:55 PM PDT 24
Peak memory 200792 kb
Host smart-47e2bf6a-6c07-4735-8590-69ee6d22967a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330322428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1330322428
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2127825649
Short name T427
Test name
Test status
Simulation time 9086575039 ps
CPU time 34.68 seconds
Started Aug 16 06:32:16 PM PDT 24
Finished Aug 16 06:32:50 PM PDT 24
Peak memory 200716 kb
Host smart-9c44871c-1e40-46fc-9903-13dd1687fada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127825649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2127825649
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2648305422
Short name T154
Test name
Test status
Simulation time 1976774738 ps
CPU time 301.91 seconds
Started Aug 16 06:32:18 PM PDT 24
Finished Aug 16 06:37:20 PM PDT 24
Peak memory 612316 kb
Host smart-9b90f835-4012-45a3-bf1c-2fac5a8ca315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648305422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2648305422
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3088541435
Short name T264
Test name
Test status
Simulation time 5474908285 ps
CPU time 70.38 seconds
Started Aug 16 06:32:17 PM PDT 24
Finished Aug 16 06:33:27 PM PDT 24
Peak memory 200800 kb
Host smart-c74e37c4-c267-4542-a20f-46a984b0d15f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088541435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3088541435
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2310030068
Short name T490
Test name
Test status
Simulation time 1231634731 ps
CPU time 17.8 seconds
Started Aug 16 06:32:16 PM PDT 24
Finished Aug 16 06:32:33 PM PDT 24
Peak memory 200596 kb
Host smart-3a6cc400-4cb9-4ced-b3a9-2e454afbecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310030068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2310030068
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4063749968
Short name T179
Test name
Test status
Simulation time 197274210 ps
CPU time 8.56 seconds
Started Aug 16 06:32:21 PM PDT 24
Finished Aug 16 06:32:30 PM PDT 24
Peak memory 200696 kb
Host smart-d144d7fd-3b5a-4add-815c-eec69ddba9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063749968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4063749968
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1001739688
Short name T484
Test name
Test status
Simulation time 72108109905 ps
CPU time 3657.98 seconds
Started Aug 16 06:32:15 PM PDT 24
Finished Aug 16 07:33:14 PM PDT 24
Peak memory 849524 kb
Host smart-b6c49f5b-31bd-4f17-8ae8-a744885081ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001739688 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1001739688
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1483571607
Short name T440
Test name
Test status
Simulation time 8656804787 ps
CPU time 119.91 seconds
Started Aug 16 06:32:18 PM PDT 24
Finished Aug 16 06:34:18 PM PDT 24
Peak memory 200736 kb
Host smart-40297269-37d6-4e60-9c17-2910bab79f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483571607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1483571607
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.243900613
Short name T325
Test name
Test status
Simulation time 36285422 ps
CPU time 0.61 seconds
Started Aug 16 06:32:28 PM PDT 24
Finished Aug 16 06:32:29 PM PDT 24
Peak memory 196740 kb
Host smart-0897c6a1-89f9-4b0d-9108-c11894b5e130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243900613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.243900613
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3646434269
Short name T247
Test name
Test status
Simulation time 3193176063 ps
CPU time 89.95 seconds
Started Aug 16 06:32:25 PM PDT 24
Finished Aug 16 06:33:55 PM PDT 24
Peak memory 200672 kb
Host smart-8f19221d-0f1a-47c4-a606-2aab0535467d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3646434269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3646434269
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3081996849
Short name T298
Test name
Test status
Simulation time 4942114555 ps
CPU time 16.61 seconds
Started Aug 16 06:32:22 PM PDT 24
Finished Aug 16 06:32:39 PM PDT 24
Peak memory 200688 kb
Host smart-2c79bf78-0a6e-4f7b-9f59-64e03900657b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081996849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3081996849
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2546923505
Short name T39
Test name
Test status
Simulation time 6044397304 ps
CPU time 1193.75 seconds
Started Aug 16 06:32:24 PM PDT 24
Finished Aug 16 06:52:18 PM PDT 24
Peak memory 744236 kb
Host smart-171c400b-576c-4010-a70b-a804f7878ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546923505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2546923505
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2548721650
Short name T307
Test name
Test status
Simulation time 56032680092 ps
CPU time 208.11 seconds
Started Aug 16 06:32:23 PM PDT 24
Finished Aug 16 06:35:51 PM PDT 24
Peak memory 200692 kb
Host smart-aacf31d3-09f1-48d5-89bc-7268ee7e3b67
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548721650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2548721650
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2270996144
Short name T405
Test name
Test status
Simulation time 34180438795 ps
CPU time 128.76 seconds
Started Aug 16 06:32:26 PM PDT 24
Finished Aug 16 06:34:35 PM PDT 24
Peak memory 200776 kb
Host smart-24342f80-4b8c-4ba1-86d6-ba6481224723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270996144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2270996144
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1833662786
Short name T178
Test name
Test status
Simulation time 1302805002 ps
CPU time 11.2 seconds
Started Aug 16 06:32:25 PM PDT 24
Finished Aug 16 06:32:36 PM PDT 24
Peak memory 200748 kb
Host smart-530d1472-52cf-4afc-b997-6ef6e11fa2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833662786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1833662786
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1443298872
Short name T368
Test name
Test status
Simulation time 315991353671 ps
CPU time 1449.31 seconds
Started Aug 16 06:32:24 PM PDT 24
Finished Aug 16 06:56:33 PM PDT 24
Peak memory 661524 kb
Host smart-38636d3e-3138-4a3a-95ad-0aaac56a6cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443298872 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1443298872
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.21707104
Short name T29
Test name
Test status
Simulation time 29452472409 ps
CPU time 93.91 seconds
Started Aug 16 06:32:23 PM PDT 24
Finished Aug 16 06:33:57 PM PDT 24
Peak memory 200764 kb
Host smart-88149689-1788-4561-bc2d-ab7a01be47a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21707104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.21707104
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1522879689
Short name T153
Test name
Test status
Simulation time 13804930 ps
CPU time 0.59 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:29:56 PM PDT 24
Peak memory 196760 kb
Host smart-8e3a875b-400f-4fb3-afff-5ca1cd417d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522879689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1522879689
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.4229750565
Short name T195
Test name
Test status
Simulation time 3216262615 ps
CPU time 33.74 seconds
Started Aug 16 06:29:57 PM PDT 24
Finished Aug 16 06:30:31 PM PDT 24
Peak memory 200764 kb
Host smart-f8949670-61bc-41f7-8fd7-993023514e2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229750565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.4229750565
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.2154037211
Short name T399
Test name
Test status
Simulation time 2615052323 ps
CPU time 36.15 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:30:34 PM PDT 24
Peak memory 200692 kb
Host smart-6baff206-8e4f-4fa8-971f-a2cfe9942539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154037211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.2154037211
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1606605603
Short name T228
Test name
Test status
Simulation time 17339161373 ps
CPU time 694.75 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:41:33 PM PDT 24
Peak memory 667196 kb
Host smart-469c6913-9034-4097-ba1a-c170d443ebbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606605603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1606605603
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2399746455
Short name T249
Test name
Test status
Simulation time 559410490 ps
CPU time 17.41 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:30:13 PM PDT 24
Peak memory 200620 kb
Host smart-ee4e51b2-1392-4a27-b6bb-9d850503ceae
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399746455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2399746455
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1432024444
Short name T190
Test name
Test status
Simulation time 27570175383 ps
CPU time 130.24 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:32:06 PM PDT 24
Peak memory 201024 kb
Host smart-e2679318-5623-4e27-b442-669700840cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432024444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1432024444
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.713148986
Short name T390
Test name
Test status
Simulation time 598265848 ps
CPU time 3.99 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:30:02 PM PDT 24
Peak memory 200720 kb
Host smart-9febfeb0-d09b-4353-921f-8f369808d160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713148986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.713148986
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1300770419
Short name T218
Test name
Test status
Simulation time 322771696596 ps
CPU time 2666.03 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 07:14:22 PM PDT 24
Peak memory 760300 kb
Host smart-04507f49-6e62-4680-a179-a4eeaa2ac7fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300770419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1300770419
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2369201415
Short name T11
Test name
Test status
Simulation time 8343799034 ps
CPU time 159.75 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:32:36 PM PDT 24
Peak memory 322928 kb
Host smart-905332f8-5675-43a2-8404-b25034ee421d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369201415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2369201415
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1188842630
Short name T306
Test name
Test status
Simulation time 476155075 ps
CPU time 24.23 seconds
Started Aug 16 06:29:56 PM PDT 24
Finished Aug 16 06:30:20 PM PDT 24
Peak memory 200708 kb
Host smart-1d73d5e6-0806-4d03-a180-ea017a9fe5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188842630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1188842630
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.4171472621
Short name T378
Test name
Test status
Simulation time 23404839 ps
CPU time 0.6 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:01 PM PDT 24
Peak memory 197416 kb
Host smart-57958fb0-d509-469e-ac12-08fd76b0ed38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171472621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.4171472621
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2212387628
Short name T207
Test name
Test status
Simulation time 4349773066 ps
CPU time 60.34 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:31:01 PM PDT 24
Peak memory 200740 kb
Host smart-80497abd-11ef-4aad-90ab-44a83588b0cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212387628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2212387628
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4178384069
Short name T314
Test name
Test status
Simulation time 6062344169 ps
CPU time 27.64 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:29 PM PDT 24
Peak memory 200760 kb
Host smart-70edda13-516c-460d-a04d-ed7bca8e4a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178384069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4178384069
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2719479774
Short name T420
Test name
Test status
Simulation time 3976665828 ps
CPU time 748.86 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:42:30 PM PDT 24
Peak memory 723644 kb
Host smart-09cb0d50-c1f7-4c3b-9a88-2440f6d00659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719479774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2719479774
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3131702056
Short name T415
Test name
Test status
Simulation time 36956296844 ps
CPU time 83.25 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:31:23 PM PDT 24
Peak memory 200664 kb
Host smart-19bcfe57-31d0-46ac-9b28-48338aaccaa6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131702056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3131702056
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2939426132
Short name T66
Test name
Test status
Simulation time 2975291740 ps
CPU time 25.93 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 200636 kb
Host smart-f272b75d-a551-468c-b5a4-b8ddba202846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939426132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2939426132
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.765761430
Short name T500
Test name
Test status
Simulation time 2547655013 ps
CPU time 10.25 seconds
Started Aug 16 06:30:02 PM PDT 24
Finished Aug 16 06:30:12 PM PDT 24
Peak memory 200724 kb
Host smart-9299803e-f7d3-4879-bc0f-f8bd0e108f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765761430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.765761430
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.585348242
Short name T73
Test name
Test status
Simulation time 18351447329 ps
CPU time 268.07 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:34:28 PM PDT 24
Peak memory 217136 kb
Host smart-4fad6c21-6552-4036-947d-02e14ba944c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585348242 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.585348242
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.973564677
Short name T15
Test name
Test status
Simulation time 4646272218 ps
CPU time 95.73 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:31:35 PM PDT 24
Peak memory 441128 kb
Host smart-baa72716-f075-412a-b958-48a488247a9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=973564677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.973564677
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3229294433
Short name T446
Test name
Test status
Simulation time 1799910579 ps
CPU time 71.98 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:31:13 PM PDT 24
Peak memory 200680 kb
Host smart-9a2b67cd-c616-4c45-a003-69dc8dba1a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229294433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3229294433
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2013691682
Short name T347
Test name
Test status
Simulation time 15429650 ps
CPU time 0.6 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:02 PM PDT 24
Peak memory 196360 kb
Host smart-cda3077c-ae8a-4d59-8696-fb4c08251430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013691682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2013691682
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.439719403
Short name T398
Test name
Test status
Simulation time 5716699465 ps
CPU time 63.37 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:31:04 PM PDT 24
Peak memory 208928 kb
Host smart-cba8b572-1293-4b23-a2d2-880953dd2cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439719403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.439719403
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1073585115
Short name T214
Test name
Test status
Simulation time 10462442052 ps
CPU time 76.28 seconds
Started Aug 16 06:29:58 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 217144 kb
Host smart-f4a19d6e-1b13-455d-84db-5384feb9e7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073585115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1073585115
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3895162212
Short name T213
Test name
Test status
Simulation time 5667502996 ps
CPU time 934.55 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:45:35 PM PDT 24
Peak memory 711024 kb
Host smart-400421bc-eba7-41d2-a393-9b2a5195eddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895162212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3895162212
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4101898649
Short name T320
Test name
Test status
Simulation time 25453387783 ps
CPU time 155.24 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:32:35 PM PDT 24
Peak memory 200704 kb
Host smart-3d16e4da-0cdd-4876-8643-877a8cf8c955
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101898649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4101898649
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1050831945
Short name T157
Test name
Test status
Simulation time 3372875024 ps
CPU time 66.02 seconds
Started Aug 16 06:30:04 PM PDT 24
Finished Aug 16 06:31:10 PM PDT 24
Peak memory 200712 kb
Host smart-24fb9a00-9e61-4fe3-be1d-898f0328f84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050831945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1050831945
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1277248230
Short name T281
Test name
Test status
Simulation time 699615203 ps
CPU time 4.57 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:30:05 PM PDT 24
Peak memory 200692 kb
Host smart-40c73ff7-6e93-414e-a6d1-e381e6805224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277248230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1277248230
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1687321483
Short name T482
Test name
Test status
Simulation time 241005206467 ps
CPU time 1117.67 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:48:37 PM PDT 24
Peak memory 200712 kb
Host smart-9b7d0b87-4b1c-4450-9eb5-3324178fbf5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687321483 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1687321483
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4020927350
Short name T516
Test name
Test status
Simulation time 6055176662 ps
CPU time 68.15 seconds
Started Aug 16 06:30:04 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 200724 kb
Host smart-1f5a77f9-0dd5-4c17-9156-f7d86d5ba835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020927350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4020927350
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2351435638
Short name T365
Test name
Test status
Simulation time 22199197 ps
CPU time 0.63 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:30:00 PM PDT 24
Peak memory 196772 kb
Host smart-b4146961-420e-40b5-b746-5a2292a3c8ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351435638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2351435638
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1433222564
Short name T342
Test name
Test status
Simulation time 3881421490 ps
CPU time 56.63 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:30:57 PM PDT 24
Peak memory 200732 kb
Host smart-434de3da-b766-4414-b98b-29178893a274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433222564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1433222564
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1423513807
Short name T187
Test name
Test status
Simulation time 23332906398 ps
CPU time 72.6 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 200736 kb
Host smart-f0c63d1b-b613-4fe9-9206-0804f46d7368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423513807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1423513807
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.126550399
Short name T309
Test name
Test status
Simulation time 862765182 ps
CPU time 153.45 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:32:34 PM PDT 24
Peak memory 629452 kb
Host smart-da9437f3-4182-4bbc-8d6b-f8f825fb0e10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=126550399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.126550399
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.450727718
Short name T188
Test name
Test status
Simulation time 29889846967 ps
CPU time 208.3 seconds
Started Aug 16 06:30:04 PM PDT 24
Finished Aug 16 06:33:32 PM PDT 24
Peak memory 200684 kb
Host smart-18c83b7c-0743-4fc8-9913-d59ba6b04b33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450727718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.450727718
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.4070001758
Short name T355
Test name
Test status
Simulation time 567563714 ps
CPU time 28.41 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:29 PM PDT 24
Peak memory 200604 kb
Host smart-ab085ed8-d8bb-4446-b33f-ffe346d5dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070001758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.4070001758
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.576434405
Short name T435
Test name
Test status
Simulation time 594760011 ps
CPU time 8.72 seconds
Started Aug 16 06:30:03 PM PDT 24
Finished Aug 16 06:30:12 PM PDT 24
Peak memory 200728 kb
Host smart-cb8961e1-f587-490c-8d3f-69cae51d6f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576434405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.576434405
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2815112444
Short name T14
Test name
Test status
Simulation time 12296467279 ps
CPU time 679.15 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:41:20 PM PDT 24
Peak memory 200736 kb
Host smart-3eef5575-d7ea-4499-a4a8-f702feed3117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815112444 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2815112444
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3378570148
Short name T313
Test name
Test status
Simulation time 11977037270 ps
CPU time 34.67 seconds
Started Aug 16 06:30:00 PM PDT 24
Finished Aug 16 06:30:35 PM PDT 24
Peak memory 200752 kb
Host smart-4cce1866-0cb2-47a7-98df-1ef161490722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378570148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3378570148
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1996825973
Short name T372
Test name
Test status
Simulation time 13335484 ps
CPU time 0.59 seconds
Started Aug 16 06:30:07 PM PDT 24
Finished Aug 16 06:30:08 PM PDT 24
Peak memory 196396 kb
Host smart-f7a186ed-ef77-4416-8165-540370215b82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996825973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1996825973
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3279830727
Short name T54
Test name
Test status
Simulation time 489538981 ps
CPU time 28.08 seconds
Started Aug 16 06:29:59 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 200716 kb
Host smart-c4c4ef03-4ea6-44c0-8d63-cd54f17b6d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3279830727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3279830727
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2303862212
Short name T528
Test name
Test status
Simulation time 794811173 ps
CPU time 3.2 seconds
Started Aug 16 06:30:02 PM PDT 24
Finished Aug 16 06:30:05 PM PDT 24
Peak memory 200548 kb
Host smart-f63fbb98-1ae9-435a-8d95-00504db9e2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303862212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2303862212
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1074155592
Short name T143
Test name
Test status
Simulation time 7548803268 ps
CPU time 234.98 seconds
Started Aug 16 06:30:03 PM PDT 24
Finished Aug 16 06:33:59 PM PDT 24
Peak memory 616060 kb
Host smart-15af0952-543d-4cdf-89c7-6376a360a5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074155592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1074155592
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.728253990
Short name T413
Test name
Test status
Simulation time 86381404438 ps
CPU time 300.77 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:35:02 PM PDT 24
Peak memory 200672 kb
Host smart-7443cfe5-3734-44c1-8754-7bb2f051bf61
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728253990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.728253990
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2195256181
Short name T308
Test name
Test status
Simulation time 1848262112 ps
CPU time 31.71 seconds
Started Aug 16 06:30:03 PM PDT 24
Finished Aug 16 06:30:34 PM PDT 24
Peak memory 200660 kb
Host smart-78bc6f37-8c22-4ea3-9161-044798b50cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195256181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2195256181
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3792944828
Short name T255
Test name
Test status
Simulation time 684001038 ps
CPU time 11.63 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:30:13 PM PDT 24
Peak memory 200724 kb
Host smart-53e44209-c1e2-471f-a7b9-81dcb2912ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792944828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3792944828
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3504614075
Short name T431
Test name
Test status
Simulation time 83079862919 ps
CPU time 693.22 seconds
Started Aug 16 06:30:03 PM PDT 24
Finished Aug 16 06:41:36 PM PDT 24
Peak memory 200724 kb
Host smart-10f26d30-e704-4b9e-86fe-e1b13e8a8805
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504614075 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3504614075
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3325753550
Short name T87
Test name
Test status
Simulation time 17662018050 ps
CPU time 101.78 seconds
Started Aug 16 06:30:01 PM PDT 24
Finished Aug 16 06:31:43 PM PDT 24
Peak memory 200680 kb
Host smart-c0260760-e851-48d2-a6e9-6d5a4890d95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325753550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3325753550
Directory /workspace/9.hmac_wipe_secret/latest
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