Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16772559	1			T1	17935		T2	93470		T3	3
all_values[1]	16772559	1			T1	17935		T2	93470		T3	3
all_values[2]	16772559	1			T1	17935		T2	93470		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230287

1

T2

1845

T3

6

T4

134

auto[1]

50087390

1

T1

53805

T2

278565

T3

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42890909

1

T1

41902

T2

233837

T3

8

auto[1]

7426768

1

T1

11903

T2

46573

T3

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	73632	1			T2	1823		T3	3		T4	130
all_values[0]	auto[0]	auto[1]	322	1			T4	4		T5	1		T6	3
all_values[0]	auto[1]	auto[0]	16680224	1			T1	17932		T2	91429		T7	32673
all_values[0]	auto[1]	auto[1]	18381	1			T1	3		T2	218		T7	5
all_values[1]	auto[0]	auto[0]	70857	1			T3	3		T5	6		T18	1
all_values[1]	auto[0]	auto[1]	176	1			T5	2		T6	4		T70	4
all_values[1]	auto[1]	auto[0]	16701275	1			T1	17935		T2	93466		T7	32678
all_values[1]	auto[1]	auto[1]	251	1			T2	4		T5	1		T6	10
all_values[2]	auto[0]	auto[0]	45308	1			T2	2		T5	375		T8	109
all_values[2]	auto[0]	auto[1]	39992	1			T2	20		T8	330		T6	7
all_values[2]	auto[1]	auto[0]	9319613	1			T1	6035		T2	47117		T3	2
all_values[2]	auto[1]	auto[1]	7367646	1			T1	11900		T2	46331		T3	1