Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94362

1

T1

18

T2

2120

T7

26

auto[1]

105850

1

T1

18

T2

2240

T7

16

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	74918	1			T1	15		T2	1612		T7	14
len_1026_2046	6298	1			T1	2		T2	107		T7	1
len_514_1022	2952	1			T2	55		T4	1		T8	1
len_2_510	3303	1			T2	65		T5	9		T6	19
len_2056	175	1			T2	12		T5	4		T70	4
len_2048	302	1			T2	9		T5	4		T50	1
len_2040	184	1			T2	3		T4	3		T5	1
len_1032	149	1			T2	8		T4	3		T5	9
len_1024	1845	1			T2	15		T4	2		T5	2
len_1016	266	1			T2	11		T5	2		T70	9
len_520	155	1			T2	9		T5	3		T70	3
len_512	314	1			T2	10		T5	2		T6	3
len_504	163	1			T2	4		T5	2		T6	8
len_8	1126	1			T2	1		T5	14		T6	51
len_0	7956	1			T1	1		T2	259		T7	6

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

122

1

T5

2

T6

5

T53

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	36846	1			T1	8		T2	830		T7	9
auto[0]	len_1026_2046	2009	1			T2	39		T4	1		T5	1
auto[0]	len_514_1022	1892	1			T2	33		T4	1		T6	11
auto[0]	len_2_510	2002	1			T2	47		T5	1		T6	10
auto[0]	len_2056	88	1			T2	6		T5	3		T70	3
auto[0]	len_2048	160	1			T2	4		T5	1		T21	1
auto[0]	len_2040	105	1			T2	2		T4	1		T6	1
auto[0]	len_1032	61	1			T2	6		T5	2		T70	1
auto[0]	len_1024	221	1			T2	8		T4	2		T12	7
auto[0]	len_1016	161	1			T2	5		T5	2		T70	5
auto[0]	len_520	83	1			T2	5		T5	2		T70	1
auto[0]	len_512	193	1			T2	3		T6	3		T22	2
auto[0]	len_504	87	1			T2	2		T6	2		T70	1
auto[0]	len_8	84	1			T2	1		T6	45		T39	4
auto[0]	len_0	3189	1			T1	1		T2	69		T7	4
auto[1]	len_2050_plus	38072	1			T1	7		T2	782		T7	5
auto[1]	len_1026_2046	4289	1			T1	2		T2	68		T7	1
auto[1]	len_514_1022	1060	1			T2	22		T8	1		T6	16
auto[1]	len_2_510	1301	1			T2	18		T5	8		T6	9
auto[1]	len_2056	87	1			T2	6		T5	1		T70	1
auto[1]	len_2048	142	1			T2	5		T5	3		T50	1
auto[1]	len_2040	79	1			T2	1		T4	2		T5	1
auto[1]	len_1032	88	1			T2	2		T4	3		T5	7
auto[1]	len_1024	1624	1			T2	7		T5	2		T12	4
auto[1]	len_1016	105	1			T2	6		T70	4		T122	2
auto[1]	len_520	72	1			T2	4		T5	1		T70	2
auto[1]	len_512	121	1			T2	7		T5	2		T70	1
auto[1]	len_504	76	1			T2	2		T5	2		T6	6
auto[1]	len_8	1042	1			T5	14		T6	6		T50	7
auto[1]	len_0	4767	1			T2	190		T7	2		T5	7

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

59

1

T6

3

T53

1

T137

2

auto[1]

len_upper

63

1

T5

2

T6

2

T138

2