Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4167609 1 T1 1820 T2 24072 T3 1
auto[1] 2546763 1 T1 1425 T2 24373 T7 2398


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2469438 1 T1 1632 T2 23420 T7 2002
auto[1] 4244934 1 T1 1613 T2 25025 T3 1


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3006589 1 T1 1272 T2 19278 T3 1
auto[1] 3707783 1 T1 1973 T2 29167 T7 1473


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4238012 1 T1 1832 T2 25769 T3 1
auto[1] 2476360 1 T1 1413 T2 22676 T7 11


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6159273 1 T1 3070 T2 28465 T3 1
fifo_depth[1] 105348 1 T1 35 T2 803 T7 116
fifo_depth[2] 72959 1 T1 29 T2 770 T7 104
fifo_depth[3] 54851 1 T1 24 T2 689 T7 68
fifo_depth[4] 50265 1 T1 15 T2 730 T7 28
fifo_depth[5] 40760 1 T1 22 T2 570 T7 10
fifo_depth[6] 32151 1 T1 20 T2 488 T7 1
fifo_depth[7] 21426 1 T1 18 T2 428 T8 99


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 555099 1 T1 175 T2 19980 T7 327
auto[1] 6159273 1 T1 3070 T2 28465 T3 1


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6703615 1 T1 3245 T2 48115 T3 1
auto[1] 10757 1 T2 330 T6 46 T21 750


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 29396 1 T2 1996 T5 22 T12 1
auto[0] auto[0] auto[0] auto[0] auto[1] 27704 1 T1 151 T2 872 T5 6
auto[0] auto[0] auto[0] auto[1] auto[0] 21201 1 T2 1798 T7 152 T12 27
auto[0] auto[0] auto[0] auto[1] auto[1] 21830 1 T1 7 T2 11 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] 91593 1 T2 1024 T7 169 T5 4
auto[0] auto[0] auto[1] auto[0] auto[1] 28408 1 T2 38 T8 220 T6 745
auto[0] auto[0] auto[1] auto[1] auto[0] 28788 1 T2 520 T5 4 T8 303
auto[0] auto[0] auto[1] auto[1] auto[1] 21132 1 T1 17 T2 1678 T5 14
auto[0] auto[1] auto[0] auto[0] auto[0] 29900 1 T2 1322 T5 2 T8 117
auto[0] auto[1] auto[0] auto[0] auto[1] 32279 1 T2 1708 T5 86 T8 61
auto[0] auto[1] auto[0] auto[1] auto[0] 32836 1 T2 1601 T4 4 T5 332
auto[0] auto[1] auto[0] auto[1] auto[1] 38560 1 T2 1181 T4 3 T5 33
auto[0] auto[1] auto[1] auto[0] auto[0] 47139 1 T2 4268 T5 4 T12 11
auto[0] auto[1] auto[1] auto[0] auto[1] 29159 1 T2 79 T5 18 T8 6
auto[0] auto[1] auto[1] auto[1] auto[0] 37640 1 T2 331 T7 6 T4 2
auto[0] auto[1] auto[1] auto[1] auto[1] 37534 1 T2 1553 T4 3 T5 44
auto[1] auto[0] auto[0] auto[0] auto[0] 155969 1 T2 676 T4 15 T5 619
auto[1] auto[0] auto[0] auto[0] auto[1] 144939 1 T1 531 T2 2444 T7 1
auto[1] auto[0] auto[0] auto[1] auto[0] 152926 1 T2 2102 T7 1607 T4 55
auto[1] auto[0] auto[0] auto[1] auto[1] 142511 1 T1 31 T2 906 T7 2
auto[1] auto[0] auto[1] auto[0] auto[0] 1706819 1 T1 328 T2 1344 T3 1
auto[1] auto[0] auto[1] auto[0] auto[1] 152634 1 T2 1043 T7 1 T5 553
auto[1] auto[0] auto[1] auto[1] auto[0] 148772 1 T1 1 T2 1706 T7 1
auto[1] auto[0] auto[1] auto[1] auto[1] 131967 1 T1 206 T2 1120 T7 1
auto[1] auto[1] auto[0] auto[0] auto[0] 397886 1 T2 2822 T7 238 T5 1922
auto[1] auto[1] auto[0] auto[0] auto[1] 398186 1 T2 1387 T7 2 T4 11
auto[1] auto[1] auto[0] auto[1] auto[0] 422848 1 T1 445 T2 1326 T4 19
auto[1] auto[1] auto[0] auto[1] auto[1] 420467 1 T1 467 T2 1268 T4 130
auto[1] auto[1] auto[1] auto[0] auto[0] 452223 1 T1 807 T2 1482 T7 596
auto[1] auto[1] auto[1] auto[0] auto[1] 443375 1 T1 3 T2 1567 T7 2
auto[1] auto[1] auto[1] auto[1] auto[0] 482076 1 T1 251 T2 1451 T7 627
auto[1] auto[1] auto[1] auto[1] auto[1] 405675 1 T2 5821 T7 2 T4 38


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 184800 1 T2 2671 T4 15 T5 641
auto[0] auto[0] auto[0] auto[0] auto[1] 169887 1 T1 682 T2 3303 T7 1
auto[0] auto[0] auto[0] auto[1] auto[0] 173982 1 T2 3880 T7 1759 T4 55
auto[0] auto[0] auto[0] auto[1] auto[1] 164086 1 T1 38 T2 917 T7 2
auto[0] auto[0] auto[1] auto[0] auto[0] 1798117 1 T1 328 T2 2352 T3 1
auto[0] auto[0] auto[1] auto[0] auto[1] 179858 1 T2 1081 T7 1 T5 553
auto[0] auto[0] auto[1] auto[1] auto[0] 176621 1 T1 1 T2 2226 T7 1
auto[0] auto[0] auto[1] auto[1] auto[1] 152827 1 T1 223 T2 2770 T7 1
auto[0] auto[1] auto[0] auto[0] auto[0] 427211 1 T2 4144 T7 238 T5 1924
auto[0] auto[1] auto[0] auto[0] auto[1] 430194 1 T2 3060 T7 2 T4 11
auto[0] auto[1] auto[0] auto[1] auto[0] 455119 1 T1 445 T2 2923 T4 23
auto[0] auto[1] auto[0] auto[1] auto[1] 458573 1 T1 467 T2 2356 T4 133
auto[0] auto[1] auto[1] auto[0] auto[0] 499200 1 T1 807 T2 5630 T7 596
auto[0] auto[1] auto[1] auto[0] auto[1] 472530 1 T1 3 T2 1646 T7 2
auto[0] auto[1] auto[1] auto[1] auto[0] 519559 1 T1 251 T2 1782 T7 633
auto[0] auto[1] auto[1] auto[1] auto[1] 441051 1 T2 7374 T7 2 T4 41
auto[1] auto[0] auto[0] auto[0] auto[0] 565 1 T2 1 T21 32 T122 1
auto[1] auto[0] auto[0] auto[0] auto[1] 2756 1 T2 13 T6 9 T21 143
auto[1] auto[0] auto[0] auto[1] auto[0] 145 1 T2 20 T21 6 T122 35
auto[1] auto[0] auto[0] auto[1] auto[1] 255 1 T6 4 T122 136 T29 5
auto[1] auto[0] auto[1] auto[0] auto[0] 295 1 T2 16 T6 3 T122 1
auto[1] auto[0] auto[1] auto[0] auto[1] 1184 1 T6 5 T21 209 T140 6
auto[1] auto[0] auto[1] auto[1] auto[0] 939 1 T6 13 T140 116 T29 183
auto[1] auto[0] auto[1] auto[1] auto[1] 272 1 T2 28 T6 1 T21 13
auto[1] auto[1] auto[0] auto[0] auto[0] 575 1 T21 346 T140 88 T29 51
auto[1] auto[1] auto[0] auto[0] auto[1] 271 1 T2 35 T6 2 T141 230
auto[1] auto[1] auto[0] auto[1] auto[0] 565 1 T2 4 T140 103 T29 6
auto[1] auto[1] auto[0] auto[1] auto[1] 454 1 T2 93 T62 1 T44 14
auto[1] auto[1] auto[1] auto[0] auto[0] 162 1 T2 120 T6 1 T21 1
auto[1] auto[1] auto[1] auto[0] auto[1] 4 1 T76 4 - - - -
auto[1] auto[1] auto[1] auto[1] auto[0] 157 1 T29 84 T142 73 - -
auto[1] auto[1] auto[1] auto[1] auto[1] 2158 1 T6 8 T29 69 T78 124


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 155969 1 T2 676 T4 15 T5 619
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 144939 1 T1 531 T2 2444 T7 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 152926 1 T2 2102 T7 1607 T4 55
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 142511 1 T1 31 T2 906 T7 2
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1706819 1 T1 328 T2 1344 T3 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 152634 1 T2 1043 T7 1 T5 553
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 148772 1 T1 1 T2 1706 T7 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 131967 1 T1 206 T2 1120 T7 1
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 397886 1 T2 2822 T7 238 T5 1922
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 398186 1 T2 1387 T7 2 T4 11
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 422848 1 T1 445 T2 1326 T4 19
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 420467 1 T1 467 T2 1268 T4 130
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 452223 1 T1 807 T2 1482 T7 596
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 443375 1 T1 3 T2 1567 T7 2
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 482076 1 T1 251 T2 1451 T7 627
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 405675 1 T2 5821 T7 2 T4 38
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3296 1 T2 26 T5 15 T12 1
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3379 1 T1 23 T2 166 T5 3
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3054 1 T2 70 T7 54 T12 20
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 2876 1 T1 2 T5 1 T8 9
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 35093 1 T2 13 T7 58 T5 2
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3055 1 T2 5 T8 33 T6 28
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3301 1 T2 37 T5 3 T8 65
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3069 1 T1 10 T2 38 T5 11
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 4353 1 T2 82 T5 1 T8 15
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5937 1 T2 44 T5 68 T8 10
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5239 1 T2 41 T4 2 T5 256
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6051 1 T2 7 T4 2 T5 30
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8560 1 T2 18 T5 4 T12 10
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5761 1 T2 12 T5 15 T8 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7021 1 T7 4 T5 9 T12 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5303 1 T2 244 T4 1 T5 35
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2790 1 T2 24 T5 4 T6 4
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2892 1 T1 23 T2 139 T5 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2229 1 T2 61 T7 46 T12 4
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2159 1 T1 3 T8 21 T6 146
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 16129 1 T2 13 T7 56 T5 2
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2344 1 T2 9 T8 37 T6 30
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2527 1 T2 48 T8 69 T6 134
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2376 1 T1 3 T2 23 T5 3
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 3851 1 T2 82 T5 1 T8 23
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4716 1 T2 37 T5 15 T8 8
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4012 1 T2 41 T4 1 T5 66
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4644 1 T2 7 T4 1 T5 3
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6980 1 T2 42 T12 1 T8 38
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4971 1 T2 9 T5 2 T8 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5970 1 T2 2 T7 2 T5 3
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4369 1 T2 233 T4 1 T5 7
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2066 1 T2 25 T5 3 T6 6
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2024 1 T1 20 T2 55 T12 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1585 1 T2 69 T7 39 T12 2
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1638 1 T8 13 T6 134 T23 24
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 9375 1 T2 14 T7 29 T8 11
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1756 1 T2 6 T8 29 T6 12
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1798 1 T2 39 T5 1 T8 53
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1860 1 T1 4 T2 38 T8 13
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3033 1 T2 79 T8 19 T6 32
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3906 1 T2 18 T5 3 T8 11
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3381 1 T2 48 T4 1 T5 8
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3890 1 T2 10 T6 199 T23 32
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5437 1 T2 37 T8 31 T6 89
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3941 1 T2 10 T5 1 T8 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5417 1 T4 2 T6 197 T23 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3744 1 T2 241 T5 2 T8 6
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2096 1 T2 27 T6 5 T23 6
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2101 1 T1 15 T2 32 T5 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1605 1 T2 72 T7 12 T12 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1718 1 T2 2 T8 7 T6 146
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 6633 1 T2 19 T7 16 T8 10
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1769 1 T2 4 T8 31 T6 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1686 1 T2 43 T8 42 T6 95
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 1923 1 T2 59 T8 8 T6 180
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 2962 1 T2 77 T8 15 T6 58
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3578 1 T2 13 T8 10 T6 72
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3135 1 T2 40 T5 2 T6 6
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3756 1 T2 11 T6 151 T23 26
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5133 1 T2 92 T8 21 T6 143
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3770 1 T2 11 T8 1 T6 21
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4929 1 T2 2 T6 172 T23 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3471 1 T2 226 T4 1 T8 11
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1567 1 T2 28 T6 5 T23 6
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1389 1 T1 21 T2 10 T6 49
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1226 1 T2 63 T7 1 T8 24
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1378 1 T1 1 T8 19 T6 96
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 4790 1 T2 12 T7 9 T8 13
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1128 1 T2 3 T8 21 T6 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1479 1 T2 41 T8 34 T6 97
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1356 1 T2 33 T8 8 T6 157
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2642 1 T2 57 T8 12 T6 52
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3062 1 T2 8 T8 5 T6 64
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 2628 1 T2 40 T6 11 T23 33
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3244 1 T2 5 T6 166 T23 17
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4313 1 T2 55 T8 19 T6 79
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3237 1 T2 11 T6 24 T50 116
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4328 1 T2 10 T6 145 T47 46
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 2993 1 T2 194 T8 8 T6 177
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1297 1 T2 29 T23 4 T119 7
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1283 1 T1 19 T2 6 T6 29
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 924 1 T2 46 T8 12 T6 33
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 999 1 T1 1 T8 10 T6 81
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 3378 1 T2 10 T7 1 T8 11
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 960 1 T2 5 T8 32 T6 3
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1115 1 T2 36 T8 18 T6 44
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1106 1 T2 18 T8 10 T6 90
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2203 1 T2 53 T8 11 T6 52
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2455 1 T2 1 T8 7 T6 69
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2167 1 T2 28 T6 13 T23 15
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2521 1 T2 12 T6 139 T23 14
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3437 1 T2 55 T8 6 T6 109
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2460 1 T2 7 T8 1 T6 24
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3424 1 T2 4 T6 90 T47 19
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2422 1 T2 178 T8 7 T6 196
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 918 1 T2 30 T6 4 T23 6
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 703 1 T1 18 T2 2 T6 27
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 645 1 T2 47 T8 12 T6 22
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 737 1 T8 9 T6 59 T23 5
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 1996 1 T2 16 T8 11 T6 40
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 549 1 T2 4 T8 20 T21 30
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 758 1 T2 15 T8 13 T6 29
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 712 1 T2 32 T8 8 T6 61
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1482 1 T2 29 T8 12 T6 47
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1610 1 T2 4 T8 6 T6 43
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1444 1 T2 21 T6 6 T23 9
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1817 1 T2 15 T6 86 T23 4
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2362 1 T2 72 T8 4 T6 43
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1781 1 T2 6 T8 1 T6 14
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2330 1 T2 10 T6 47 T47 4
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1582 1 T2 125 T8 3 T6 168

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