Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16772559	1			T1	17935		T2	93470		T3	3
all_pins[1]	16772559	1			T1	17935		T2	93470		T3	3
all_pins[2]	16772559	1			T1	17935		T2	93470		T3	3

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42930565	1			T1	41902		T2	233847		T3	8
values[0x1]	7387112	1			T1	11903		T2	46563		T3	1
transitions[0x0=>0x1]	7386969	1			T1	11903		T2	46563		T3	1
transitions[0x1=>0x0]	7386988	1			T1	11903		T2	46563		T3	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16753364	1			T1	17932		T2	93243		T3	3
all_pins[0]	values[0x1]	19195	1			T1	3		T2	227		T7	6
all_pins[0]	transitions[0x0=>0x1]	19133	1			T1	3		T2	227		T7	6
all_pins[0]	transitions[0x1=>0x0]	7367603	1			T1	11900		T2	46331		T3	1
all_pins[1]	values[0x0]	16772288	1			T1	17935		T2	93465		T3	3
all_pins[1]	values[0x1]	271	1			T2	5		T5	1		T6	10
all_pins[1]	transitions[0x0=>0x1]	227	1			T2	5		T5	1		T6	8
all_pins[1]	transitions[0x1=>0x0]	19151	1			T1	3		T2	227		T7	6
all_pins[2]	values[0x0]	9404913	1			T1	6035		T2	47139		T3	2
all_pins[2]	values[0x1]	7367646	1			T1	11900		T2	46331		T3	1
all_pins[2]	transitions[0x0=>0x1]	7367609	1			T1	11900		T2	46331		T3	1
all_pins[2]	transitions[0x1=>0x0]	234	1			T2	5		T5	1		T6	10