Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 756 1 T5 14 T6 14 T70 24
all_values[1] 756 1 T5 14 T6 14 T70 24
all_values[2] 756 1 T5 14 T6 14 T70 24


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1127 1 T5 17 T6 22 T70 34
auto[1] 1141 1 T5 25 T6 20 T70 38


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 810 1 T5 27 T6 12 T70 32
auto[1] 1458 1 T5 15 T6 30 T70 40


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1304 1 T5 34 T6 22 T70 43
auto[1] 964 1 T5 8 T6 20 T70 29


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 145 1 T5 2 T6 2 T70 3
all_values[0] auto[0] auto[0] auto[1] 64 1 T6 1 T70 1 T121 1
all_values[0] auto[0] auto[1] auto[0] 152 1 T5 6 T6 3 T70 6
all_values[0] auto[0] auto[1] auto[1] 86 1 T5 3 T6 2 T70 2
all_values[0] auto[1] auto[0] auto[1] 156 1 T5 2 T6 2 T70 6
all_values[0] auto[1] auto[1] auto[1] 153 1 T5 1 T6 4 T70 6
all_values[1] auto[0] auto[0] auto[0] 107 1 T5 4 T6 1 T70 4
all_values[1] auto[0] auto[0] auto[1] 101 1 T6 2 T70 3 T121 1
all_values[1] auto[0] auto[1] auto[0] 116 1 T5 5 T6 2 T70 6
all_values[1] auto[0] auto[1] auto[1] 98 1 T5 2 T6 2 T70 3
all_values[1] auto[1] auto[0] auto[1] 178 1 T5 2 T6 4 T70 3
all_values[1] auto[1] auto[1] auto[1] 156 1 T5 1 T6 3 T70 5
all_values[2] auto[0] auto[0] auto[0] 142 1 T5 6 T6 4 T70 8
all_values[2] auto[0] auto[0] auto[1] 75 1 T6 3 T70 2 T122 1
all_values[2] auto[0] auto[1] auto[0] 148 1 T5 4 T70 5 T121 4
all_values[2] auto[0] auto[1] auto[1] 70 1 T5 2 T30 2 T14 1
all_values[2] auto[1] auto[0] auto[1] 159 1 T5 1 T6 3 T70 4
all_values[2] auto[1] auto[1] auto[1] 162 1 T5 1 T6 4 T70 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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