Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3846	1			T1	5		T2	67		T3	1
sha2_none	3775	1			T1	3		T2	88		T7	1
sha2_512	7131	1			T1	1		T2	80		T7	1
sha2_384	6943	1			T1	3		T2	71		T7	6
sha2_256	5549	1			T1	3		T2	89		T7	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17413

1

T1

6

T2

209

T3

1

auto[1]

10181

1

T1

9

T2

189

T7

14

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10164

1

T1

9

T2

209

T7

12

auto[1]

17430

1

T1

6

T2

189

T3

1

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14250

1

T1

9

T2

197

T7

14

disabled

13344

1

T1

6

T2

201

T3

1

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4005	1			T1	4		T2	81		T7	8
key_none	7382	1			T1	1		T2	59		T3	1
key_1024	4102	1			T1	2		T2	51		T7	3
key_512	3497	1			T1	4		T2	61		T7	7
key_384	3131	1			T1	1		T2	49		T7	2
key_256	2647	1			T1	1		T2	40		T7	2
key_128	2760	1			T1	2		T2	56		T7	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17593

1

T1

6

T2

197

T3

1

auto[1]

10001

1

T1

9

T2

201

T7

7

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

27431

1

T1

14

T2

397

T3

1

disabled

163

1

T1

1

T2

1

T7

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1397

1

T1

1

T2

32

T7

2

enabled

auto[0]

auto[0]

auto[1]

1318

1

T2

28

T7

2

T4

1

enabled

auto[0]

auto[1]

auto[0]

1552

1

T1

1

T2

23

T4

1

enabled

auto[0]

auto[1]

auto[1]

1483

1

T1

3

T2

23

T7

1

enabled

auto[1]

auto[0]

auto[0]

4115

1

T1

2

T2

22

T7

3

enabled

auto[1]

auto[0]

auto[1]

1471

1

T1

1

T2

26

T4

2

enabled

auto[1]

auto[1]

auto[0]

1496

1

T1

1

T2

19

T7

5

enabled

auto[1]

auto[1]

auto[1]

1418

1

T2

24

T7

1

T4

1

disabled

auto[0]

auto[0]

auto[0]

1137

1

T2

23

T4

1

T5

7

disabled

auto[0]

auto[0]

auto[1]

1138

1

T1

1

T2

30

T7

1

disabled

auto[0]

auto[1]

auto[0]

1102

1

T2

26

T7

5

T4

3

disabled

auto[0]

auto[1]

auto[1]

1037

1

T1

3

T2

24

T7

1

disabled

auto[1]

auto[0]

auto[0]

5736

1

T1

1

T2

31

T3

1

disabled

auto[1]

auto[0]

auto[1]

1101

1

T2

17

T7

1

T5

11

disabled

auto[1]

auto[1]

auto[0]

1058

1

T2

21

T7

1

T5

9

disabled

auto[1]

auto[1]

auto[1]

1035

1

T1

1

T2

29

T4

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14190

1

T1

9

T2

197

T7

12

enabled

disabled

60

1

T7

2

T12

2

T6

2

disabled

disabled

103

1

T1

1

T2

1

T7

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13241

1

T1

5

T2

200

T3

1

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	955	1			T1	1		T2	15		T7	4
key_invalid	sha2_none	719	1			T1	1		T2	16		T7	1
key_invalid	sha2_512	762	1			T2	17		T4	1		T5	9
key_invalid	sha2_384	746	1			T1	2		T2	15		T7	1
key_invalid	sha2_256	725	1			T2	17		T7	2		T4	1
key_none	sha2_invalid	501	1			T2	12		T3	1		T5	3
key_none	sha2_none	529	1			T2	13		T5	7		T6	9
key_none	sha2_512	2502	1			T2	10		T5	3		T6	12
key_none	sha2_384	2483	1			T1	1		T2	8		T4	1
key_none	sha2_256	1313	1			T2	16		T5	2		T12	2
key_1024	sha2_invalid	513	1			T2	7		T7	1		T4	1
key_1024	sha2_none	495	1			T1	2		T2	10		T5	3
key_1024	sha2_512	1650	1			T2	13		T5	6		T6	7
key_1024	sha2_384	888	1			T2	11		T7	1		T4	1
key_512	sha2_invalid	470	1			T1	2		T2	15		T7	1
key_512	sha2_none	502	1			T2	14		T5	7		T12	4
key_512	sha2_512	538	1			T2	9		T7	1		T5	5
key_512	sha2_384	1181	1			T2	11		T7	2		T4	1
key_512	sha2_256	775	1			T1	2		T2	12		T7	3
key_384	sha2_invalid	480	1			T1	1		T2	4		T7	1
key_384	sha2_none	463	1			T2	8		T5	4		T12	1
key_384	sha2_512	553	1			T2	11		T4	1		T5	5
key_384	sha2_384	561	1			T2	9		T4	1		T5	2
key_384	sha2_256	1037	1			T2	17		T4	1		T5	9
key_256	sha2_invalid	449	1			T1	1		T2	4		T7	1
key_256	sha2_none	498	1			T2	11		T4	1		T5	3
key_256	sha2_512	536	1			T2	6		T4	1		T5	6
key_256	sha2_384	526	1			T2	8		T7	1		T5	4
key_256	sha2_256	606	1			T2	11		T5	6		T12	1
key_128	sha2_invalid	465	1			T2	10		T7	1		T4	1
key_128	sha2_none	555	1			T2	16		T4	1		T5	8
key_128	sha2_512	573	1			T1	1		T2	14		T4	2
key_128	sha2_384	546	1			T2	8		T7	1		T5	1
key_128	sha2_256	576	1			T1	1		T2	7		T7	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

505

1

T2

9

T7

1

T5

7

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	955	1			T1	1		T2	15		T7	4
key_invalid	sha2_none	719	1			T1	1		T2	16		T7	1
key_invalid	sha2_512	762	1			T2	17		T4	1		T5	9
key_invalid	sha2_384	746	1			T1	2		T2	15		T7	1
key_invalid	sha2_256	725	1			T2	17		T7	2		T4	1
key_none	sha2_invalid	501	1			T2	12		T3	1		T5	3
key_none	sha2_none	529	1			T2	13		T5	7		T6	9
key_none	sha2_512	2502	1			T2	10		T5	3		T6	12
key_none	sha2_384	2483	1			T1	1		T2	8		T4	1
key_none	sha2_256	1313	1			T2	16		T5	2		T12	2
key_1024	sha2_invalid	513	1			T2	7		T7	1		T4	1
key_1024	sha2_none	495	1			T1	2		T2	10		T5	3
key_1024	sha2_512	1650	1			T2	13		T5	6		T6	7
key_1024	sha2_384	888	1			T2	11		T7	1		T4	1
key_1024	sha2_256	505	1			T2	9		T7	1		T5	7
key_512	sha2_invalid	470	1			T1	2		T2	15		T7	1
key_512	sha2_none	502	1			T2	14		T5	7		T12	4
key_512	sha2_512	538	1			T2	9		T7	1		T5	5
key_512	sha2_384	1181	1			T2	11		T7	2		T4	1
key_512	sha2_256	775	1			T1	2		T2	12		T7	3
key_384	sha2_invalid	480	1			T1	1		T2	4		T7	1
key_384	sha2_none	463	1			T2	8		T5	4		T12	1
key_384	sha2_512	553	1			T2	11		T4	1		T5	5
key_384	sha2_384	561	1			T2	9		T4	1		T5	2
key_384	sha2_256	1037	1			T2	17		T4	1		T5	9
key_256	sha2_invalid	449	1			T1	1		T2	4		T7	1
key_256	sha2_none	498	1			T2	11		T4	1		T5	3
key_256	sha2_512	536	1			T2	6		T4	1		T5	6
key_256	sha2_384	526	1			T2	8		T7	1		T5	4
key_256	sha2_256	606	1			T2	11		T5	6		T12	1
key_128	sha2_invalid	465	1			T2	10		T7	1		T4	1
key_128	sha2_none	555	1			T2	16		T4	1		T5	8
key_128	sha2_512	573	1			T1	1		T2	14		T4	2
key_128	sha2_384	546	1			T2	8		T7	1		T5	1
key_128	sha2_256	576	1			T1	1		T2	7		T7	1