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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 651
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T539 /workspace/coverage/cover_reg_top/48.hmac_intr_test.659148190 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:13 PM PDT 24 41430074 ps
T90 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1614704440 Aug 17 05:54:02 PM PDT 24 Aug 17 05:54:05 PM PDT 24 42645693 ps
T540 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.436308382 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:05 PM PDT 24 19574105 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.13335738 Aug 17 05:53:55 PM PDT 24 Aug 17 05:53:56 PM PDT 24 29422495 ps
T541 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2578522957 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 22525451 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1362314938 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:55 PM PDT 24 109170741 ps
T69 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.875441073 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:06 PM PDT 24 244545850 ps
T542 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2775550969 Aug 17 05:54:05 PM PDT 24 Aug 17 06:00:59 PM PDT 24 42591630633 ps
T113 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3861981390 Aug 17 05:53:49 PM PDT 24 Aug 17 05:53:51 PM PDT 24 410994198 ps
T543 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2678829095 Aug 17 05:53:50 PM PDT 24 Aug 17 05:53:51 PM PDT 24 90144641 ps
T544 /workspace/coverage/cover_reg_top/5.hmac_intr_test.275458788 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:52 PM PDT 24 56672593 ps
T545 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1644660773 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:55 PM PDT 24 23123210 ps
T546 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.609519851 Aug 17 05:53:50 PM PDT 24 Aug 17 05:53:54 PM PDT 24 334144084 ps
T114 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2695734034 Aug 17 05:53:49 PM PDT 24 Aug 17 05:53:50 PM PDT 24 112648232 ps
T127 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4273711389 Aug 17 05:53:49 PM PDT 24 Aug 17 05:53:53 PM PDT 24 285144436 ps
T547 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2927664269 Aug 17 05:54:18 PM PDT 24 Aug 17 05:54:18 PM PDT 24 55718892 ps
T98 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2993496236 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:57 PM PDT 24 307740458 ps
T133 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2188098408 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:50 PM PDT 24 90272087 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2457456504 Aug 17 05:54:10 PM PDT 24 Aug 17 05:54:11 PM PDT 24 26295291 ps
T548 /workspace/coverage/cover_reg_top/17.hmac_intr_test.79221813 Aug 17 05:54:08 PM PDT 24 Aug 17 05:54:09 PM PDT 24 16897480 ps
T549 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3844355374 Aug 17 05:54:06 PM PDT 24 Aug 17 05:54:07 PM PDT 24 24264068 ps
T116 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2993180477 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:56 PM PDT 24 85886286 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3378829055 Aug 17 05:53:57 PM PDT 24 Aug 17 05:53:58 PM PDT 24 42465405 ps
T550 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2761405882 Aug 17 05:53:57 PM PDT 24 Aug 17 05:53:58 PM PDT 24 48840999 ps
T117 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3904872181 Aug 17 05:54:02 PM PDT 24 Aug 17 05:54:03 PM PDT 24 162503682 ps
T551 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4145874774 Aug 17 05:53:58 PM PDT 24 Aug 17 05:53:58 PM PDT 24 19017426 ps
T552 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2265290553 Aug 17 05:54:03 PM PDT 24 Aug 17 05:54:03 PM PDT 24 43974711 ps
T100 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1055963054 Aug 17 05:53:55 PM PDT 24 Aug 17 05:53:56 PM PDT 24 31213189 ps
T134 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3507002145 Aug 17 05:54:02 PM PDT 24 Aug 17 05:54:04 PM PDT 24 287054641 ps
T553 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2498561558 Aug 17 05:54:03 PM PDT 24 Aug 17 05:54:05 PM PDT 24 26203455 ps
T554 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3067540708 Aug 17 05:54:06 PM PDT 24 Aug 17 05:54:07 PM PDT 24 14500256 ps
T555 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1584419078 Aug 17 05:53:49 PM PDT 24 Aug 17 05:53:50 PM PDT 24 32654290 ps
T128 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1522012613 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:17 PM PDT 24 504949449 ps
T556 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.208116154 Aug 17 05:54:03 PM PDT 24 Aug 17 05:54:06 PM PDT 24 376866555 ps
T557 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1752714482 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:06 PM PDT 24 59646624 ps
T558 /workspace/coverage/cover_reg_top/30.hmac_intr_test.168900406 Aug 17 05:54:12 PM PDT 24 Aug 17 05:54:12 PM PDT 24 36270456 ps
T124 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1534396378 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:53 PM PDT 24 599000033 ps
T559 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2292884082 Aug 17 05:54:14 PM PDT 24 Aug 17 05:54:15 PM PDT 24 33217120 ps
T560 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1049060688 Aug 17 05:54:14 PM PDT 24 Aug 17 05:54:15 PM PDT 24 15631522 ps
T561 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1461870751 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:05 PM PDT 24 11839420 ps
T101 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2721641379 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:17 PM PDT 24 221705153 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2564363062 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 24975023 ps
T118 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1412938612 Aug 17 05:53:49 PM PDT 24 Aug 17 05:53:51 PM PDT 24 187666136 ps
T103 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1728512331 Aug 17 05:54:14 PM PDT 24 Aug 17 05:54:14 PM PDT 24 12554561 ps
T562 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.575659945 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:07 PM PDT 24 103755704 ps
T563 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3609183796 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:55 PM PDT 24 30145634 ps
T564 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.981850668 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:53 PM PDT 24 127955098 ps
T565 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1081797198 Aug 17 05:54:10 PM PDT 24 Aug 17 05:54:12 PM PDT 24 278405516 ps
T566 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3211852076 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:49 PM PDT 24 18009845 ps
T104 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1165620384 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:51 PM PDT 24 20666892 ps
T567 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1252800114 Aug 17 05:53:44 PM PDT 24 Aug 17 05:53:47 PM PDT 24 252052913 ps
T105 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4068419800 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 52840493 ps
T568 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1070613632 Aug 17 05:53:44 PM PDT 24 Aug 17 05:53:48 PM PDT 24 192246507 ps
T569 /workspace/coverage/cover_reg_top/0.hmac_intr_test.83134935 Aug 17 05:53:47 PM PDT 24 Aug 17 05:53:47 PM PDT 24 36374356 ps
T570 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3689834082 Aug 17 05:54:03 PM PDT 24 Aug 17 05:54:04 PM PDT 24 22950765 ps
T106 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1881732151 Aug 17 05:53:57 PM PDT 24 Aug 17 05:53:57 PM PDT 24 81094702 ps
T131 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1427971678 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:55 PM PDT 24 95995867 ps
T571 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3152058939 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:08 PM PDT 24 79369078 ps
T129 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.97365868 Aug 17 05:53:58 PM PDT 24 Aug 17 05:54:02 PM PDT 24 459563178 ps
T107 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2815284441 Aug 17 05:53:56 PM PDT 24 Aug 17 05:53:57 PM PDT 24 17770305 ps
T572 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4207785409 Aug 17 05:54:01 PM PDT 24 Aug 17 05:54:04 PM PDT 24 152370981 ps
T135 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.899607365 Aug 17 05:53:59 PM PDT 24 Aug 17 05:54:03 PM PDT 24 646261349 ps
T573 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1840826426 Aug 17 05:54:00 PM PDT 24 Aug 17 05:54:01 PM PDT 24 59258652 ps
T574 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4212275857 Aug 17 05:54:07 PM PDT 24 Aug 17 05:54:07 PM PDT 24 23290565 ps
T575 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1402798431 Aug 17 05:54:00 PM PDT 24 Aug 17 05:54:00 PM PDT 24 23708535 ps
T576 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3464752218 Aug 17 05:54:08 PM PDT 24 Aug 17 05:54:10 PM PDT 24 32928219 ps
T577 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1480987229 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:06 PM PDT 24 113846915 ps
T578 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3363723900 Aug 17 05:53:56 PM PDT 24 Aug 17 05:53:57 PM PDT 24 13708609 ps
T579 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4183662547 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:56 PM PDT 24 74714455 ps
T580 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3016728034 Aug 17 05:53:46 PM PDT 24 Aug 17 05:53:46 PM PDT 24 45945888 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3583247232 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:05 PM PDT 24 48425970 ps
T582 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4290703184 Aug 17 05:53:56 PM PDT 24 Aug 17 05:54:00 PM PDT 24 248500022 ps
T583 /workspace/coverage/cover_reg_top/46.hmac_intr_test.4209330478 Aug 17 05:54:15 PM PDT 24 Aug 17 05:54:16 PM PDT 24 53153560 ps
T584 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3549910552 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:08 PM PDT 24 276470928 ps
T585 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4144281569 Aug 17 05:53:51 PM PDT 24 Aug 17 05:54:01 PM PDT 24 334035064 ps
T586 /workspace/coverage/cover_reg_top/26.hmac_intr_test.4026296381 Aug 17 05:54:14 PM PDT 24 Aug 17 05:54:15 PM PDT 24 13360576 ps
T587 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2578168707 Aug 17 05:54:17 PM PDT 24 Aug 17 05:54:18 PM PDT 24 45924873 ps
T588 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.757058544 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:06 PM PDT 24 43582080 ps
T589 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3782222022 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:14 PM PDT 24 130579305 ps
T590 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.98070852 Aug 17 05:53:56 PM PDT 24 Aug 17 05:53:59 PM PDT 24 169474910 ps
T591 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1148947893 Aug 17 05:53:49 PM PDT 24 Aug 17 05:54:00 PM PDT 24 1853094330 ps
T592 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1889296181 Aug 17 05:53:55 PM PDT 24 Aug 17 05:53:57 PM PDT 24 25737513 ps
T593 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.126376372 Aug 17 05:53:59 PM PDT 24 Aug 17 05:54:01 PM PDT 24 382186238 ps
T594 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2559858838 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:14 PM PDT 24 16260250 ps
T595 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.135153460 Aug 17 05:54:08 PM PDT 24 Aug 17 05:54:10 PM PDT 24 83334682 ps
T596 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2397021268 Aug 17 05:54:07 PM PDT 24 Aug 17 05:54:10 PM PDT 24 183302853 ps
T132 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3639821904 Aug 17 05:53:52 PM PDT 24 Aug 17 05:53:55 PM PDT 24 86033754 ps
T597 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2874106370 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:06 PM PDT 24 67446456 ps
T125 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3433775052 Aug 17 05:53:57 PM PDT 24 Aug 17 05:54:02 PM PDT 24 543873848 ps
T598 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1375473022 Aug 17 05:53:57 PM PDT 24 Aug 17 05:53:58 PM PDT 24 41845004 ps
T599 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2295936247 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:10 PM PDT 24 17073785 ps
T600 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2755290358 Aug 17 05:54:08 PM PDT 24 Aug 17 05:54:08 PM PDT 24 15475293 ps
T601 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3874480737 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:52 PM PDT 24 164602852 ps
T602 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3317676205 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:14 PM PDT 24 53436004 ps
T603 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2711510261 Aug 17 05:53:56 PM PDT 24 Aug 17 05:53:58 PM PDT 24 36184970 ps
T604 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3297126341 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:13 PM PDT 24 76087660 ps
T111 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2658989155 Aug 17 05:54:11 PM PDT 24 Aug 17 05:54:12 PM PDT 24 26406967 ps
T605 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3695097823 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:56 PM PDT 24 73700372 ps
T136 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2432582480 Aug 17 05:54:00 PM PDT 24 Aug 17 05:54:02 PM PDT 24 424040160 ps
T606 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.833077741 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:56 PM PDT 24 203255938 ps
T607 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2780925129 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:06 PM PDT 24 92136777 ps
T608 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1373894999 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:50 PM PDT 24 273485371 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2210937038 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:49 PM PDT 24 17453954 ps
T610 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2855024521 Aug 17 05:53:44 PM PDT 24 Aug 17 05:53:47 PM PDT 24 715255355 ps
T126 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2104009591 Aug 17 05:53:57 PM PDT 24 Aug 17 05:54:02 PM PDT 24 536916486 ps
T108 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.325059967 Aug 17 05:54:07 PM PDT 24 Aug 17 05:54:08 PM PDT 24 47223408 ps
T611 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1040330538 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:10 PM PDT 24 42674688 ps
T612 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1166608070 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:54 PM PDT 24 71403672 ps
T613 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1717809142 Aug 17 05:53:56 PM PDT 24 Aug 17 05:53:56 PM PDT 24 31101923 ps
T614 /workspace/coverage/cover_reg_top/11.hmac_intr_test.961392055 Aug 17 05:54:03 PM PDT 24 Aug 17 05:54:04 PM PDT 24 55477805 ps
T615 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2574302180 Aug 17 05:54:01 PM PDT 24 Aug 17 05:54:01 PM PDT 24 16775221 ps
T616 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.606440244 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:54 PM PDT 24 358397020 ps
T112 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3330582266 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 30712426 ps
T109 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1480554488 Aug 17 05:54:11 PM PDT 24 Aug 17 05:54:12 PM PDT 24 18730889 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2506470961 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:54 PM PDT 24 42420916 ps
T618 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1841327223 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 24428215 ps
T619 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3109565490 Aug 17 05:54:04 PM PDT 24 Aug 17 05:54:05 PM PDT 24 15418466 ps
T130 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2250751742 Aug 17 05:53:47 PM PDT 24 Aug 17 05:53:49 PM PDT 24 338165723 ps
T620 /workspace/coverage/cover_reg_top/24.hmac_intr_test.3837381789 Aug 17 05:54:15 PM PDT 24 Aug 17 05:54:16 PM PDT 24 12015446 ps
T621 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2052318790 Aug 17 05:54:15 PM PDT 24 Aug 17 05:54:16 PM PDT 24 120186455 ps
T622 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.517421395 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:50 PM PDT 24 1911921949 ps
T623 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.541052621 Aug 17 05:53:46 PM PDT 24 Aug 17 05:53:47 PM PDT 24 38750591 ps
T624 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2419133407 Aug 17 05:53:50 PM PDT 24 Aug 17 05:53:53 PM PDT 24 43779353 ps
T625 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3589443997 Aug 17 05:54:14 PM PDT 24 Aug 17 05:54:16 PM PDT 24 377493951 ps
T110 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3309841462 Aug 17 05:54:11 PM PDT 24 Aug 17 05:54:18 PM PDT 24 546150124 ps
T626 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2165384713 Aug 17 05:54:13 PM PDT 24 Aug 17 05:54:13 PM PDT 24 13171203 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2478090161 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:10 PM PDT 24 359315232 ps
T628 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1938895123 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:54 PM PDT 24 181993613 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.311974035 Aug 17 05:53:54 PM PDT 24 Aug 17 05:53:56 PM PDT 24 71240035 ps
T630 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1542420406 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:11 PM PDT 24 45407505 ps
T631 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1332970287 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:10 PM PDT 24 12973558 ps
T632 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1625670447 Aug 17 05:54:00 PM PDT 24 Aug 17 05:54:02 PM PDT 24 67781349 ps
T633 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4039272850 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:58 PM PDT 24 322057024 ps
T634 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2564297864 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:12 PM PDT 24 163503312 ps
T635 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2035847348 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:55 PM PDT 24 44229391 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4122586959 Aug 17 05:53:53 PM PDT 24 Aug 17 05:53:54 PM PDT 24 60326807 ps
T637 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3166405076 Aug 17 05:53:58 PM PDT 24 Aug 17 05:54:01 PM PDT 24 1205914813 ps
T638 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3527015449 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:12 PM PDT 24 208191007 ps
T639 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1383896955 Aug 17 05:53:58 PM PDT 24 Aug 17 05:54:00 PM PDT 24 92507623 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3147107963 Aug 17 05:53:55 PM PDT 24 Aug 17 05:54:01 PM PDT 24 111336316 ps
T641 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1943139271 Aug 17 05:53:47 PM PDT 24 Aug 17 05:53:52 PM PDT 24 207681187 ps
T642 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2537273827 Aug 17 05:53:50 PM PDT 24 Aug 17 05:53:51 PM PDT 24 20266166 ps
T643 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2213744156 Aug 17 05:53:48 PM PDT 24 Aug 17 05:53:49 PM PDT 24 66614677 ps
T644 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1222791547 Aug 17 05:54:11 PM PDT 24 Aug 17 05:54:12 PM PDT 24 934732415 ps
T645 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1759117691 Aug 17 05:54:08 PM PDT 24 Aug 17 05:54:10 PM PDT 24 34400989 ps
T646 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3256287377 Aug 17 05:53:51 PM PDT 24 Aug 17 05:53:55 PM PDT 24 104962134 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1041028105 Aug 17 05:54:00 PM PDT 24 Aug 17 06:07:18 PM PDT 24 85938074600 ps
T648 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4065236342 Aug 17 05:54:01 PM PDT 24 Aug 17 05:54:03 PM PDT 24 47691289 ps
T649 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2683981588 Aug 17 05:54:09 PM PDT 24 Aug 17 05:54:12 PM PDT 24 201944458 ps
T650 /workspace/coverage/cover_reg_top/15.hmac_intr_test.247264600 Aug 17 05:53:57 PM PDT 24 Aug 17 05:53:58 PM PDT 24 13581167 ps
T651 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3782283780 Aug 17 05:54:05 PM PDT 24 Aug 17 05:54:06 PM PDT 24 59842142 ps

Test location /workspace/coverage/default/16.hmac_stress_all.3586283503
Short name T5
Test name
Test status
Simulation time 48354234153 ps
CPU time 1525.37 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 06:20:17 PM PDT 24
Peak memory 748728 kb
Host smart-e72c78ee-7418-49f6-9744-d4d33a3bbc18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586283503 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3586283503
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all.3739659300
Short name T6
Test name
Test status
Simulation time 38991496793 ps
CPU time 1291.04 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 06:16:00 PM PDT 24
Peak memory 619312 kb
Host smart-b52e5ada-fac6-4b87-a17f-82bdbc1f24c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739659300 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.3739659300
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2651455109
Short name T9
Test name
Test status
Simulation time 7374639168 ps
CPU time 169.53 seconds
Started Aug 17 05:54:18 PM PDT 24
Finished Aug 17 05:57:08 PM PDT 24
Peak memory 627652 kb
Host smart-f4b09c87-3a7f-450e-b234-cb6db8d45836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651455109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2651455109
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.4273711389
Short name T127
Test name
Test status
Simulation time 285144436 ps
CPU time 4.34 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:53:53 PM PDT 24
Peak memory 200524 kb
Host smart-bb8156d3-5a0e-4b51-aa08-ce53a7e87b2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273711389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4273711389
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1056116618
Short name T10
Test name
Test status
Simulation time 14408925872 ps
CPU time 515.27 seconds
Started Aug 17 05:54:25 PM PDT 24
Finished Aug 17 06:03:01 PM PDT 24
Peak memory 666952 kb
Host smart-4e396737-04f0-4a81-915d-0725893ae845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1056116618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1056116618
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2723985115
Short name T55
Test name
Test status
Simulation time 1047712620 ps
CPU time 1 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:54:31 PM PDT 24
Peak memory 220096 kb
Host smart-7daf2f78-d6c7-4a59-bfea-d995e4689e3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723985115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2723985115
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/44.hmac_stress_all.655410040
Short name T14
Test name
Test status
Simulation time 58699502877 ps
CPU time 1506.97 seconds
Started Aug 17 05:55:37 PM PDT 24
Finished Aug 17 06:20:44 PM PDT 24
Peak memory 708676 kb
Host smart-85a33fcd-d659-4a83-885e-b551f6bf27ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655410040 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.655410040
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3378829055
Short name T99
Test name
Test status
Simulation time 42465405 ps
CPU time 0.81 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 199972 kb
Host smart-89f2ac8a-09e7-49a3-8cc5-74e3aca34749
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378829055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3378829055
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.475968426
Short name T21
Test name
Test status
Simulation time 1195414157 ps
CPU time 53.79 seconds
Started Aug 17 05:54:17 PM PDT 24
Finished Aug 17 05:55:11 PM PDT 24
Peak memory 200568 kb
Host smart-1c0d4638-50f6-479a-a5b7-cddbc2779d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475968426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.475968426
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1027035282
Short name T163
Test name
Test status
Simulation time 23673640 ps
CPU time 0.62 seconds
Started Aug 17 05:54:20 PM PDT 24
Finished Aug 17 05:54:20 PM PDT 24
Peak memory 197396 kb
Host smart-12c51fda-e9c0-4bc0-bf82-046548108af5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027035282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1027035282
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2104009591
Short name T126
Test name
Test status
Simulation time 536916486 ps
CPU time 4.73 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 200276 kb
Host smart-f4bb24e1-39a3-4303-8744-d9b405914e05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104009591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2104009591
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.753641186
Short name T142
Test name
Test status
Simulation time 629328344 ps
CPU time 31.42 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:26 PM PDT 24
Peak memory 200712 kb
Host smart-25f4d148-0475-4e71-bfad-36ec0c6866b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753641186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.753641186
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.325059967
Short name T108
Test name
Test status
Simulation time 47223408 ps
CPU time 0.94 seconds
Started Aug 17 05:54:07 PM PDT 24
Finished Aug 17 05:54:08 PM PDT 24
Peak memory 200096 kb
Host smart-2f377320-a3d0-4768-93cc-9dcee916fce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325059967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.325059967
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2250751742
Short name T130
Test name
Test status
Simulation time 338165723 ps
CPU time 1.91 seconds
Started Aug 17 05:53:47 PM PDT 24
Finished Aug 17 05:53:49 PM PDT 24
Peak memory 200244 kb
Host smart-1736e218-28ef-4d6d-bbd4-d37fd7da009b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250751742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2250751742
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1015698974
Short name T68
Test name
Test status
Simulation time 193400737 ps
CPU time 2.77 seconds
Started Aug 17 05:53:59 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 200324 kb
Host smart-4c3acfd7-eb5f-42bd-a312-8879c87cc317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015698974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1015698974
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_long_msg.397869827
Short name T65
Test name
Test status
Simulation time 36580733654 ps
CPU time 163.24 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:57:18 PM PDT 24
Peak memory 200688 kb
Host smart-46f3ba57-2955-4ad5-8b9c-cd34d495a430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397869827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.397869827
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1024751194
Short name T122
Test name
Test status
Simulation time 4470903684 ps
CPU time 348.37 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 06:00:23 PM PDT 24
Peak memory 607580 kb
Host smart-1db2bac6-bd3f-450c-9d93-c5a485ab94a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024751194 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1024751194
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.323476728
Short name T76
Test name
Test status
Simulation time 1288069449 ps
CPU time 16.75 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 200724 kb
Host smart-5a8bdf82-11b6-4a8c-b3d3-0382a260bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323476728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.323476728
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1670026865
Short name T11
Test name
Test status
Simulation time 42620733123 ps
CPU time 268.98 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:58:59 PM PDT 24
Peak memory 565756 kb
Host smart-d0433b99-bc6e-4e34-b618-1f6155474138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1670026865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1670026865
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1943139271
Short name T641
Test name
Test status
Simulation time 207681187 ps
CPU time 5.32 seconds
Started Aug 17 05:53:47 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 200236 kb
Host smart-ee46db7d-f53b-412c-a329-5f20c0665294
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943139271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1943139271
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.606440244
Short name T616
Test name
Test status
Simulation time 358397020 ps
CPU time 6.03 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200232 kb
Host smart-e29f2c4d-ed7c-41fd-a9dd-1eae324030b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606440244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.606440244
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.541052621
Short name T623
Test name
Test status
Simulation time 38750591 ps
CPU time 0.73 seconds
Started Aug 17 05:53:46 PM PDT 24
Finished Aug 17 05:53:47 PM PDT 24
Peak memory 198016 kb
Host smart-80d095f4-5de5-42fe-a03f-8104db1d6ac3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541052621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.541052621
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1252800114
Short name T567
Test name
Test status
Simulation time 252052913 ps
CPU time 2.75 seconds
Started Aug 17 05:53:44 PM PDT 24
Finished Aug 17 05:53:47 PM PDT 24
Peak memory 216708 kb
Host smart-69cad6f6-210c-4cbb-8476-ebad583dee54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252800114 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1252800114
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2210937038
Short name T609
Test name
Test status
Simulation time 17453954 ps
CPU time 0.7 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:49 PM PDT 24
Peak memory 198300 kb
Host smart-9703e472-b55a-4750-98a7-7931b60da4f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210937038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2210937038
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.83134935
Short name T569
Test name
Test status
Simulation time 36374356 ps
CPU time 0.58 seconds
Started Aug 17 05:53:47 PM PDT 24
Finished Aug 17 05:53:47 PM PDT 24
Peak memory 195180 kb
Host smart-07bb41b1-938f-4d77-8d22-dd2e56e039b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83134935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.83134935
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3861981390
Short name T113
Test name
Test status
Simulation time 410994198 ps
CPU time 2.13 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:53:51 PM PDT 24
Peak memory 200244 kb
Host smart-5e82707c-8d91-4fb7-b50c-489f43c2af87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861981390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3861981390
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1070613632
Short name T568
Test name
Test status
Simulation time 192246507 ps
CPU time 3.81 seconds
Started Aug 17 05:53:44 PM PDT 24
Finished Aug 17 05:53:48 PM PDT 24
Peak memory 200164 kb
Host smart-207ef38c-817d-4304-9297-834a04e2f1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070613632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1070613632
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.609519851
Short name T546
Test name
Test status
Simulation time 334144084 ps
CPU time 3.1 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200244 kb
Host smart-473ade0e-e857-4656-99cc-3e050e741653
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609519851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.609519851
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1148947893
Short name T591
Test name
Test status
Simulation time 1853094330 ps
CPU time 10.93 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:54:00 PM PDT 24
Peak memory 199416 kb
Host smart-c1eadfed-a130-4c5d-9ed8-184dd23e70f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148947893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1148947893
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1584419078
Short name T555
Test name
Test status
Simulation time 32654290 ps
CPU time 0.71 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 198324 kb
Host smart-e1114bb1-360b-4dd7-af26-958dc1edec90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584419078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1584419078
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2678829095
Short name T543
Test name
Test status
Simulation time 90144641 ps
CPU time 1.34 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:51 PM PDT 24
Peak memory 200332 kb
Host smart-04109172-8e89-42a7-b955-f331f9cd0058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678829095 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2678829095
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1841327223
Short name T618
Test name
Test status
Simulation time 24428215 ps
CPU time 0.81 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 199112 kb
Host smart-447f443a-643f-4269-aecc-391d6f42fe1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841327223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1841327223
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3016728034
Short name T580
Test name
Test status
Simulation time 45945888 ps
CPU time 0.59 seconds
Started Aug 17 05:53:46 PM PDT 24
Finished Aug 17 05:53:46 PM PDT 24
Peak memory 195216 kb
Host smart-c838a790-1a71-4d39-b6b5-ae038726f634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016728034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3016728034
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4122586959
Short name T636
Test name
Test status
Simulation time 60326807 ps
CPU time 1.13 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 198944 kb
Host smart-e5fcd857-6117-4bc1-bdec-521455474214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122586959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4122586959
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.517421395
Short name T622
Test name
Test status
Simulation time 1911921949 ps
CPU time 2.32 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 200236 kb
Host smart-1982b9ac-694c-4703-ac5f-7662a31c3cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517421395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.517421395
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2855024521
Short name T610
Test name
Test status
Simulation time 715255355 ps
CPU time 3.88 seconds
Started Aug 17 05:53:44 PM PDT 24
Finished Aug 17 05:53:47 PM PDT 24
Peak memory 200280 kb
Host smart-bbd58a73-99c9-4f5a-9959-9975c5caa70c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855024521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2855024521
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.311974035
Short name T629
Test name
Test status
Simulation time 71240035 ps
CPU time 1.22 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200056 kb
Host smart-ada00290-72c3-45fd-871e-f02d5a03efd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311974035 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.311974035
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3330582266
Short name T112
Test name
Test status
Simulation time 30712426 ps
CPU time 0.69 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 198620 kb
Host smart-012bc704-5256-4b55-b937-2f5fb2913d78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330582266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3330582266
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2761405882
Short name T550
Test name
Test status
Simulation time 48840999 ps
CPU time 0.59 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 195284 kb
Host smart-03200d26-a92a-44ce-b430-96796acdb283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761405882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2761405882
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2035847348
Short name T635
Test name
Test status
Simulation time 44229391 ps
CPU time 2.3 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200260 kb
Host smart-a87bdb92-7ff5-46d5-b2dd-d0a351551225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035847348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2035847348
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1889296181
Short name T592
Test name
Test status
Simulation time 25737513 ps
CPU time 1.22 seconds
Started Aug 17 05:53:55 PM PDT 24
Finished Aug 17 05:53:57 PM PDT 24
Peak memory 200252 kb
Host smart-9132c816-37bf-4c5f-9476-4ae5e92c8691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889296181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1889296181
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2432582480
Short name T136
Test name
Test status
Simulation time 424040160 ps
CPU time 1.97 seconds
Started Aug 17 05:54:00 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 200272 kb
Host smart-f8aa6c2c-a75e-4d5f-8c41-4c71ed671837
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432582480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2432582480
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.4065236342
Short name T648
Test name
Test status
Simulation time 47691289 ps
CPU time 1.77 seconds
Started Aug 17 05:54:01 PM PDT 24
Finished Aug 17 05:54:03 PM PDT 24
Peak memory 200264 kb
Host smart-1d560b14-288e-4639-b1b4-b39999fc1eae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065236342 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.4065236342
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.436308382
Short name T540
Test name
Test status
Simulation time 19574105 ps
CPU time 0.74 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 197940 kb
Host smart-253b453c-2e62-4de3-96c5-d2103e9c1422
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436308382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.436308382
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.961392055
Short name T614
Test name
Test status
Simulation time 55477805 ps
CPU time 0.6 seconds
Started Aug 17 05:54:03 PM PDT 24
Finished Aug 17 05:54:04 PM PDT 24
Peak memory 195292 kb
Host smart-02321459-e7d1-420d-b8ca-7bf168bb42db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961392055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.961392055
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2711510261
Short name T603
Test name
Test status
Simulation time 36184970 ps
CPU time 1.68 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 200220 kb
Host smart-b1f913d0-7092-41f0-bb0a-c588ea91a824
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711510261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2711510261
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3124339074
Short name T71
Test name
Test status
Simulation time 86991832 ps
CPU time 1.37 seconds
Started Aug 17 05:53:52 PM PDT 24
Finished Aug 17 05:53:53 PM PDT 24
Peak memory 200244 kb
Host smart-2ad80701-227a-4735-af45-9371da56a857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124339074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3124339074
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3639821904
Short name T132
Test name
Test status
Simulation time 86033754 ps
CPU time 2.88 seconds
Started Aug 17 05:53:52 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200288 kb
Host smart-8ef527be-7578-4db4-8119-aa2d078b376c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639821904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3639821904
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.208116154
Short name T556
Test name
Test status
Simulation time 376866555 ps
CPU time 2.24 seconds
Started Aug 17 05:54:03 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 199912 kb
Host smart-f5e4677e-c267-4c67-8fdb-eb3dae9aa97b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208116154 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.208116154
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1402798431
Short name T575
Test name
Test status
Simulation time 23708535 ps
CPU time 0.57 seconds
Started Aug 17 05:54:00 PM PDT 24
Finished Aug 17 05:54:00 PM PDT 24
Peak memory 195232 kb
Host smart-89339b37-b7f9-4ff0-ae5b-cf5574fd3a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402798431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1402798431
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2993180477
Short name T116
Test name
Test status
Simulation time 85886286 ps
CPU time 1.8 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200260 kb
Host smart-259accc4-92d0-46f0-ae5f-7c3ca5330116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993180477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2993180477
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3527015449
Short name T638
Test name
Test status
Simulation time 208191007 ps
CPU time 2.96 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200252 kb
Host smart-3dfe7fc7-78ed-4a50-9bc1-1f547362f81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527015449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3527015449
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3589443997
Short name T625
Test name
Test status
Simulation time 377493951 ps
CPU time 2.6 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 200392 kb
Host smart-3c664a5d-0368-4836-97dd-3b16d5981a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589443997 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3589443997
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3363723900
Short name T578
Test name
Test status
Simulation time 13708609 ps
CPU time 0.57 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:53:57 PM PDT 24
Peak memory 195256 kb
Host smart-d489453f-2cf7-4c62-87cb-f04ddd4a0e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363723900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3363723900
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1081797198
Short name T565
Test name
Test status
Simulation time 278405516 ps
CPU time 1.7 seconds
Started Aug 17 05:54:10 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200312 kb
Host smart-0796abd4-7010-4c44-a1ac-f086d414d78a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081797198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1081797198
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2683981588
Short name T649
Test name
Test status
Simulation time 201944458 ps
CPU time 2.73 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200248 kb
Host smart-efdc5cc9-4f05-41c8-bb38-479036e35e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683981588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2683981588
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3433775052
Short name T125
Test name
Test status
Simulation time 543873848 ps
CPU time 4.39 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 200348 kb
Host smart-26bbac6f-51fe-4968-906d-28cb3d551bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433775052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3433775052
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.575659945
Short name T562
Test name
Test status
Simulation time 103755704 ps
CPU time 2.31 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:07 PM PDT 24
Peak memory 208448 kb
Host smart-54a1c807-bfd0-44b0-a676-c9d1449b0c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575659945 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.575659945
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1728512331
Short name T103
Test name
Test status
Simulation time 12554561 ps
CPU time 0.7 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:14 PM PDT 24
Peak memory 198076 kb
Host smart-a4f198c2-3686-4c71-a1f1-4d43ff057752
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728512331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1728512331
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1840826426
Short name T573
Test name
Test status
Simulation time 59258652 ps
CPU time 0.6 seconds
Started Aug 17 05:54:00 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 195228 kb
Host smart-717de106-692f-49f5-af6d-4d7c02673ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840826426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1840826426
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1542420406
Short name T630
Test name
Test status
Simulation time 45407505 ps
CPU time 2.06 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:11 PM PDT 24
Peak memory 200276 kb
Host smart-1d67e83c-ba5c-433d-8139-b424c7e4bae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542420406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1542420406
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2564297864
Short name T634
Test name
Test status
Simulation time 163503312 ps
CPU time 3.09 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200248 kb
Host smart-3381e978-4a77-451e-9326-349c30a4da53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564297864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2564297864
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2775550969
Short name T542
Test name
Test status
Simulation time 42591630633 ps
CPU time 414.63 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 06:00:59 PM PDT 24
Peak memory 216812 kb
Host smart-22a2e210-06bd-4937-9b63-a8c1428e9a50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775550969 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2775550969
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2658989155
Short name T111
Test name
Test status
Simulation time 26406967 ps
CPU time 0.87 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200004 kb
Host smart-081bc960-6300-4b50-9473-04f9f170e608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658989155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2658989155
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.247264600
Short name T650
Test name
Test status
Simulation time 13581167 ps
CPU time 0.61 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 195140 kb
Host smart-f5b86fc7-4fd6-42b8-b000-bf41b3578e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247264600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.247264600
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3583247232
Short name T581
Test name
Test status
Simulation time 48425970 ps
CPU time 1.2 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 200196 kb
Host smart-4120eace-6a36-4f81-ac7e-49013c07e172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583247232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3583247232
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3166405076
Short name T637
Test name
Test status
Simulation time 1205914813 ps
CPU time 3.55 seconds
Started Aug 17 05:53:58 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 199256 kb
Host smart-30143759-e5c2-402c-a79f-8d7c65a0b220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166405076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3166405076
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.899607365
Short name T135
Test name
Test status
Simulation time 646261349 ps
CPU time 3.22 seconds
Started Aug 17 05:53:59 PM PDT 24
Finished Aug 17 05:54:03 PM PDT 24
Peak memory 200152 kb
Host smart-337b0a77-c593-4db3-96ef-a791222a9f96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899607365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.899607365
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3464752218
Short name T576
Test name
Test status
Simulation time 32928219 ps
CPU time 2.08 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200308 kb
Host smart-694927d2-cc2f-49df-ac97-98ac15a7db86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464752218 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3464752218
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2295936247
Short name T599
Test name
Test status
Simulation time 17073785 ps
CPU time 0.89 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200092 kb
Host smart-b53c333f-15f8-4407-af03-006a69a039d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295936247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2295936247
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1717809142
Short name T613
Test name
Test status
Simulation time 31101923 ps
CPU time 0.58 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 195276 kb
Host smart-fc7e585b-1ab3-450c-91f0-f4f40abc16af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717809142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1717809142
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1040330538
Short name T611
Test name
Test status
Simulation time 42674688 ps
CPU time 1.11 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 199004 kb
Host smart-2700b5db-e1cf-4896-b121-cb36ad409ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040330538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1040330538
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1614704440
Short name T90
Test name
Test status
Simulation time 42645693 ps
CPU time 2.44 seconds
Started Aug 17 05:54:02 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 200264 kb
Host smart-a7f227c0-4a56-4552-94e5-a97107a2a5d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614704440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1614704440
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3507002145
Short name T134
Test name
Test status
Simulation time 287054641 ps
CPU time 1.78 seconds
Started Aug 17 05:54:02 PM PDT 24
Finished Aug 17 05:54:04 PM PDT 24
Peak memory 200300 kb
Host smart-39ed2a32-6ff7-433e-86c3-89884822a43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507002145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3507002145
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1383896955
Short name T639
Test name
Test status
Simulation time 92507623 ps
CPU time 2.21 seconds
Started Aug 17 05:53:58 PM PDT 24
Finished Aug 17 05:54:00 PM PDT 24
Peak memory 200268 kb
Host smart-ec25b06e-2ad9-4f8e-8a0a-8c60d41eea4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383896955 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1383896955
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1480554488
Short name T109
Test name
Test status
Simulation time 18730889 ps
CPU time 0.98 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 200072 kb
Host smart-6eea6745-1a99-4c27-8d3a-21025aa66b2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480554488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1480554488
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.79221813
Short name T548
Test name
Test status
Simulation time 16897480 ps
CPU time 0.66 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 05:54:09 PM PDT 24
Peak memory 195188 kb
Host smart-adee01c6-8c88-4b77-a2ff-f142a4dbd3e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79221813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.79221813
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2780925129
Short name T607
Test name
Test status
Simulation time 92136777 ps
CPU time 1.65 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 200192 kb
Host smart-321eb868-4563-46d8-833a-7821a6fb15ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780925129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2780925129
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2498561558
Short name T553
Test name
Test status
Simulation time 26203455 ps
CPU time 1.37 seconds
Started Aug 17 05:54:03 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 199848 kb
Host smart-f9be591c-5c2e-4525-9d08-8065f3f1e458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498561558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2498561558
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.875441073
Short name T69
Test name
Test status
Simulation time 244545850 ps
CPU time 1.97 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 200248 kb
Host smart-0238d15b-0a58-46e1-8330-ef0bd998fcff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875441073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.875441073
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1417551678
Short name T72
Test name
Test status
Simulation time 47811255 ps
CPU time 1.41 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 200196 kb
Host smart-200ca26b-dc64-467e-a0cf-ccfce8e5b4c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417551678 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1417551678
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2815284441
Short name T107
Test name
Test status
Simulation time 17770305 ps
CPU time 0.82 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:53:57 PM PDT 24
Peak memory 199360 kb
Host smart-d31376ef-7983-495a-bc31-e9af75f2d016
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815284441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2815284441
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2265290553
Short name T552
Test name
Test status
Simulation time 43974711 ps
CPU time 0.69 seconds
Started Aug 17 05:54:03 PM PDT 24
Finished Aug 17 05:54:03 PM PDT 24
Peak memory 195344 kb
Host smart-fff98f66-b960-4eda-9ae3-d57467e410dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265290553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2265290553
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.757058544
Short name T588
Test name
Test status
Simulation time 43582080 ps
CPU time 1.12 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 200188 kb
Host smart-b754969f-d54e-4464-8bb0-d73d04ddeec1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757058544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.757058544
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3549910552
Short name T584
Test name
Test status
Simulation time 276470928 ps
CPU time 2.99 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:08 PM PDT 24
Peak memory 200200 kb
Host smart-1bfabd23-359d-4d23-a341-f19c640f3d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549910552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3549910552
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.97365868
Short name T129
Test name
Test status
Simulation time 459563178 ps
CPU time 3.92 seconds
Started Aug 17 05:53:58 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 199252 kb
Host smart-94b53690-a14f-43be-8596-cb90aab4a286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97365868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.97365868
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.135153460
Short name T595
Test name
Test status
Simulation time 83334682 ps
CPU time 1.7 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200268 kb
Host smart-35beb00d-8ae3-476f-97e0-03a228cdf4ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135153460 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.135153460
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1881732151
Short name T106
Test name
Test status
Simulation time 81094702 ps
CPU time 0.8 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:53:57 PM PDT 24
Peak memory 200088 kb
Host smart-c703de1c-274f-426b-8a0c-c74e331bbca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881732151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1881732151
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3109565490
Short name T619
Test name
Test status
Simulation time 15418466 ps
CPU time 0.67 seconds
Started Aug 17 05:54:04 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 195304 kb
Host smart-76d0f7e0-c2a1-4e54-a543-c54d1ae98413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109565490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3109565490
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1759117691
Short name T645
Test name
Test status
Simulation time 34400989 ps
CPU time 1.11 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200072 kb
Host smart-53ce446c-037e-4873-a31c-d3a0376f06d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759117691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1759117691
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3152058939
Short name T571
Test name
Test status
Simulation time 79369078 ps
CPU time 2.49 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:08 PM PDT 24
Peak memory 200224 kb
Host smart-2e86f37c-1b80-40fa-8e2b-9915ac4d651a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152058939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3152058939
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1522012613
Short name T128
Test name
Test status
Simulation time 504949449 ps
CPU time 4.11 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:17 PM PDT 24
Peak memory 200276 kb
Host smart-62b65728-e0d7-49bd-879a-e91e9b4ace30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522012613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1522012613
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.98070852
Short name T590
Test name
Test status
Simulation time 169474910 ps
CPU time 3.11 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:53:59 PM PDT 24
Peak memory 200064 kb
Host smart-8c813453-ed76-4f6d-bed8-4737337146e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98070852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.98070852
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4144281569
Short name T585
Test name
Test status
Simulation time 334035064 ps
CPU time 9.74 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 200304 kb
Host smart-375a3baf-e471-4413-acb5-3d2dbd2beea6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144281569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4144281569
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2213744156
Short name T643
Test name
Test status
Simulation time 66614677 ps
CPU time 1.06 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:49 PM PDT 24
Peak memory 200040 kb
Host smart-47507b57-fa3c-4f71-8454-b9040f459cd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213744156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2213744156
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1625670447
Short name T632
Test name
Test status
Simulation time 67781349 ps
CPU time 2.12 seconds
Started Aug 17 05:54:00 PM PDT 24
Finished Aug 17 05:54:02 PM PDT 24
Peak memory 200316 kb
Host smart-f98b79fd-e01f-4bc4-9a2f-dd94f1e796d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625670447 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1625670447
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2564363062
Short name T102
Test name
Test status
Simulation time 24975023 ps
CPU time 0.85 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 199792 kb
Host smart-fc7e3a0b-94b4-4f09-900c-47fadca26cd3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564363062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2564363062
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2537273827
Short name T642
Test name
Test status
Simulation time 20266166 ps
CPU time 0.64 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:51 PM PDT 24
Peak memory 195240 kb
Host smart-a2d2c548-4893-449e-865d-08f18df26366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537273827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2537273827
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1362314938
Short name T89
Test name
Test status
Simulation time 109170741 ps
CPU time 1.8 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200272 kb
Host smart-3500f1f0-5743-4192-9845-939a52a08740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362314938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1362314938
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2419133407
Short name T624
Test name
Test status
Simulation time 43779353 ps
CPU time 2.52 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:53 PM PDT 24
Peak memory 200236 kb
Host smart-6525518f-9497-4e24-acfc-ae542a84cc6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419133407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2419133407
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3123071806
Short name T67
Test name
Test status
Simulation time 619945068 ps
CPU time 3.26 seconds
Started Aug 17 05:54:01 PM PDT 24
Finished Aug 17 05:54:04 PM PDT 24
Peak memory 200276 kb
Host smart-2b7b1fb0-af6f-466d-9a76-feb1b26043b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123071806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3123071806
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3317676205
Short name T602
Test name
Test status
Simulation time 53436004 ps
CPU time 0.63 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:14 PM PDT 24
Peak memory 195272 kb
Host smart-c087a307-fda5-46f1-9bd6-c5e2c4da996f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317676205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3317676205
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1489745160
Short name T88
Test name
Test status
Simulation time 40841818 ps
CPU time 0.6 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 195232 kb
Host smart-e14cd96b-dd14-4054-8b32-6b46c5d0b851
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489745160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1489745160
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3067540708
Short name T554
Test name
Test status
Simulation time 14500256 ps
CPU time 0.62 seconds
Started Aug 17 05:54:06 PM PDT 24
Finished Aug 17 05:54:07 PM PDT 24
Peak memory 195156 kb
Host smart-0c42b192-35f1-4a16-8134-3991dbecb7c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067540708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3067540708
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4212275857
Short name T574
Test name
Test status
Simulation time 23290565 ps
CPU time 0.65 seconds
Started Aug 17 05:54:07 PM PDT 24
Finished Aug 17 05:54:07 PM PDT 24
Peak memory 195316 kb
Host smart-832bc37d-eb69-4ead-a5d2-fe739b03afca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212275857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4212275857
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3837381789
Short name T620
Test name
Test status
Simulation time 12015446 ps
CPU time 0.59 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 195252 kb
Host smart-93fc4bd4-14d7-43c6-be12-bde482d1b17c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837381789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3837381789
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1049060688
Short name T560
Test name
Test status
Simulation time 15631522 ps
CPU time 0.63 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:15 PM PDT 24
Peak memory 195172 kb
Host smart-a0a10abb-7ca5-4f0f-8be0-4e6b5ab1485c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049060688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1049060688
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.4026296381
Short name T586
Test name
Test status
Simulation time 13360576 ps
CPU time 0.61 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:15 PM PDT 24
Peak memory 195356 kb
Host smart-fc1197aa-6b78-4b77-a36d-462048557dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026296381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.4026296381
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1752714482
Short name T557
Test name
Test status
Simulation time 59646624 ps
CPU time 0.63 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 195356 kb
Host smart-3da91487-0cbb-4f13-8c4c-f1becaba599f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752714482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1752714482
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1480987229
Short name T577
Test name
Test status
Simulation time 113846915 ps
CPU time 0.61 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 195204 kb
Host smart-f8397b07-69b8-4982-985b-38daef4388dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480987229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1480987229
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2927664269
Short name T547
Test name
Test status
Simulation time 55718892 ps
CPU time 0.59 seconds
Started Aug 17 05:54:18 PM PDT 24
Finished Aug 17 05:54:18 PM PDT 24
Peak memory 195224 kb
Host smart-479fb7ae-ef39-4f20-82e7-8d308529126e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927664269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2927664269
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2721641379
Short name T101
Test name
Test status
Simulation time 221705153 ps
CPU time 8.2 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:17 PM PDT 24
Peak memory 200280 kb
Host smart-b550c434-83f9-41db-97e4-c1ff68dc12c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721641379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2721641379
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3309841462
Short name T110
Test name
Test status
Simulation time 546150124 ps
CPU time 6.36 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:18 PM PDT 24
Peak memory 200268 kb
Host smart-e69dbdf0-3768-407f-8c85-d0ee07c9a737
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309841462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3309841462
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1375473022
Short name T598
Test name
Test status
Simulation time 41845004 ps
CPU time 0.98 seconds
Started Aug 17 05:53:57 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 200000 kb
Host smart-09b77812-71d6-4f74-bba4-b4985704b622
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375473022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1375473022
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3689834082
Short name T570
Test name
Test status
Simulation time 22950765 ps
CPU time 1.47 seconds
Started Aug 17 05:54:03 PM PDT 24
Finished Aug 17 05:54:04 PM PDT 24
Peak memory 200248 kb
Host smart-7dad7ab3-7819-4a08-89a6-45682cf37eb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689834082 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3689834082
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3211852076
Short name T566
Test name
Test status
Simulation time 18009845 ps
CPU time 0.74 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:49 PM PDT 24
Peak memory 198232 kb
Host smart-717521f1-6dca-48fa-b6ac-ad44346c457a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211852076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3211852076
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1644660773
Short name T545
Test name
Test status
Simulation time 23123210 ps
CPU time 0.62 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 195276 kb
Host smart-f06e4647-836a-4d25-a3fd-1779efd7d3f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644660773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1644660773
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1412938612
Short name T118
Test name
Test status
Simulation time 187666136 ps
CPU time 1.76 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:53:51 PM PDT 24
Peak memory 200272 kb
Host smart-0516a5a0-498b-4d8f-b925-d700237752f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412938612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1412938612
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2506470961
Short name T617
Test name
Test status
Simulation time 42420916 ps
CPU time 2.16 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200236 kb
Host smart-2fbd42db-b35c-4069-90df-c865b37b3555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506470961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2506470961
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2478090161
Short name T627
Test name
Test status
Simulation time 359315232 ps
CPU time 1.76 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200276 kb
Host smart-34e51aba-c08d-416b-92c6-646e17e2274f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478090161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2478090161
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.168900406
Short name T558
Test name
Test status
Simulation time 36270456 ps
CPU time 0.6 seconds
Started Aug 17 05:54:12 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 195236 kb
Host smart-7df32fd2-5c9f-4055-9f8d-ac8fc9026ae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168900406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.168900406
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3782283780
Short name T651
Test name
Test status
Simulation time 59842142 ps
CPU time 0.59 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 195268 kb
Host smart-21f9f150-d7ee-4a3c-842b-9dca8a70acb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782283780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3782283780
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.388620663
Short name T537
Test name
Test status
Simulation time 71997534 ps
CPU time 0.56 seconds
Started Aug 17 05:54:12 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 195316 kb
Host smart-5dfdc012-f5d5-442a-86ac-9dce1dd4f800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388620663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.388620663
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2292884082
Short name T559
Test name
Test status
Simulation time 33217120 ps
CPU time 0.61 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:15 PM PDT 24
Peak memory 195352 kb
Host smart-751759eb-9a2e-4cdc-bf8c-4a31f9f0d5cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292884082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2292884082
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3297126341
Short name T604
Test name
Test status
Simulation time 76087660 ps
CPU time 0.65 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:13 PM PDT 24
Peak memory 195284 kb
Host smart-a6465b22-71df-422b-86e7-b1f26c056641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297126341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3297126341
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2578168707
Short name T587
Test name
Test status
Simulation time 45924873 ps
CPU time 0.61 seconds
Started Aug 17 05:54:17 PM PDT 24
Finished Aug 17 05:54:18 PM PDT 24
Peak memory 195200 kb
Host smart-929a7066-1347-432e-8a11-16397a04ce05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578168707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2578168707
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3782222022
Short name T589
Test name
Test status
Simulation time 130579305 ps
CPU time 0.63 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:14 PM PDT 24
Peak memory 195296 kb
Host smart-48369058-eb72-432b-a9d2-e301b25f00bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782222022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3782222022
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2165384713
Short name T626
Test name
Test status
Simulation time 13171203 ps
CPU time 0.57 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:13 PM PDT 24
Peak memory 195296 kb
Host smart-36c6a3b4-7f23-468e-a867-c61af26b76a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165384713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2165384713
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1332970287
Short name T631
Test name
Test status
Simulation time 12973558 ps
CPU time 0.59 seconds
Started Aug 17 05:54:09 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 195208 kb
Host smart-44c5f886-7f88-4647-8457-d964a835abf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332970287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1332970287
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3844355374
Short name T549
Test name
Test status
Simulation time 24264068 ps
CPU time 0.62 seconds
Started Aug 17 05:54:06 PM PDT 24
Finished Aug 17 05:54:07 PM PDT 24
Peak memory 195380 kb
Host smart-b3c610a7-e66e-43c1-8a0f-dacc05d4027b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844355374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3844355374
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2993496236
Short name T98
Test name
Test status
Simulation time 307740458 ps
CPU time 5.78 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:57 PM PDT 24
Peak memory 200180 kb
Host smart-2cacb9e9-3d51-426c-91b1-3e11161bc327
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993496236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2993496236
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3147107963
Short name T640
Test name
Test status
Simulation time 111336316 ps
CPU time 5.26 seconds
Started Aug 17 05:53:55 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 199568 kb
Host smart-2881b8e2-346c-447e-a212-0f2a99487fc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147107963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3147107963
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2578522957
Short name T541
Test name
Test status
Simulation time 22525451 ps
CPU time 0.73 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 198044 kb
Host smart-fedfcf22-0c67-48e4-913d-50eeedc1f6cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578522957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2578522957
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.4183662547
Short name T579
Test name
Test status
Simulation time 74714455 ps
CPU time 1.93 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200320 kb
Host smart-c42d2098-525f-4327-bfe9-a1330fa921a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183662547 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.4183662547
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.13335738
Short name T97
Test name
Test status
Simulation time 29422495 ps
CPU time 0.99 seconds
Started Aug 17 05:53:55 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 199832 kb
Host smart-84f49793-2e1a-4272-969c-0d620f359a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.13335738
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2408912518
Short name T538
Test name
Test status
Simulation time 63830457 ps
CPU time 0.62 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 195272 kb
Host smart-d3d299a4-005a-41c1-8606-5f2c7fec9ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408912518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2408912518
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1373894999
Short name T608
Test name
Test status
Simulation time 273485371 ps
CPU time 2.17 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 200328 kb
Host smart-9585da5d-d967-45a7-8442-879ad6d4b53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373894999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1373894999
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.833077741
Short name T606
Test name
Test status
Simulation time 203255938 ps
CPU time 2.73 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200236 kb
Host smart-8a7154fa-db8a-4173-ae4f-7fa8e9056d0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833077741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.833077741
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.628177863
Short name T534
Test name
Test status
Simulation time 14935309 ps
CPU time 0.61 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:15 PM PDT 24
Peak memory 195264 kb
Host smart-62fc85de-aac0-4a9e-b9f3-6f82a55e9dc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628177863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.628177863
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2052318790
Short name T621
Test name
Test status
Simulation time 120186455 ps
CPU time 0.61 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 195332 kb
Host smart-dbf975dc-ce37-4949-b7c1-5d1a7d1991e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052318790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2052318790
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2755290358
Short name T600
Test name
Test status
Simulation time 15475293 ps
CPU time 0.61 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 05:54:08 PM PDT 24
Peak memory 195128 kb
Host smart-b0c09f8a-f944-472b-b1a6-ef8a5c9f836f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755290358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2755290358
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3804562761
Short name T536
Test name
Test status
Simulation time 14842266 ps
CPU time 0.57 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:11 PM PDT 24
Peak memory 195216 kb
Host smart-e7bb51f5-8b5a-472a-a34f-53e841868837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804562761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3804562761
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2559858838
Short name T594
Test name
Test status
Simulation time 16260250 ps
CPU time 0.61 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:14 PM PDT 24
Peak memory 195248 kb
Host smart-f95bea06-de41-4f7d-997d-598251c1e7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559858838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2559858838
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2874106370
Short name T597
Test name
Test status
Simulation time 67446456 ps
CPU time 0.59 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:06 PM PDT 24
Peak memory 195164 kb
Host smart-adf47edc-08af-4d10-b8da-88260390dbee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874106370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2874106370
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.4209330478
Short name T583
Test name
Test status
Simulation time 53153560 ps
CPU time 0.58 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 195236 kb
Host smart-0602d0f1-4ab2-415c-a1eb-cf71aff1d42b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209330478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.4209330478
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1461870751
Short name T561
Test name
Test status
Simulation time 11839420 ps
CPU time 0.63 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:54:05 PM PDT 24
Peak memory 195284 kb
Host smart-e50658e2-9cad-4fed-a931-544b0f31f798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461870751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1461870751
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.659148190
Short name T539
Test name
Test status
Simulation time 41430074 ps
CPU time 0.59 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:13 PM PDT 24
Peak memory 195284 kb
Host smart-093a2829-e0ec-4d5f-b7dd-067961566758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659148190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.659148190
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1032856963
Short name T87
Test name
Test status
Simulation time 12954448 ps
CPU time 0.61 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:15 PM PDT 24
Peak memory 195164 kb
Host smart-af028ecc-34c1-49de-89c5-1077921413ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032856963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1032856963
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4207785409
Short name T572
Test name
Test status
Simulation time 152370981 ps
CPU time 2.62 seconds
Started Aug 17 05:54:01 PM PDT 24
Finished Aug 17 05:54:04 PM PDT 24
Peak memory 200336 kb
Host smart-945c6de7-591a-4c22-8de5-494cb65044d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207785409 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4207785409
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2457456504
Short name T115
Test name
Test status
Simulation time 26295291 ps
CPU time 0.81 seconds
Started Aug 17 05:54:10 PM PDT 24
Finished Aug 17 05:54:11 PM PDT 24
Peak memory 200084 kb
Host smart-c22e57f3-8db7-46f7-9952-ba6ea799efd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457456504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2457456504
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.275458788
Short name T544
Test name
Test status
Simulation time 56672593 ps
CPU time 0.55 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 195220 kb
Host smart-c4a95826-6ff1-463c-b2ec-aa518e1aa0d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275458788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.275458788
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3874480737
Short name T601
Test name
Test status
Simulation time 164602852 ps
CPU time 1.12 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 198696 kb
Host smart-03205362-2252-416c-9d4b-40b26fb5dab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874480737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3874480737
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.3256287377
Short name T646
Test name
Test status
Simulation time 104962134 ps
CPU time 2.8 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200224 kb
Host smart-3690e45c-b07f-4add-a788-57ebb8dbd232
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256287377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3256287377
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2188098408
Short name T133
Test name
Test status
Simulation time 90272087 ps
CPU time 1.86 seconds
Started Aug 17 05:53:48 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 200288 kb
Host smart-b23fddc2-01b5-43c0-a66e-ec429e13d21b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188098408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2188098408
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1938895123
Short name T628
Test name
Test status
Simulation time 181993613 ps
CPU time 2.73 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200232 kb
Host smart-a45a93ae-d8a2-452c-ad00-cc4ca845d789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938895123 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1938895123
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2695734034
Short name T114
Test name
Test status
Simulation time 112648232 ps
CPU time 0.72 seconds
Started Aug 17 05:53:49 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 198104 kb
Host smart-86ac5ffe-871a-4482-927a-02f455bbaa10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695734034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2695734034
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2574302180
Short name T615
Test name
Test status
Simulation time 16775221 ps
CPU time 0.61 seconds
Started Aug 17 05:54:01 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 195356 kb
Host smart-6c7c7188-4cee-4c57-be28-30932626f7ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574302180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2574302180
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2397021268
Short name T596
Test name
Test status
Simulation time 183302853 ps
CPU time 2.22 seconds
Started Aug 17 05:54:07 PM PDT 24
Finished Aug 17 05:54:10 PM PDT 24
Peak memory 200264 kb
Host smart-c51a7ff3-2a13-4dac-9025-c50203f58c9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397021268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2397021268
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.4290703184
Short name T582
Test name
Test status
Simulation time 248500022 ps
CPU time 4.48 seconds
Started Aug 17 05:53:56 PM PDT 24
Finished Aug 17 05:54:00 PM PDT 24
Peak memory 200256 kb
Host smart-26135cd4-b9d9-4fcf-b594-48c2a354913e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290703184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.4290703184
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.126376372
Short name T593
Test name
Test status
Simulation time 382186238 ps
CPU time 1.99 seconds
Started Aug 17 05:53:59 PM PDT 24
Finished Aug 17 05:54:01 PM PDT 24
Peak memory 200332 kb
Host smart-82a5222c-51a8-41be-a224-1a7e649a0489
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126376372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.126376372
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1166608070
Short name T612
Test name
Test status
Simulation time 71403672 ps
CPU time 2.02 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200372 kb
Host smart-50c792ea-7008-4f9a-8ab8-3e6ac0af511d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166608070 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1166608070
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1055963054
Short name T100
Test name
Test status
Simulation time 31213189 ps
CPU time 1 seconds
Started Aug 17 05:53:55 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200084 kb
Host smart-0ea5e7bf-da30-47c6-a132-da429f3b6f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055963054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1055963054
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4145874774
Short name T551
Test name
Test status
Simulation time 19017426 ps
CPU time 0.6 seconds
Started Aug 17 05:53:58 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 195212 kb
Host smart-cf8f3154-1d43-4ce1-97a6-344231ecdb20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145874774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4145874774
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3904872181
Short name T117
Test name
Test status
Simulation time 162503682 ps
CPU time 1.13 seconds
Started Aug 17 05:54:02 PM PDT 24
Finished Aug 17 05:54:03 PM PDT 24
Peak memory 200096 kb
Host smart-38114948-89ed-4805-b140-16baa2c34519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904872181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3904872181
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2816145200
Short name T73
Test name
Test status
Simulation time 98786464 ps
CPU time 2.08 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 200236 kb
Host smart-d4bec25a-1ba8-4c14-b4a9-ba56635f1104
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816145200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2816145200
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1427971678
Short name T131
Test name
Test status
Simulation time 95995867 ps
CPU time 1.93 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200244 kb
Host smart-16d3e76e-df02-4080-9da4-fad08b782951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427971678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1427971678
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3695097823
Short name T605
Test name
Test status
Simulation time 73700372 ps
CPU time 1.82 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 200284 kb
Host smart-7888482f-7179-44d1-929a-2bc48b0012d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695097823 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3695097823
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.4068419800
Short name T105
Test name
Test status
Simulation time 52840493 ps
CPU time 0.9 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200036 kb
Host smart-80fe0169-c2a1-4334-a34c-c76b854fe9d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068419800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.4068419800
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3609183796
Short name T563
Test name
Test status
Simulation time 30145634 ps
CPU time 0.6 seconds
Started Aug 17 05:53:54 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 195268 kb
Host smart-2c034792-d3c8-4810-b358-13de5c9f242f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609183796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3609183796
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.981850668
Short name T564
Test name
Test status
Simulation time 127955098 ps
CPU time 1.59 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:53 PM PDT 24
Peak memory 200248 kb
Host smart-57bbfb5a-9122-4e54-bd67-5bc4a55e8e9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981850668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_
outstanding.981850668
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2252899150
Short name T74
Test name
Test status
Simulation time 72411855 ps
CPU time 3.62 seconds
Started Aug 17 05:53:50 PM PDT 24
Finished Aug 17 05:53:54 PM PDT 24
Peak memory 200260 kb
Host smart-7cff84de-5c8a-4b9b-a3c8-e1637374df69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252899150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2252899150
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4039272850
Short name T633
Test name
Test status
Simulation time 322057024 ps
CPU time 4.81 seconds
Started Aug 17 05:53:53 PM PDT 24
Finished Aug 17 05:53:58 PM PDT 24
Peak memory 200260 kb
Host smart-b1ffe32d-7c54-482f-b7c4-fb82c7da8442
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039272850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4039272850
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1041028105
Short name T647
Test name
Test status
Simulation time 85938074600 ps
CPU time 797.36 seconds
Started Aug 17 05:54:00 PM PDT 24
Finished Aug 17 06:07:18 PM PDT 24
Peak memory 216748 kb
Host smart-ac188196-9c47-4761-9fda-e8365723da95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041028105 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1041028105
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1165620384
Short name T104
Test name
Test status
Simulation time 20666892 ps
CPU time 0.71 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:51 PM PDT 24
Peak memory 197900 kb
Host smart-e33ddef4-3b31-46bd-9abf-c457f373607c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165620384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1165620384
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1594728037
Short name T535
Test name
Test status
Simulation time 17652208 ps
CPU time 0.6 seconds
Started Aug 17 05:54:10 PM PDT 24
Finished Aug 17 05:54:11 PM PDT 24
Peak memory 195248 kb
Host smart-ae9c3c58-b57e-468c-9f79-044942a7251f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594728037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1594728037
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1222791547
Short name T644
Test name
Test status
Simulation time 934732415 ps
CPU time 1.07 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:12 PM PDT 24
Peak memory 198904 kb
Host smart-9a9f6a19-0389-4492-b799-f512acd86360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222791547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1222791547
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1146808475
Short name T75
Test name
Test status
Simulation time 72382166 ps
CPU time 4.05 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:55 PM PDT 24
Peak memory 200176 kb
Host smart-7188ac82-dfc2-44e6-99f7-d6990ba10c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146808475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1146808475
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1534396378
Short name T124
Test name
Test status
Simulation time 599000033 ps
CPU time 2.67 seconds
Started Aug 17 05:53:51 PM PDT 24
Finished Aug 17 05:53:53 PM PDT 24
Peak memory 200248 kb
Host smart-b4d71493-67a3-4de9-ae6f-c6bf678109e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534396378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1534396378
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2862922206
Short name T147
Test name
Test status
Simulation time 318602631 ps
CPU time 12.05 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:27 PM PDT 24
Peak memory 200588 kb
Host smart-2f47387c-76fc-4356-9019-9f7cf896eca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862922206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2862922206
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3727913678
Short name T497
Test name
Test status
Simulation time 6972134209 ps
CPU time 25.97 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 200740 kb
Host smart-62eb99e3-01c8-40fe-a802-5fcba3876005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727913678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3727913678
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2761891533
Short name T486
Test name
Test status
Simulation time 13389380618 ps
CPU time 532.36 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 06:03:00 PM PDT 24
Peak memory 687928 kb
Host smart-00037fb5-54b4-48a6-859c-32ed67473e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2761891533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2761891533
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.362133642
Short name T431
Test name
Test status
Simulation time 6303125226 ps
CPU time 112.83 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:56:08 PM PDT 24
Peak memory 200740 kb
Host smart-2a6b0c12-59a7-4fcc-89fe-0cfd55e12f7b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362133642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.362133642
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.969435236
Short name T201
Test name
Test status
Simulation time 1864829074 ps
CPU time 106.81 seconds
Started Aug 17 05:54:07 PM PDT 24
Finished Aug 17 05:55:53 PM PDT 24
Peak memory 200700 kb
Host smart-dc041b87-b4e6-4a1a-a078-e2d8c7d7029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969435236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.969435236
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1178372967
Short name T58
Test name
Test status
Simulation time 189572754 ps
CPU time 0.8 seconds
Started Aug 17 05:54:17 PM PDT 24
Finished Aug 17 05:54:18 PM PDT 24
Peak memory 219024 kb
Host smart-f423f2d3-a780-4e91-adee-5ea3e8341b5c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178372967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1178372967
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2230093355
Short name T158
Test name
Test status
Simulation time 962075779 ps
CPU time 16.94 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:31 PM PDT 24
Peak memory 200756 kb
Host smart-a1940d49-a732-44b4-949f-0a2eb3f221ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230093355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2230093355
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3668517024
Short name T96
Test name
Test status
Simulation time 617733722699 ps
CPU time 2668.17 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 06:38:42 PM PDT 24
Peak memory 809680 kb
Host smart-280269e3-d0ba-4d02-bb20-441fdf43a406
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668517024 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3668517024
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3448222428
Short name T327
Test name
Test status
Simulation time 19578565679 ps
CPU time 78.87 seconds
Started Aug 17 05:54:05 PM PDT 24
Finished Aug 17 05:55:24 PM PDT 24
Peak memory 200736 kb
Host smart-8ce4515a-9f14-496d-8cd6-aed8eed00cb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3448222428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3448222428
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3333771106
Short name T430
Test name
Test status
Simulation time 4783447896 ps
CPU time 97.45 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:55:54 PM PDT 24
Peak memory 200736 kb
Host smart-a7aa9390-74e0-429c-8633-a262b29313dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3333771106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3333771106
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1538199195
Short name T226
Test name
Test status
Simulation time 8230280617 ps
CPU time 66.88 seconds
Started Aug 17 05:54:12 PM PDT 24
Finished Aug 17 05:55:19 PM PDT 24
Peak memory 200732 kb
Host smart-ef794e27-bc9b-4a0a-b51d-f1d103ca95e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1538199195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1538199195
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3387548385
Short name T399
Test name
Test status
Simulation time 904607178398 ps
CPU time 709.76 seconds
Started Aug 17 05:54:07 PM PDT 24
Finished Aug 17 06:05:57 PM PDT 24
Peak memory 200672 kb
Host smart-9d0bd734-7245-4afe-bc48-67d24d1b8479
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3387548385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3387548385
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.736410902
Short name T152
Test name
Test status
Simulation time 586724355022 ps
CPU time 2584.96 seconds
Started Aug 17 05:54:11 PM PDT 24
Finished Aug 17 06:37:16 PM PDT 24
Peak memory 216064 kb
Host smart-782f6eac-808f-4dd8-8794-7fd792c46ea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=736410902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.736410902
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3316769386
Short name T193
Test name
Test status
Simulation time 138288621366 ps
CPU time 2319.29 seconds
Started Aug 17 05:54:08 PM PDT 24
Finished Aug 17 06:32:47 PM PDT 24
Peak memory 216644 kb
Host smart-10286a63-0c58-4850-8f4d-cb2af63ab022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3316769386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3316769386
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3430601485
Short name T285
Test name
Test status
Simulation time 3028130947 ps
CPU time 73.71 seconds
Started Aug 17 05:54:06 PM PDT 24
Finished Aug 17 05:55:20 PM PDT 24
Peak memory 200780 kb
Host smart-f8bad55f-8ba7-471c-ba3b-861de9567996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430601485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3430601485
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1815050583
Short name T301
Test name
Test status
Simulation time 23510131 ps
CPU time 0.61 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:54:16 PM PDT 24
Peak memory 196740 kb
Host smart-ef0fee7a-843b-478e-9e61-6daf3e604a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815050583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1815050583
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4292055708
Short name T473
Test name
Test status
Simulation time 1170202579 ps
CPU time 17.58 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:54:32 PM PDT 24
Peak memory 200728 kb
Host smart-2936193b-75b1-424e-b093-7da42c537478
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292055708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4292055708
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.70174963
Short name T46
Test name
Test status
Simulation time 8508359644 ps
CPU time 15.44 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:54:32 PM PDT 24
Peak memory 200644 kb
Host smart-890519a4-c784-4e38-9444-867af0104401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70174963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.70174963
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1639809364
Short name T40
Test name
Test status
Simulation time 18456884266 ps
CPU time 757.24 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:07:09 PM PDT 24
Peak memory 692844 kb
Host smart-52766cbf-a41b-4c1d-85aa-e5b2de181deb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1639809364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1639809364
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2377534985
Short name T162
Test name
Test status
Simulation time 2059416106 ps
CPU time 115.41 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:56:11 PM PDT 24
Peak memory 200656 kb
Host smart-5802a602-e791-4455-872f-8f1a95ea4421
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377534985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2377534985
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2184805458
Short name T496
Test name
Test status
Simulation time 25752603841 ps
CPU time 183.73 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 05:57:27 PM PDT 24
Peak memory 200756 kb
Host smart-f37af7f9-47b3-4ad9-8195-1973a069aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184805458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2184805458
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3392145327
Short name T57
Test name
Test status
Simulation time 736063867 ps
CPU time 0.89 seconds
Started Aug 17 05:54:13 PM PDT 24
Finished Aug 17 05:54:14 PM PDT 24
Peak memory 218900 kb
Host smart-c6e201b3-1ce7-422c-ba5c-d425e65dd338
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392145327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3392145327
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.632902695
Short name T242
Test name
Test status
Simulation time 78534260 ps
CPU time 3.71 seconds
Started Aug 17 05:54:18 PM PDT 24
Finished Aug 17 05:54:21 PM PDT 24
Peak memory 200632 kb
Host smart-95f17302-82f5-45d8-99fc-7a21c954809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632902695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.632902695
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1142602200
Short name T121
Test name
Test status
Simulation time 50183506576 ps
CPU time 1314.94 seconds
Started Aug 17 05:54:18 PM PDT 24
Finished Aug 17 06:16:13 PM PDT 24
Peak memory 651684 kb
Host smart-f67b2537-b38c-48b2-81c6-0a8264643927
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142602200 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1142602200
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3811278097
Short name T32
Test name
Test status
Simulation time 4423047128 ps
CPU time 37.63 seconds
Started Aug 17 05:54:21 PM PDT 24
Finished Aug 17 05:54:59 PM PDT 24
Peak memory 200748 kb
Host smart-426d1cef-7afc-4b02-b1f4-6e6336981e38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3811278097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3811278097
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3988524347
Short name T407
Test name
Test status
Simulation time 10903719915 ps
CPU time 61.97 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:55:16 PM PDT 24
Peak memory 200716 kb
Host smart-fa5a8a0b-9b5e-4960-a79a-433c0cfc0ce7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3988524347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3988524347
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1304016813
Short name T153
Test name
Test status
Simulation time 3676395665 ps
CPU time 72.03 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 05:55:26 PM PDT 24
Peak memory 200732 kb
Host smart-43da6656-d106-4b05-8aab-e529c0dd188f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1304016813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1304016813
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2306374270
Short name T213
Test name
Test status
Simulation time 1519844898535 ps
CPU time 2335.08 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:33:27 PM PDT 24
Peak memory 216444 kb
Host smart-3831e081-f088-4f4b-b0b2-187b92c03bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2306374270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2306374270
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2019450175
Short name T363
Test name
Test status
Simulation time 615336956108 ps
CPU time 2389.81 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:34:22 PM PDT 24
Peak memory 216188 kb
Host smart-4906e80b-9765-42b9-9064-5f0062a5afa6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2019450175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2019450175
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3886208105
Short name T346
Test name
Test status
Simulation time 21945434581 ps
CPU time 160.02 seconds
Started Aug 17 05:54:24 PM PDT 24
Finished Aug 17 05:57:04 PM PDT 24
Peak memory 200760 kb
Host smart-d7a75cde-cd74-4b4b-b817-1a524c8ece73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886208105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3886208105
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1378222558
Short name T396
Test name
Test status
Simulation time 15529119 ps
CPU time 0.6 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 196748 kb
Host smart-e66877d1-d303-4cad-b949-b0357df3be53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378222558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1378222558
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2361702623
Short name T240
Test name
Test status
Simulation time 3104163743 ps
CPU time 47.5 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:55:23 PM PDT 24
Peak memory 200644 kb
Host smart-ea253d98-1394-473b-822f-bfe8d1af1536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361702623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2361702623
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2655304848
Short name T328
Test name
Test status
Simulation time 3772271791 ps
CPU time 19.01 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:54:54 PM PDT 24
Peak memory 200720 kb
Host smart-3d69ff07-f098-4ea4-9e84-36a3cc5de4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655304848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2655304848
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1769934578
Short name T401
Test name
Test status
Simulation time 9685457130 ps
CPU time 387.92 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 06:01:03 PM PDT 24
Peak memory 603708 kb
Host smart-b0f07ec3-6682-4a28-9ea4-f789b06ea10a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769934578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1769934578
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.139551135
Short name T481
Test name
Test status
Simulation time 3743504683 ps
CPU time 201.21 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:57:50 PM PDT 24
Peak memory 200736 kb
Host smart-d8f81820-07be-439e-890a-173ea63fa347
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139551135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.139551135
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_smoke.942173394
Short name T321
Test name
Test status
Simulation time 1263253035 ps
CPU time 5.6 seconds
Started Aug 17 05:54:43 PM PDT 24
Finished Aug 17 05:54:49 PM PDT 24
Peak memory 200620 kb
Host smart-2c16f246-b9a1-4bbe-b8ec-3c3c7d3f1d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942173394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.942173394
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3602609485
Short name T84
Test name
Test status
Simulation time 308171179148 ps
CPU time 2255.95 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:32:08 PM PDT 24
Peak memory 776756 kb
Host smart-4ca91882-d819-43ce-9511-33d2f3de0913
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602609485 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3602609485
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2765384063
Short name T426
Test name
Test status
Simulation time 3038265886 ps
CPU time 70.52 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:55:39 PM PDT 24
Peak memory 200764 kb
Host smart-d9cae5da-91cf-4390-8586-f80fb81e9e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765384063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2765384063
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1635416335
Short name T382
Test name
Test status
Simulation time 12927431 ps
CPU time 0.58 seconds
Started Aug 17 05:54:37 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 196448 kb
Host smart-cf538be8-857e-492a-a70f-3eb19a923d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635416335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1635416335
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.758373923
Short name T351
Test name
Test status
Simulation time 282408454 ps
CPU time 17.16 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 200640 kb
Host smart-e9f75703-fbc9-4e05-ac69-595bd2c81edd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=758373923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.758373923
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1916515948
Short name T322
Test name
Test status
Simulation time 3471588227 ps
CPU time 16.3 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:54:45 PM PDT 24
Peak memory 200740 kb
Host smart-dbee247b-8d04-4450-ba0e-7520ba0c9d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916515948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1916515948
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.295561440
Short name T300
Test name
Test status
Simulation time 20907602366 ps
CPU time 1408.22 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:18:00 PM PDT 24
Peak memory 724928 kb
Host smart-f0ba4080-ef4e-4f32-a97e-123f99b70568
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295561440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.295561440
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2726041082
Short name T331
Test name
Test status
Simulation time 24046708095 ps
CPU time 97.22 seconds
Started Aug 17 05:54:41 PM PDT 24
Finished Aug 17 05:56:18 PM PDT 24
Peak memory 200720 kb
Host smart-c442a2e1-df93-4cab-81df-d99672d3f041
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726041082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2726041082
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1669960716
Short name T323
Test name
Test status
Simulation time 56512599635 ps
CPU time 186.21 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:57:40 PM PDT 24
Peak memory 200692 kb
Host smart-79e78a77-b068-42e4-83c0-6ccc58488268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669960716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1669960716
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.623433749
Short name T4
Test name
Test status
Simulation time 403006375 ps
CPU time 7.27 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 200660 kb
Host smart-ed1ec948-b761-47d6-b156-fc13193f6360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623433749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.623433749
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1532973764
Short name T320
Test name
Test status
Simulation time 3884937675 ps
CPU time 70.6 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:55:45 PM PDT 24
Peak memory 200628 kb
Host smart-d5116e40-7bb7-46bc-b264-08ca6f84c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532973764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1532973764
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1359134638
Short name T144
Test name
Test status
Simulation time 43894330 ps
CPU time 0.57 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 05:54:43 PM PDT 24
Peak memory 195688 kb
Host smart-0f2fcee8-ef88-4424-8a5e-a145772c6751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359134638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1359134638
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.307962017
Short name T175
Test name
Test status
Simulation time 628188725 ps
CPU time 10.34 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:54:44 PM PDT 24
Peak memory 200648 kb
Host smart-240598ea-af2a-4cf2-b941-e2e5e7d07540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307962017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.307962017
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.181826522
Short name T319
Test name
Test status
Simulation time 6140349187 ps
CPU time 22.54 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:54:57 PM PDT 24
Peak memory 200732 kb
Host smart-059d9f72-995e-40a4-bd7f-6e9b549c9a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181826522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.181826522
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2517856380
Short name T348
Test name
Test status
Simulation time 11598967658 ps
CPU time 879.18 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 06:09:08 PM PDT 24
Peak memory 719028 kb
Host smart-ed10b5d4-415b-4a31-a374-325ff42e4ab1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517856380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2517856380
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2169695707
Short name T7
Test name
Test status
Simulation time 12446970337 ps
CPU time 154.65 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:57:05 PM PDT 24
Peak memory 200792 kb
Host smart-ea7fa38d-8735-4408-b798-0277051f54a9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169695707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2169695707
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4204924536
Short name T427
Test name
Test status
Simulation time 11886208303 ps
CPU time 82.08 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:55:56 PM PDT 24
Peak memory 200820 kb
Host smart-687c4d0b-55be-4bbb-be42-0e33a901e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204924536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4204924536
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.576928298
Short name T517
Test name
Test status
Simulation time 1359699266 ps
CPU time 14.77 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:55:04 PM PDT 24
Peak memory 200720 kb
Host smart-0617ef7c-23a2-4cef-b106-598702cd0e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576928298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.576928298
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.245026270
Short name T13
Test name
Test status
Simulation time 20268002507 ps
CPU time 1308.36 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 06:16:22 PM PDT 24
Peak memory 504968 kb
Host smart-a09b76d7-9665-4b61-8f2d-56a014e3012d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245026270 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.245026270
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3511364515
Short name T355
Test name
Test status
Simulation time 1903030954 ps
CPU time 4.37 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:54:42 PM PDT 24
Peak memory 200632 kb
Host smart-410f0a28-4306-43b8-aed0-fcbc7d0d5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511364515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3511364515
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1541615675
Short name T470
Test name
Test status
Simulation time 54937477 ps
CPU time 0.65 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 196744 kb
Host smart-4176e50e-dfee-4af1-81e4-d7b4d6eabdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541615675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1541615675
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.4051138293
Short name T204
Test name
Test status
Simulation time 870219447 ps
CPU time 22.52 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:54:58 PM PDT 24
Peak memory 200664 kb
Host smart-899803cd-a5f2-4258-b994-d9790905b3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051138293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.4051138293
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3704847010
Short name T425
Test name
Test status
Simulation time 5476156117 ps
CPU time 71.99 seconds
Started Aug 17 05:54:44 PM PDT 24
Finished Aug 17 05:55:56 PM PDT 24
Peak memory 208920 kb
Host smart-41aac384-a0dc-4e66-bfaa-c45f3b5ef5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704847010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3704847010
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.640876113
Short name T267
Test name
Test status
Simulation time 8111739712 ps
CPU time 401.07 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 06:01:11 PM PDT 24
Peak memory 640720 kb
Host smart-f8ad7f50-aa11-4fdf-b29f-33fa511ba6ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640876113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.640876113
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3309943176
Short name T190
Test name
Test status
Simulation time 578397146 ps
CPU time 30.46 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:55:08 PM PDT 24
Peak memory 200496 kb
Host smart-d566a17b-7a4a-451b-9a43-ef2a750f90e8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309943176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3309943176
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1985055160
Short name T222
Test name
Test status
Simulation time 66883821955 ps
CPU time 216.23 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:58:06 PM PDT 24
Peak memory 200904 kb
Host smart-c431b0ca-4553-4a50-97e1-7827d33b676a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985055160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1985055160
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3449349158
Short name T442
Test name
Test status
Simulation time 3283438922 ps
CPU time 12.24 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 200716 kb
Host smart-1b45935d-e310-4f1d-8d11-d091e57ae40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449349158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3449349158
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1141234767
Short name T475
Test name
Test status
Simulation time 15919559821 ps
CPU time 73.03 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:56:13 PM PDT 24
Peak memory 200616 kb
Host smart-3e92aa25-c93c-4b4e-804f-7a7c96d8ce89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141234767 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1141234767
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1180418133
Short name T148
Test name
Test status
Simulation time 1097260920 ps
CPU time 19.9 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:54:56 PM PDT 24
Peak memory 200584 kb
Host smart-50c2e29b-b316-425b-98d5-e2e7093aa2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180418133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1180418133
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1567558247
Short name T326
Test name
Test status
Simulation time 18026856 ps
CPU time 0.6 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 197336 kb
Host smart-58faa87a-b943-4616-855a-6c980f65996b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567558247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1567558247
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1853588436
Short name T460
Test name
Test status
Simulation time 1593339695 ps
CPU time 84.23 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:56:02 PM PDT 24
Peak memory 200660 kb
Host smart-6384847c-88cd-4597-aee4-9d6ac55cd83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1853588436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1853588436
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3477961186
Short name T419
Test name
Test status
Simulation time 2636295749 ps
CPU time 32.42 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:55:27 PM PDT 24
Peak memory 200616 kb
Host smart-1d6d185f-8f64-4a7e-a21a-81420085e6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477961186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3477961186
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3338524763
Short name T64
Test name
Test status
Simulation time 22286248867 ps
CPU time 1026.05 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 06:11:43 PM PDT 24
Peak memory 732640 kb
Host smart-9c4d9d21-fbda-4a11-85ec-1544472b6894
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3338524763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3338524763
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.622416480
Short name T250
Test name
Test status
Simulation time 7333557105 ps
CPU time 53.91 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:55:27 PM PDT 24
Peak memory 200644 kb
Host smart-0ee71e7c-8a94-457a-b7cc-bca765f9a610
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622416480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.622416480
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1256525150
Short name T516
Test name
Test status
Simulation time 2200338797 ps
CPU time 31.94 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:55:10 PM PDT 24
Peak memory 200736 kb
Host smart-ff82adf4-fc83-4d27-af10-385a17cdc421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256525150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1256525150
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3656462849
Short name T304
Test name
Test status
Simulation time 23697672 ps
CPU time 0.73 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 05:54:43 PM PDT 24
Peak memory 198540 kb
Host smart-2dae955b-e4e0-4ee3-a14a-faea965b0027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656462849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3656462849
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2281076479
Short name T375
Test name
Test status
Simulation time 122035568785 ps
CPU time 997.63 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 06:11:16 PM PDT 24
Peak memory 706252 kb
Host smart-50ff04f3-2768-4bcd-8bf2-b67d976aa448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281076479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2281076479
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1736421735
Short name T527
Test name
Test status
Simulation time 3636332685 ps
CPU time 128.28 seconds
Started Aug 17 05:54:40 PM PDT 24
Finished Aug 17 05:56:48 PM PDT 24
Peak memory 200792 kb
Host smart-f9680f98-7564-414a-a539-0c29d9eb0759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736421735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1736421735
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.449802760
Short name T312
Test name
Test status
Simulation time 23444856 ps
CPU time 0.6 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:54:35 PM PDT 24
Peak memory 196760 kb
Host smart-2a582b5c-c2e8-4f7e-a083-34aafaf0a263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449802760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.449802760
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2727690293
Short name T506
Test name
Test status
Simulation time 12573969158 ps
CPU time 77.93 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:55:50 PM PDT 24
Peak memory 200708 kb
Host smart-b8732ea0-ceb4-4e7d-bbb3-ef487ce6bcfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727690293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2727690293
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1608458431
Short name T28
Test name
Test status
Simulation time 8586056697 ps
CPU time 470.75 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 06:02:27 PM PDT 24
Peak memory 674836 kb
Host smart-39457746-16c9-4450-98cf-b39c95e691e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608458431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1608458431
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3598073762
Short name T275
Test name
Test status
Simulation time 41325328475 ps
CPU time 175.28 seconds
Started Aug 17 05:54:39 PM PDT 24
Finished Aug 17 05:57:34 PM PDT 24
Peak memory 200724 kb
Host smart-84136bbc-cd8b-4270-b17d-94d8d792c135
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598073762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3598073762
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2410111200
Short name T164
Test name
Test status
Simulation time 5196814389 ps
CPU time 121.72 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:56:38 PM PDT 24
Peak memory 200748 kb
Host smart-26ebcca0-a285-4398-b781-6fdaa40b4cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410111200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2410111200
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1112320941
Short name T508
Test name
Test status
Simulation time 214508460 ps
CPU time 3.53 seconds
Started Aug 17 05:54:37 PM PDT 24
Finished Aug 17 05:54:41 PM PDT 24
Peak memory 200672 kb
Host smart-ecafc0db-8233-46c7-a912-2797492724f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112320941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1112320941
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1872933331
Short name T303
Test name
Test status
Simulation time 11392676028 ps
CPU time 1843.53 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 06:25:19 PM PDT 24
Peak memory 746032 kb
Host smart-6db57296-aceb-462f-90b8-55191d27e527
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872933331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1872933331
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4057792263
Short name T345
Test name
Test status
Simulation time 5320677628 ps
CPU time 66 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:55:40 PM PDT 24
Peak memory 200676 kb
Host smart-4d33a55d-ef33-4013-ac38-d41d3408c238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057792263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4057792263
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2493925558
Short name T441
Test name
Test status
Simulation time 17371962 ps
CPU time 0.62 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:54:51 PM PDT 24
Peak memory 196736 kb
Host smart-714be389-0475-4418-9f02-4bf613b13301
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493925558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2493925558
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3680459160
Short name T234
Test name
Test status
Simulation time 36030457 ps
CPU time 2.03 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 05:54:44 PM PDT 24
Peak memory 200588 kb
Host smart-63b86805-9d2a-4f3b-9c69-2fd58c3e8a5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3680459160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3680459160
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1776307067
Short name T246
Test name
Test status
Simulation time 1892695864 ps
CPU time 21.5 seconds
Started Aug 17 05:54:39 PM PDT 24
Finished Aug 17 05:55:00 PM PDT 24
Peak memory 200640 kb
Host smart-c22b3cc5-a2c5-4b86-bdf9-abb65b77d0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776307067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1776307067
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.152203006
Short name T509
Test name
Test status
Simulation time 10212638684 ps
CPU time 447.04 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 06:02:09 PM PDT 24
Peak memory 598464 kb
Host smart-72747fdf-05c9-445d-8b1e-bd2b3fe2191e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152203006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.152203006
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2896186157
Short name T18
Test name
Test status
Simulation time 17515575 ps
CPU time 0.64 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:54:48 PM PDT 24
Peak memory 197092 kb
Host smart-ca23a4c1-5071-49c8-9c74-596b74dde906
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896186157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2896186157
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_smoke.4242309756
Short name T389
Test name
Test status
Simulation time 537723036 ps
CPU time 12.44 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:54:45 PM PDT 24
Peak memory 200748 kb
Host smart-1d09be18-637c-435b-a7fb-b9dc97e677e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242309756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4242309756
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.1991640823
Short name T525
Test name
Test status
Simulation time 14094530240 ps
CPU time 29.93 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:55:06 PM PDT 24
Peak memory 200788 kb
Host smart-80f8ad58-421d-4f22-a847-cfccfb02f86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991640823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1991640823
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3297780451
Short name T455
Test name
Test status
Simulation time 14899281 ps
CPU time 0.58 seconds
Started Aug 17 05:54:44 PM PDT 24
Finished Aug 17 05:54:45 PM PDT 24
Peak memory 196396 kb
Host smart-c232b9d0-fad9-44a3-9959-457119d295cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297780451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3297780451
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.805239417
Short name T254
Test name
Test status
Simulation time 1581265670 ps
CPU time 18.4 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:55:10 PM PDT 24
Peak memory 200596 kb
Host smart-6ad669de-e09b-4628-a82a-c6e35e2f92d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=805239417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.805239417
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3142975965
Short name T476
Test name
Test status
Simulation time 6218219261 ps
CPU time 73.51 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 208948 kb
Host smart-be281df2-1177-4c12-9ef9-ed3a93a0db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142975965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3142975965
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3174316863
Short name T263
Test name
Test status
Simulation time 13204844269 ps
CPU time 532.51 seconds
Started Aug 17 05:54:41 PM PDT 24
Finished Aug 17 06:03:33 PM PDT 24
Peak memory 699812 kb
Host smart-4164efa7-c133-4511-a1f7-5b0abc8b480d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174316863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3174316863
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3495693647
Short name T354
Test name
Test status
Simulation time 15410944619 ps
CPU time 90.35 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:56:25 PM PDT 24
Peak memory 200640 kb
Host smart-66c363b3-1ba9-40de-b2cb-94201e3a49d0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495693647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3495693647
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3624869407
Short name T288
Test name
Test status
Simulation time 2298372040 ps
CPU time 23.03 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:55:13 PM PDT 24
Peak memory 200784 kb
Host smart-df7b4056-6b82-48c5-acb9-7555c86112e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624869407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3624869407
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.902410825
Short name T289
Test name
Test status
Simulation time 1370802435 ps
CPU time 9.04 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:55:02 PM PDT 24
Peak memory 200404 kb
Host smart-cf752992-86a0-4104-ac7b-a8bc3960e7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902410825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.902410825
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1084552658
Short name T498
Test name
Test status
Simulation time 28814999459 ps
CPU time 86.45 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:56:17 PM PDT 24
Peak memory 200640 kb
Host smart-6b356031-d8d2-41fc-a171-a0cf256953ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084552658 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1084552658
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2740739868
Short name T120
Test name
Test status
Simulation time 7786255570 ps
CPU time 106.24 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 200752 kb
Host smart-fec99ac7-43c9-4e91-8985-d29b49cdedce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740739868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2740739868
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3158050724
Short name T520
Test name
Test status
Simulation time 22210702 ps
CPU time 0.57 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 196740 kb
Host smart-d34b5761-e8e1-4dc5-9d5c-f70fd317ca22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158050724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3158050724
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4082083204
Short name T225
Test name
Test status
Simulation time 3417685226 ps
CPU time 50.26 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:55:37 PM PDT 24
Peak memory 200784 kb
Host smart-4189ff99-be6a-4d60-ad71-897a992d9954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082083204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4082083204
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3754317310
Short name T349
Test name
Test status
Simulation time 3013821512 ps
CPU time 39.44 seconds
Started Aug 17 05:54:43 PM PDT 24
Finished Aug 17 05:55:23 PM PDT 24
Peak memory 200700 kb
Host smart-f15145d9-42ef-483f-97d7-0c7ccdb8d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754317310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3754317310
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2215652465
Short name T262
Test name
Test status
Simulation time 14161461185 ps
CPU time 1394.18 seconds
Started Aug 17 05:54:56 PM PDT 24
Finished Aug 17 06:18:10 PM PDT 24
Peak memory 765192 kb
Host smart-6cd340cf-d72f-4e51-95ef-4bc4d0ebf0fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215652465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2215652465
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2742036976
Short name T12
Test name
Test status
Simulation time 46090150787 ps
CPU time 212.25 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 05:58:14 PM PDT 24
Peak memory 200724 kb
Host smart-1ec284a1-6fdc-4ad0-8f77-8951321edf02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742036976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2742036976
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.3685447154
Short name T416
Test name
Test status
Simulation time 4319763717 ps
CPU time 61.8 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:55:51 PM PDT 24
Peak memory 200752 kb
Host smart-313682ff-ab64-4a27-a3b9-95ba4d023791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685447154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.3685447154
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3563593516
Short name T291
Test name
Test status
Simulation time 3266585854 ps
CPU time 12.14 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:55:06 PM PDT 24
Peak memory 200688 kb
Host smart-875fa296-f28d-4839-b95e-87e17b76d6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563593516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3563593516
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3445287334
Short name T480
Test name
Test status
Simulation time 19613520815 ps
CPU time 463.48 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 06:02:30 PM PDT 24
Peak memory 581932 kb
Host smart-d1cd288b-b639-4929-a04d-1c438a147d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445287334 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3445287334
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.397434792
Short name T370
Test name
Test status
Simulation time 38944850630 ps
CPU time 136.69 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:57:10 PM PDT 24
Peak memory 200684 kb
Host smart-e4f71424-4ce3-4c42-b7a4-37fbc02a7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397434792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.397434792
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.700012016
Short name T524
Test name
Test status
Simulation time 19490257 ps
CPU time 0.57 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 196744 kb
Host smart-75412192-b89a-47dc-be8a-3763b09557ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700012016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.700012016
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.890182049
Short name T223
Test name
Test status
Simulation time 573997185 ps
CPU time 26.25 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:55:17 PM PDT 24
Peak memory 200660 kb
Host smart-57cf944c-d155-449d-99d0-5d248a02ed8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890182049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.890182049
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2041967917
Short name T35
Test name
Test status
Simulation time 2078840863 ps
CPU time 36.23 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:36 PM PDT 24
Peak memory 200656 kb
Host smart-73c88768-c004-4e82-be8f-b0a59deed6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041967917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2041967917
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2572220743
Short name T63
Test name
Test status
Simulation time 7636441199 ps
CPU time 371.58 seconds
Started Aug 17 05:54:45 PM PDT 24
Finished Aug 17 06:00:57 PM PDT 24
Peak memory 651724 kb
Host smart-18378ba8-b59b-4fe9-9851-0a8b9b4fd0e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572220743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2572220743
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.617346152
Short name T364
Test name
Test status
Simulation time 4203691286 ps
CPU time 196.95 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:58:12 PM PDT 24
Peak memory 200748 kb
Host smart-7ff4edb2-a829-4ed3-a8f0-672865e27a74
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617346152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.617346152
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3949023071
Short name T231
Test name
Test status
Simulation time 61101524283 ps
CPU time 181.24 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:57:59 PM PDT 24
Peak memory 200680 kb
Host smart-14c8665a-5708-48e4-9dad-29429cc545ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949023071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3949023071
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.370921983
Short name T196
Test name
Test status
Simulation time 673257256 ps
CPU time 6.19 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:54:57 PM PDT 24
Peak memory 200672 kb
Host smart-37f7aa9f-4271-4849-986d-1d6a6e997fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370921983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.370921983
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3132784500
Short name T356
Test name
Test status
Simulation time 122577023316 ps
CPU time 800.21 seconds
Started Aug 17 05:54:48 PM PDT 24
Finished Aug 17 06:08:09 PM PDT 24
Peak memory 642916 kb
Host smart-e21d3870-3ac0-4441-96eb-d0a396cb25ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132784500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3132784500
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3759289637
Short name T454
Test name
Test status
Simulation time 3368421776 ps
CPU time 50.57 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:55:41 PM PDT 24
Peak memory 200732 kb
Host smart-f8fc1b98-0187-4865-9e89-476cbad89153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759289637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3759289637
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3505301465
Short name T422
Test name
Test status
Simulation time 46580877 ps
CPU time 0.59 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:54:17 PM PDT 24
Peak memory 196744 kb
Host smart-c080108b-59a7-4c94-958c-4b3214eba7c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505301465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3505301465
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3194208368
Short name T20
Test name
Test status
Simulation time 1460053749 ps
CPU time 92.09 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:55:47 PM PDT 24
Peak memory 200676 kb
Host smart-6921629b-20ba-49c8-ae3c-934e5d434f7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194208368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3194208368
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2409751936
Short name T412
Test name
Test status
Simulation time 13269617415 ps
CPU time 617.33 seconds
Started Aug 17 05:54:20 PM PDT 24
Finished Aug 17 06:04:37 PM PDT 24
Peak memory 759896 kb
Host smart-464659ad-04b9-4cf8-a0e3-9ec8d130aa05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2409751936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2409751936
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.722590441
Short name T388
Test name
Test status
Simulation time 2037121835 ps
CPU time 119.79 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:56:16 PM PDT 24
Peak memory 200684 kb
Host smart-6ffe1ded-c692-4a8f-815c-d73d18fa9349
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722590441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.722590441
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4195889409
Short name T184
Test name
Test status
Simulation time 7807128400 ps
CPU time 72.6 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:55:29 PM PDT 24
Peak memory 200648 kb
Host smart-6bfaa5ee-2ea9-4e48-9827-990ee9e4adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195889409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4195889409
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4278035257
Short name T59
Test name
Test status
Simulation time 127469537 ps
CPU time 0.9 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:54:17 PM PDT 24
Peak memory 219016 kb
Host smart-65705320-3e9d-4bca-99ad-e5b6fb10a576
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278035257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4278035257
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2193472947
Short name T150
Test name
Test status
Simulation time 915349340 ps
CPU time 8.61 seconds
Started Aug 17 05:54:22 PM PDT 24
Finished Aug 17 05:54:31 PM PDT 24
Peak memory 200708 kb
Host smart-c205737d-8a94-4e79-8448-5adb0dffde15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193472947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2193472947
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3599308805
Short name T217
Test name
Test status
Simulation time 74884933364 ps
CPU time 3060.87 seconds
Started Aug 17 05:54:14 PM PDT 24
Finished Aug 17 06:45:16 PM PDT 24
Peak memory 817940 kb
Host smart-d7581c5f-b415-4641-a816-a2c254b63992
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599308805 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3599308805
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1051645017
Short name T409
Test name
Test status
Simulation time 4282090217 ps
CPU time 63.5 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 05:55:18 PM PDT 24
Peak memory 200748 kb
Host smart-7fb97dc2-7bcb-4180-9aea-76b96bf19c17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1051645017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1051645017
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1331401288
Short name T344
Test name
Test status
Simulation time 9949346732 ps
CPU time 100.82 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:56:13 PM PDT 24
Peak memory 200732 kb
Host smart-3147dc76-b6b9-43b8-8e8b-7afbc0642ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1331401288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1331401288
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2484078916
Short name T146
Test name
Test status
Simulation time 16985337937 ps
CPU time 141.25 seconds
Started Aug 17 05:54:17 PM PDT 24
Finished Aug 17 05:56:38 PM PDT 24
Peak memory 200668 kb
Host smart-dff93c99-f679-41ba-b33c-7a2d85f4b804
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2484078916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2484078916
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3322961124
Short name T43
Test name
Test status
Simulation time 137650009649 ps
CPU time 642.64 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 06:05:10 PM PDT 24
Peak memory 200752 kb
Host smart-5c45d5b5-45be-4a11-a364-285c4ffcfede
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3322961124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3322961124
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3173571042
Short name T309
Test name
Test status
Simulation time 282436997115 ps
CPU time 2554.85 seconds
Started Aug 17 05:54:25 PM PDT 24
Finished Aug 17 06:37:00 PM PDT 24
Peak memory 216200 kb
Host smart-591f46b2-3d1a-4998-a050-c587f0e79fbc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3173571042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3173571042
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1661180244
Short name T307
Test name
Test status
Simulation time 277768450095 ps
CPU time 2477.94 seconds
Started Aug 17 05:54:24 PM PDT 24
Finished Aug 17 06:35:43 PM PDT 24
Peak memory 216180 kb
Host smart-41e0c5d0-a9f4-4f9e-a228-10034cebd0e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1661180244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1661180244
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2011440786
Short name T377
Test name
Test status
Simulation time 32415527965 ps
CPU time 144.17 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:56:56 PM PDT 24
Peak memory 200824 kb
Host smart-1a03ed64-2db1-422e-bb70-fa23f7fab0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011440786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2011440786
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.454041276
Short name T484
Test name
Test status
Simulation time 15956423 ps
CPU time 0.59 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 196376 kb
Host smart-85177cf9-48a8-4ba2-a0a3-d514d573a528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454041276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.454041276
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1559494684
Short name T24
Test name
Test status
Simulation time 1593517341 ps
CPU time 84.63 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:56:14 PM PDT 24
Peak memory 200672 kb
Host smart-fb566c65-50b0-4847-8683-51bb52bc860d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559494684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1559494684
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2266312801
Short name T83
Test name
Test status
Simulation time 2615428730 ps
CPU time 13.9 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:55:08 PM PDT 24
Peak memory 200688 kb
Host smart-f43062b5-83aa-4ff1-8c9a-d243345bf541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266312801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2266312801
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1032645209
Short name T224
Test name
Test status
Simulation time 4850550756 ps
CPU time 879.62 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 06:09:33 PM PDT 24
Peak memory 669396 kb
Host smart-36b42167-4a72-4d6a-8966-b6bcca958795
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1032645209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1032645209
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.132821687
Short name T207
Test name
Test status
Simulation time 28838114016 ps
CPU time 201.32 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:58:15 PM PDT 24
Peak memory 200772 kb
Host smart-fea24b36-a324-4217-bfc6-997d88d1d42f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132821687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.132821687
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2243149766
Short name T221
Test name
Test status
Simulation time 5940144849 ps
CPU time 40.6 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:55:34 PM PDT 24
Peak memory 200736 kb
Host smart-f72d13df-e8b2-461f-981a-d3455cb8007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243149766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2243149766
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1248180105
Short name T518
Test name
Test status
Simulation time 548900712 ps
CPU time 12.25 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:55:05 PM PDT 24
Peak memory 200580 kb
Host smart-b3604a13-17cb-4ec5-a029-e1bf83a8e759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248180105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1248180105
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.427622766
Short name T464
Test name
Test status
Simulation time 82748114246 ps
CPU time 360.94 seconds
Started Aug 17 05:54:43 PM PDT 24
Finished Aug 17 06:00:44 PM PDT 24
Peak memory 200724 kb
Host smart-0611a772-b729-4409-9e3f-142cbefb0a86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427622766 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.427622766
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.4038037882
Short name T119
Test name
Test status
Simulation time 6236517620 ps
CPU time 87.34 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 05:56:13 PM PDT 24
Peak memory 200720 kb
Host smart-6c08222b-3299-4c42-aa84-309b509fc13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038037882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.4038037882
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.432124033
Short name T378
Test name
Test status
Simulation time 14542022 ps
CPU time 0.57 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:54:51 PM PDT 24
Peak memory 196736 kb
Host smart-451a21be-d774-4b6d-b427-e7689ff5dbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432124033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.432124033
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1952760260
Short name T530
Test name
Test status
Simulation time 1424895710 ps
CPU time 95.28 seconds
Started Aug 17 05:54:48 PM PDT 24
Finished Aug 17 05:56:23 PM PDT 24
Peak memory 200608 kb
Host smart-d9a27fae-3f1f-481b-b62e-4ca2df2d173c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1952760260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1952760260
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.839197230
Short name T140
Test name
Test status
Simulation time 4980178811 ps
CPU time 42.05 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:37 PM PDT 24
Peak memory 200672 kb
Host smart-9858924d-ae3d-4f4b-88d6-011f547564df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839197230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.839197230
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4178609073
Short name T510
Test name
Test status
Simulation time 684291223 ps
CPU time 124.76 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:57:01 PM PDT 24
Peak memory 575472 kb
Host smart-0c84fb02-dda4-47cf-91c0-ab2b851616a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4178609073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4178609073
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1502245356
Short name T208
Test name
Test status
Simulation time 9331382082 ps
CPU time 130.74 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 200676 kb
Host smart-fd7d7ecd-9ba2-4341-9916-eb884ddc9496
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502245356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1502245356
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3624768033
Short name T36
Test name
Test status
Simulation time 1855211373 ps
CPU time 30.76 seconds
Started Aug 17 05:54:44 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200680 kb
Host smart-2ba32d79-e1bd-4179-b4a3-251f35bd8ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624768033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3624768033
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.588163636
Short name T402
Test name
Test status
Simulation time 460639807 ps
CPU time 2.6 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:54:56 PM PDT 24
Peak memory 200608 kb
Host smart-1a654432-11df-4a49-a2f2-3627250684f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588163636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.588163636
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3700347652
Short name T141
Test name
Test status
Simulation time 43212447434 ps
CPU time 591.51 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 06:04:44 PM PDT 24
Peak memory 217044 kb
Host smart-01bc245d-34f7-4f5a-bbd5-9d1957611d97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700347652 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3700347652
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1283706373
Short name T415
Test name
Test status
Simulation time 419279186 ps
CPU time 6 seconds
Started Aug 17 05:54:46 PM PDT 24
Finished Aug 17 05:54:52 PM PDT 24
Peak memory 200668 kb
Host smart-0bdb5238-bb50-4783-9757-8c36d5d8eac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283706373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1283706373
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1522808903
Short name T505
Test name
Test status
Simulation time 42228918 ps
CPU time 0.59 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:54:51 PM PDT 24
Peak memory 196744 kb
Host smart-0f148d96-f519-44e8-b25a-ccbda5c6f7fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522808903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1522808903
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1571505204
Short name T194
Test name
Test status
Simulation time 252506418 ps
CPU time 15.9 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:55:03 PM PDT 24
Peak memory 200612 kb
Host smart-b4e74155-b2d8-4ef7-95a0-946782d8fdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1571505204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1571505204
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1851393412
Short name T277
Test name
Test status
Simulation time 2984756326 ps
CPU time 59.21 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:55:57 PM PDT 24
Peak memory 200744 kb
Host smart-729793ac-9072-48d9-b982-79234d60da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851393412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1851393412
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1393823294
Short name T360
Test name
Test status
Simulation time 20295755444 ps
CPU time 504.86 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 06:03:15 PM PDT 24
Peak memory 683992 kb
Host smart-4d481c61-eac4-4f14-9a33-e6f1629e5f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393823294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1393823294
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2737068661
Short name T459
Test name
Test status
Simulation time 15009279112 ps
CPU time 191.78 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:58:01 PM PDT 24
Peak memory 200788 kb
Host smart-8a51b3f3-c8d7-4bd9-bcd4-1fd42b94caa9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737068661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2737068661
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1496572451
Short name T340
Test name
Test status
Simulation time 11873588742 ps
CPU time 73.27 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:56:05 PM PDT 24
Peak memory 216944 kb
Host smart-c66c5760-e46c-4193-a044-5990e4684a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496572451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1496572451
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2819074821
Short name T176
Test name
Test status
Simulation time 232647975 ps
CPU time 4.22 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:55:01 PM PDT 24
Peak memory 200676 kb
Host smart-076de33b-c408-4b45-999a-3502686e8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819074821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2819074821
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4277727841
Short name T86
Test name
Test status
Simulation time 76964937707 ps
CPU time 2688.06 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 06:39:42 PM PDT 24
Peak memory 832624 kb
Host smart-0a0827f6-b171-4741-8a32-64b32ffa9375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277727841 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4277727841
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3848155322
Short name T446
Test name
Test status
Simulation time 1685862820 ps
CPU time 75.31 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:56:02 PM PDT 24
Peak memory 200680 kb
Host smart-14b7fa32-1f82-42a6-ae07-bfd42b5c9889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848155322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3848155322
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1658131308
Short name T245
Test name
Test status
Simulation time 12138632 ps
CPU time 0.6 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:54:55 PM PDT 24
Peak memory 197420 kb
Host smart-da586f1e-d9eb-4c92-bed6-996550788476
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658131308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1658131308
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.836502906
Short name T287
Test name
Test status
Simulation time 253003264 ps
CPU time 14.81 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:55:07 PM PDT 24
Peak memory 200568 kb
Host smart-8f7beb03-6b8e-47c4-a130-f97e70590ad0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836502906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.836502906
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2988834694
Short name T341
Test name
Test status
Simulation time 7532423397 ps
CPU time 29.41 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:55:20 PM PDT 24
Peak memory 200804 kb
Host smart-3722e496-3add-4ab2-a1c6-9ae872499d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988834694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2988834694
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1191009519
Short name T232
Test name
Test status
Simulation time 4953379264 ps
CPU time 990.29 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 06:11:18 PM PDT 24
Peak memory 680444 kb
Host smart-861e2664-3a6a-43f1-8fb8-e5f4653c0f1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191009519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1191009519
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2094272648
Short name T434
Test name
Test status
Simulation time 60941999354 ps
CPU time 187.24 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:57:57 PM PDT 24
Peak memory 200708 kb
Host smart-76b85bea-449c-4caa-93c3-40f3d8ded7cd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094272648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2094272648
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4278307127
Short name T479
Test name
Test status
Simulation time 401261366 ps
CPU time 22.52 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200616 kb
Host smart-76f41e5c-edd7-453b-8615-015ec2bb0ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278307127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4278307127
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.898352787
Short name T472
Test name
Test status
Simulation time 7309920689 ps
CPU time 9.31 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:54:58 PM PDT 24
Peak memory 200740 kb
Host smart-3cfe4049-76e0-4f3e-b04c-efe589a2dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898352787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.898352787
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2070822179
Short name T305
Test name
Test status
Simulation time 40228523980 ps
CPU time 478.61 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 06:02:51 PM PDT 24
Peak memory 655772 kb
Host smart-0080bfa4-d844-4a93-92d1-54e62857bc24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070822179 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2070822179
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3172207079
Short name T243
Test name
Test status
Simulation time 851399281 ps
CPU time 3.06 seconds
Started Aug 17 05:54:48 PM PDT 24
Finished Aug 17 05:54:51 PM PDT 24
Peak memory 200644 kb
Host smart-b7de2872-acaf-4992-b2d8-5c0f1430099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172207079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3172207079
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.228317675
Short name T438
Test name
Test status
Simulation time 12636663 ps
CPU time 0.54 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:54:59 PM PDT 24
Peak memory 195732 kb
Host smart-a82ec1d3-2c4d-4dca-ba20-3c0f0e76b818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228317675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.228317675
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2516192130
Short name T197
Test name
Test status
Simulation time 1565124746 ps
CPU time 95.39 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:56:27 PM PDT 24
Peak memory 200672 kb
Host smart-3f000e9e-ae5a-4856-86d4-f573e5704f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516192130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2516192130
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1684891507
Short name T62
Test name
Test status
Simulation time 278628049 ps
CPU time 2.71 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:54:55 PM PDT 24
Peak memory 200648 kb
Host smart-f23b83ef-4116-444a-a74f-ab4c4ff7079c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684891507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1684891507
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3932988167
Short name T31
Test name
Test status
Simulation time 802489040 ps
CPU time 37.69 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:55:32 PM PDT 24
Peak memory 309452 kb
Host smart-72cb0b31-7e9f-4240-b29d-6117432665da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932988167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3932988167
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1185082694
Short name T482
Test name
Test status
Simulation time 1670698575 ps
CPU time 96.01 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 200676 kb
Host smart-1f6fd525-64f8-4ce5-8e11-2cb6c0af966c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185082694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1185082694
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.44451754
Short name T156
Test name
Test status
Simulation time 650935856 ps
CPU time 8.66 seconds
Started Aug 17 05:54:44 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 200684 kb
Host smart-68064ae0-836f-4625-a685-479674a260e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44451754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.44451754
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3703410672
Short name T335
Test name
Test status
Simulation time 949806251 ps
CPU time 5.89 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:01 PM PDT 24
Peak memory 200676 kb
Host smart-c023a710-b0bb-4791-ab6e-971160116836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703410672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3703410672
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2137646314
Short name T85
Test name
Test status
Simulation time 194724699983 ps
CPU time 1013.64 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 06:11:52 PM PDT 24
Peak memory 715780 kb
Host smart-42d0e75a-7e0f-405e-8e9c-4c24bb2323d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137646314 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2137646314
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2958105466
Short name T501
Test name
Test status
Simulation time 18175843322 ps
CPU time 93.14 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:56:32 PM PDT 24
Peak memory 200820 kb
Host smart-984ed3a8-79e8-432e-a3a6-f062dd609bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958105466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2958105466
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4007715462
Short name T257
Test name
Test status
Simulation time 68141237 ps
CPU time 0.57 seconds
Started Aug 17 05:54:49 PM PDT 24
Finished Aug 17 05:54:49 PM PDT 24
Peak memory 196372 kb
Host smart-55798074-39b4-44af-984f-64c0c201d2ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007715462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4007715462
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2925421832
Short name T216
Test name
Test status
Simulation time 868044989 ps
CPU time 50.23 seconds
Started Aug 17 05:54:48 PM PDT 24
Finished Aug 17 05:55:38 PM PDT 24
Peak memory 200652 kb
Host smart-18d2825d-f65c-412f-9b3c-6d6f4837f925
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925421832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2925421832
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3672638957
Short name T367
Test name
Test status
Simulation time 287972748 ps
CPU time 14.97 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200548 kb
Host smart-7faef1fa-e9b2-4335-b973-ddc3dc56134c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672638957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3672638957
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2640977039
Short name T504
Test name
Test status
Simulation time 5861897876 ps
CPU time 1120.18 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 06:13:34 PM PDT 24
Peak memory 768372 kb
Host smart-e05b743c-4a59-4442-a7a1-b65bb84321e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2640977039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2640977039
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2597780100
Short name T397
Test name
Test status
Simulation time 12563416981 ps
CPU time 182.75 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:57:58 PM PDT 24
Peak memory 200748 kb
Host smart-4520e5dd-bce9-49b5-99f1-dbe15ab93dab
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597780100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2597780100
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2986313826
Short name T60
Test name
Test status
Simulation time 2004182570 ps
CPU time 32.62 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:55:24 PM PDT 24
Peak memory 200684 kb
Host smart-6bd47439-7ced-4efd-b898-f33d6002b99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986313826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2986313826
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3907138932
Short name T38
Test name
Test status
Simulation time 886271129 ps
CPU time 12.12 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:55:05 PM PDT 24
Peak memory 200640 kb
Host smart-25967ed3-7ffc-42f8-814e-e99236536c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907138932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3907138932
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4197242829
Short name T15
Test name
Test status
Simulation time 71942655533 ps
CPU time 1397.64 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 06:18:17 PM PDT 24
Peak memory 217068 kb
Host smart-6defe533-0061-4d0c-90e2-e6a205e863d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197242829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4197242829
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2375910945
Short name T192
Test name
Test status
Simulation time 5546198384 ps
CPU time 104.87 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:56:44 PM PDT 24
Peak memory 200776 kb
Host smart-179e6a2a-5517-432a-8b3a-c61d3bd5a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375910945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2375910945
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1098075983
Short name T447
Test name
Test status
Simulation time 35618481 ps
CPU time 0.6 seconds
Started Aug 17 05:55:03 PM PDT 24
Finished Aug 17 05:55:04 PM PDT 24
Peak memory 196508 kb
Host smart-80078437-df4f-4f1e-8af3-df82132188c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098075983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1098075983
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1388810335
Short name T334
Test name
Test status
Simulation time 2389093505 ps
CPU time 77.89 seconds
Started Aug 17 05:54:56 PM PDT 24
Finished Aug 17 05:56:14 PM PDT 24
Peak memory 200800 kb
Host smart-96aecfc8-f7a8-4c1c-a107-1ed79ece5744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388810335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1388810335
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.786844031
Short name T48
Test name
Test status
Simulation time 2409670994 ps
CPU time 33.33 seconds
Started Aug 17 05:54:47 PM PDT 24
Finished Aug 17 05:55:20 PM PDT 24
Peak memory 200692 kb
Host smart-ddf2d6ac-3d24-45c3-92db-998117f59327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786844031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.786844031
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.769394427
Short name T238
Test name
Test status
Simulation time 23924214576 ps
CPU time 1054.98 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 06:12:28 PM PDT 24
Peak memory 733544 kb
Host smart-4d589163-c2a6-4fec-9d4a-76c5bebe3fda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769394427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.769394427
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1958937041
Short name T390
Test name
Test status
Simulation time 33243197770 ps
CPU time 211.67 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:58:23 PM PDT 24
Peak memory 200684 kb
Host smart-7ec28d13-4a6e-4bb6-bc33-33b0482df734
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958937041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1958937041
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3092134997
Short name T469
Test name
Test status
Simulation time 9978042050 ps
CPU time 180 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:57:53 PM PDT 24
Peak memory 200640 kb
Host smart-4aa837da-1877-49c3-ae01-e45ac2fd5b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092134997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3092134997
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3007069116
Short name T420
Test name
Test status
Simulation time 842612662 ps
CPU time 9.59 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:09 PM PDT 24
Peak memory 200664 kb
Host smart-3b85671a-13c9-4f8b-9bc2-d715671f301b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007069116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3007069116
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.233610771
Short name T478
Test name
Test status
Simulation time 26650430598 ps
CPU time 373.22 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 06:01:08 PM PDT 24
Peak memory 200728 kb
Host smart-8fa79f11-9bdd-4663-aacc-36c771f2de39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233610771 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.233610771
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2662299463
Short name T94
Test name
Test status
Simulation time 7377141097 ps
CPU time 95.81 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 200764 kb
Host smart-689b1f9c-923c-4d6d-918f-b1b18e647bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662299463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2662299463
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3044502097
Short name T373
Test name
Test status
Simulation time 13875821 ps
CPU time 0.58 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 196656 kb
Host smart-7a6d2023-9774-469e-a5b3-7c47e60be249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044502097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3044502097
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.652732952
Short name T394
Test name
Test status
Simulation time 3027230378 ps
CPU time 87.45 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:56:22 PM PDT 24
Peak memory 200752 kb
Host smart-49bfdbb0-d7e9-42e6-abf5-2cf50f9e3452
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=652732952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.652732952
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2897837428
Short name T400
Test name
Test status
Simulation time 12386777604 ps
CPU time 1289.92 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 06:16:25 PM PDT 24
Peak memory 718156 kb
Host smart-f82a1424-9c1b-40d9-9825-bb72fadf2ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897837428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2897837428
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1056603208
Short name T311
Test name
Test status
Simulation time 3094254776 ps
CPU time 54.6 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:55:55 PM PDT 24
Peak memory 200616 kb
Host smart-4b87ef84-1a38-48a3-8da8-21f5063effdd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056603208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1056603208
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3934993518
Short name T365
Test name
Test status
Simulation time 15883953599 ps
CPU time 52.73 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:52 PM PDT 24
Peak memory 200788 kb
Host smart-4f796728-03a4-4b08-b330-0949b0e9da18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934993518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3934993518
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3023458196
Short name T298
Test name
Test status
Simulation time 1119826721 ps
CPU time 10.53 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:55:03 PM PDT 24
Peak memory 200580 kb
Host smart-96b62dbe-2e40-4a29-a1d8-4877b3e79ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023458196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3023458196
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2720047253
Short name T70
Test name
Test status
Simulation time 39944672306 ps
CPU time 807.43 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 06:08:23 PM PDT 24
Peak memory 618628 kb
Host smart-2aa57045-01ee-4735-a2c7-07bdb9ecce58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720047253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2720047253
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2311323523
Short name T266
Test name
Test status
Simulation time 5320510050 ps
CPU time 94.36 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:56:33 PM PDT 24
Peak memory 200720 kb
Host smart-35d2572d-195b-46e1-81af-974a9129e8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311323523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2311323523
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2955287323
Short name T228
Test name
Test status
Simulation time 14618307 ps
CPU time 0.59 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:54:55 PM PDT 24
Peak memory 197396 kb
Host smart-bf5daa82-9630-466c-b435-564db9fecec1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955287323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2955287323
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3372367386
Short name T310
Test name
Test status
Simulation time 355934629 ps
CPU time 10.86 seconds
Started Aug 17 05:55:02 PM PDT 24
Finished Aug 17 05:55:13 PM PDT 24
Peak memory 200640 kb
Host smart-65c47e46-5cba-4ad9-8a6b-2889f2b3eb62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3372367386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3372367386
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1923011304
Short name T519
Test name
Test status
Simulation time 2698736715 ps
CPU time 34.94 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:55:32 PM PDT 24
Peak memory 200672 kb
Host smart-dcc13fe7-9d6d-4ff7-aba5-a1e6f3b290e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923011304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1923011304
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4089127089
Short name T361
Test name
Test status
Simulation time 3745722047 ps
CPU time 661.95 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 06:06:03 PM PDT 24
Peak memory 686652 kb
Host smart-68549d0f-1f65-4e88-9fb0-a5d367051a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089127089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4089127089
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3993215291
Short name T200
Test name
Test status
Simulation time 112996186156 ps
CPU time 139.39 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:57:14 PM PDT 24
Peak memory 200760 kb
Host smart-34a96383-0a92-4daa-95ff-079f510dfdb3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993215291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3993215291
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1377375850
Short name T337
Test name
Test status
Simulation time 10172969495 ps
CPU time 147.01 seconds
Started Aug 17 05:54:50 PM PDT 24
Finished Aug 17 05:57:17 PM PDT 24
Peak memory 200808 kb
Host smart-f9212d2c-b406-4284-888c-ba53b2420dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377375850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1377375850
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.327587834
Short name T37
Test name
Test status
Simulation time 1091034543 ps
CPU time 12.88 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:12 PM PDT 24
Peak memory 200608 kb
Host smart-5db3808f-3d87-4415-8b35-d13006c5205b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327587834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.327587834
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.174727807
Short name T95
Test name
Test status
Simulation time 89017781948 ps
CPU time 3519.64 seconds
Started Aug 17 05:55:03 PM PDT 24
Finished Aug 17 06:53:43 PM PDT 24
Peak memory 800196 kb
Host smart-e21eaf80-7768-4a7f-808f-a8ad30102884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174727807 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.174727807
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3042720217
Short name T315
Test name
Test status
Simulation time 584371628 ps
CPU time 14.21 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200688 kb
Host smart-f9edb306-9ed9-4791-a0ca-a6f006429f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042720217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3042720217
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2263858770
Short name T333
Test name
Test status
Simulation time 76556453 ps
CPU time 0.56 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:54:56 PM PDT 24
Peak memory 196712 kb
Host smart-eaf3b539-e224-483c-b1a5-2c46a29395ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263858770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2263858770
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.775967887
Short name T439
Test name
Test status
Simulation time 3174160539 ps
CPU time 43.96 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:40 PM PDT 24
Peak memory 200692 kb
Host smart-64dd655e-09b4-4e9b-b58b-6e2733c3faf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775967887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.775967887
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2310363672
Short name T513
Test name
Test status
Simulation time 3649889743 ps
CPU time 13.8 seconds
Started Aug 17 05:55:06 PM PDT 24
Finished Aug 17 05:55:19 PM PDT 24
Peak memory 208904 kb
Host smart-fbbc88ef-6a76-4339-8888-6b530e52ca95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310363672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2310363672
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1465151290
Short name T392
Test name
Test status
Simulation time 6007293973 ps
CPU time 617.88 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 06:05:17 PM PDT 24
Peak memory 708120 kb
Host smart-c7cb99dc-122c-4a48-b2cd-9369d38313a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1465151290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1465151290
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.4060625460
Short name T487
Test name
Test status
Simulation time 9630704786 ps
CPU time 83.24 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:56:28 PM PDT 24
Peak memory 200644 kb
Host smart-13fe1719-ca71-445a-8e3b-1f2a4759aee4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060625460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.4060625460
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.356220116
Short name T237
Test name
Test status
Simulation time 1923126375 ps
CPU time 123.99 seconds
Started Aug 17 05:54:51 PM PDT 24
Finished Aug 17 05:56:55 PM PDT 24
Peak memory 200572 kb
Host smart-def51031-3057-4fd4-9160-eb87150e6198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356220116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.356220116
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1700228533
Short name T218
Test name
Test status
Simulation time 271651861 ps
CPU time 12.43 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:08 PM PDT 24
Peak memory 200644 kb
Host smart-1536a32c-af6e-4224-a485-10ff8e0c8423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700228533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1700228533
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3751280071
Short name T281
Test name
Test status
Simulation time 448968137911 ps
CPU time 430.69 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 06:02:06 PM PDT 24
Peak memory 200744 kb
Host smart-68f81876-fe94-4c28-8542-bc62ef9c82dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751280071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3751280071
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1564919744
Short name T145
Test name
Test status
Simulation time 6299124188 ps
CPU time 31.11 seconds
Started Aug 17 05:55:03 PM PDT 24
Finished Aug 17 05:55:34 PM PDT 24
Peak memory 200652 kb
Host smart-c29e0c72-ab98-4f37-8421-16bee5c3bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564919744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1564919744
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2371276029
Short name T456
Test name
Test status
Simulation time 37255934 ps
CPU time 0.59 seconds
Started Aug 17 05:54:28 PM PDT 24
Finished Aug 17 05:54:28 PM PDT 24
Peak memory 196684 kb
Host smart-92dfacbf-2f59-493a-8799-1fd4d3ed0948
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371276029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2371276029
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3548270933
Short name T198
Test name
Test status
Simulation time 1326593756 ps
CPU time 18.76 seconds
Started Aug 17 05:54:16 PM PDT 24
Finished Aug 17 05:54:34 PM PDT 24
Peak memory 200564 kb
Host smart-f7a7116d-89b0-4556-8ba4-355cca3251e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3548270933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3548270933
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3951264027
Short name T41
Test name
Test status
Simulation time 2544230146 ps
CPU time 45.61 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 05:55:12 PM PDT 24
Peak memory 200744 kb
Host smart-4cc38477-81de-4776-9293-691c8e46ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951264027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3951264027
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.391649416
Short name T424
Test name
Test status
Simulation time 3312658904 ps
CPU time 621.5 seconds
Started Aug 17 05:54:15 PM PDT 24
Finished Aug 17 06:04:36 PM PDT 24
Peak memory 683176 kb
Host smart-1aea5d5c-02cc-4d5f-9ef4-8a19d94a6a0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391649416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.391649416
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1352730631
Short name T199
Test name
Test status
Simulation time 612534194 ps
CPU time 30.21 seconds
Started Aug 17 05:54:22 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 200652 kb
Host smart-584e1549-52a8-44e7-a782-e6a06f5e4a51
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352730631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1352730631
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.849695016
Short name T282
Test name
Test status
Simulation time 2818101736 ps
CPU time 10.25 seconds
Started Aug 17 05:54:18 PM PDT 24
Finished Aug 17 05:54:28 PM PDT 24
Peak memory 200684 kb
Host smart-d1ae3b01-e3ea-43a6-9300-9fe5fbcc6571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849695016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.849695016
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.2252056939
Short name T244
Test name
Test status
Simulation time 606978371 ps
CPU time 8.51 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:54:40 PM PDT 24
Peak memory 200684 kb
Host smart-d6c5430d-2de4-47e0-a46e-de4c6a918d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252056939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2252056939
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.318383352
Short name T500
Test name
Test status
Simulation time 4037539147 ps
CPU time 208.58 seconds
Started Aug 17 05:54:20 PM PDT 24
Finished Aug 17 05:57:48 PM PDT 24
Peak memory 200924 kb
Host smart-01b376ed-1f70-44a6-b818-c583cec844e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318383352 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.318383352
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3807944983
Short name T485
Test name
Test status
Simulation time 4391778177 ps
CPU time 41.56 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200780 kb
Host smart-b148b7e8-8432-4d31-ba79-6a789773bd2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3807944983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3807944983
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3349178116
Short name T170
Test name
Test status
Simulation time 4427550963 ps
CPU time 62.94 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 05:55:30 PM PDT 24
Peak memory 200816 kb
Host smart-00306563-5171-4479-9f70-3d830aae9db6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3349178116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3349178116
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.3805294735
Short name T161
Test name
Test status
Simulation time 15196668220 ps
CPU time 126.37 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:56:36 PM PDT 24
Peak memory 200756 kb
Host smart-284322c5-96df-4c28-9456-3c41fa3fbbc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3805294735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.3805294735
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1435056313
Short name T22
Test name
Test status
Simulation time 39763314253 ps
CPU time 486.86 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 06:02:30 PM PDT 24
Peak memory 200616 kb
Host smart-b6dfcdfa-8c15-49bd-a86f-790eed5b400e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1435056313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1435056313
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.482748468
Short name T353
Test name
Test status
Simulation time 448312522853 ps
CPU time 2044.73 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 06:28:36 PM PDT 24
Peak memory 216336 kb
Host smart-d20189c3-3c59-4a2a-8165-a261e8b9a6ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=482748468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.482748468
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.97456527
Short name T338
Test name
Test status
Simulation time 142351668021 ps
CPU time 2352.31 seconds
Started Aug 17 05:54:24 PM PDT 24
Finished Aug 17 06:33:37 PM PDT 24
Peak memory 216412 kb
Host smart-abf69b4c-5377-48f1-99c0-ff2f195a111d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=97456527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.97456527
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2398023900
Short name T123
Test name
Test status
Simulation time 10093438065 ps
CPU time 112.05 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:56:23 PM PDT 24
Peak memory 200612 kb
Host smart-7a76c86a-849f-4498-9ed3-b01836ec5d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398023900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2398023900
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.568177425
Short name T357
Test name
Test status
Simulation time 23766624 ps
CPU time 0.56 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:54:59 PM PDT 24
Peak memory 196336 kb
Host smart-81eb92fb-3100-469c-a88f-9ce1c4c21bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568177425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.568177425
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.921936034
Short name T227
Test name
Test status
Simulation time 1015626409 ps
CPU time 58.15 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:56:02 PM PDT 24
Peak memory 200584 kb
Host smart-a4769619-6df8-4506-bf6c-d9a2b0b0950b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=921936034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.921936034
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1206031960
Short name T174
Test name
Test status
Simulation time 7035514521 ps
CPU time 50.68 seconds
Started Aug 17 05:54:53 PM PDT 24
Finished Aug 17 05:55:44 PM PDT 24
Peak memory 200872 kb
Host smart-f9c779d1-74a3-4d10-9b56-285a0edb0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206031960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1206031960
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.971538848
Short name T403
Test name
Test status
Simulation time 10160947974 ps
CPU time 406.47 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 06:01:41 PM PDT 24
Peak memory 676380 kb
Host smart-23cc72dc-9538-4563-ab4d-8924890fa14c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971538848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.971538848
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.206319654
Short name T302
Test name
Test status
Simulation time 6905856791 ps
CPU time 89.3 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:56:30 PM PDT 24
Peak memory 200736 kb
Host smart-bb7d2924-5ee9-4171-b8a2-455a89cab1f9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206319654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.206319654
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.4119560332
Short name T343
Test name
Test status
Simulation time 15084286279 ps
CPU time 32.18 seconds
Started Aug 17 05:55:02 PM PDT 24
Finished Aug 17 05:55:35 PM PDT 24
Peak memory 200752 kb
Host smart-60aca37c-22f1-4b8e-bec7-f7916d1304d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119560332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.4119560332
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2139931144
Short name T490
Test name
Test status
Simulation time 684349310 ps
CPU time 7.61 seconds
Started Aug 17 05:54:54 PM PDT 24
Finished Aug 17 05:55:01 PM PDT 24
Peak memory 200564 kb
Host smart-86db1d2a-89e2-445e-89be-0e85ebcffae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139931144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2139931144
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2292304729
Short name T30
Test name
Test status
Simulation time 64604302122 ps
CPU time 1964.08 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 06:27:50 PM PDT 24
Peak memory 750124 kb
Host smart-7553125d-65cc-49b7-8ab8-46daaea1b5ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292304729 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2292304729
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3102698151
Short name T259
Test name
Test status
Simulation time 22958390909 ps
CPU time 118.46 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 05:57:04 PM PDT 24
Peak memory 200644 kb
Host smart-cd4f50b3-d1c7-41ce-baa6-7e1015c69800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102698151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3102698151
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3075786184
Short name T209
Test name
Test status
Simulation time 15662813 ps
CPU time 0.59 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:01 PM PDT 24
Peak memory 197408 kb
Host smart-c0b508cf-2f47-4e0f-a98f-463741f5e013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075786184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3075786184
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1317096506
Short name T25
Test name
Test status
Simulation time 314745635 ps
CPU time 16.66 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:55:21 PM PDT 24
Peak memory 200588 kb
Host smart-e9192435-a083-43ac-a533-bc6ab0e3b5ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317096506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1317096506
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1676779436
Short name T329
Test name
Test status
Simulation time 1579923316 ps
CPU time 21.16 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:22 PM PDT 24
Peak memory 200716 kb
Host smart-c17a4dca-94f3-4d0b-bd60-629dd6f8d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676779436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1676779436
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1021730235
Short name T418
Test name
Test status
Simulation time 1508925158 ps
CPU time 281.94 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 05:59:47 PM PDT 24
Peak memory 633080 kb
Host smart-947e8a16-2534-4fe2-bd1a-2de09eae4b1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021730235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1021730235
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.1389679565
Short name T283
Test name
Test status
Simulation time 9487431150 ps
CPU time 256.58 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:59:17 PM PDT 24
Peak memory 200708 kb
Host smart-0205a053-d734-42bd-b195-146ad33cbc8c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389679565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1389679565
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.940439815
Short name T433
Test name
Test status
Simulation time 1222740951 ps
CPU time 74.5 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 200724 kb
Host smart-42041c64-54d5-4b7c-b4b9-1daa80e229aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940439815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.940439815
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3117233520
Short name T241
Test name
Test status
Simulation time 1603673433 ps
CPU time 14.28 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:10 PM PDT 24
Peak memory 200676 kb
Host smart-7b45eb1b-a406-4b7d-a58e-d299ed677d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117233520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3117233520
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.402040707
Short name T229
Test name
Test status
Simulation time 26178708 ps
CPU time 0.65 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:54:58 PM PDT 24
Peak memory 196436 kb
Host smart-414387e9-d50f-42ba-9f66-627b2eea182c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402040707 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.402040707
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2134641980
Short name T376
Test name
Test status
Simulation time 3579694188 ps
CPU time 62.45 seconds
Started Aug 17 05:54:55 PM PDT 24
Finished Aug 17 05:55:58 PM PDT 24
Peak memory 200684 kb
Host smart-0079abc8-c7e2-44ce-b05d-9efd12904de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134641980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2134641980
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2657082087
Short name T16
Test name
Test status
Simulation time 46838552 ps
CPU time 0.6 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:00 PM PDT 24
Peak memory 196740 kb
Host smart-5e651601-60ae-4be3-b2aa-aba450ed57fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657082087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2657082087
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2754439510
Short name T325
Test name
Test status
Simulation time 492722062 ps
CPU time 14.93 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 05:55:12 PM PDT 24
Peak memory 200648 kb
Host smart-f043fe40-a942-449d-9202-27dd151b552f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754439510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2754439510
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.840667299
Short name T414
Test name
Test status
Simulation time 1458661027 ps
CPU time 19.23 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:19 PM PDT 24
Peak memory 200688 kb
Host smart-8a38c45d-1172-4ec5-89d3-bfac30904248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840667299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.840667299
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4160848338
Short name T313
Test name
Test status
Simulation time 756299743 ps
CPU time 74.04 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:56:15 PM PDT 24
Peak memory 408760 kb
Host smart-f403a1ea-056b-45d6-88dd-4bf594333d42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160848338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4160848338
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.80120907
Short name T293
Test name
Test status
Simulation time 53897815067 ps
CPU time 189.85 seconds
Started Aug 17 05:55:02 PM PDT 24
Finished Aug 17 05:58:12 PM PDT 24
Peak memory 200724 kb
Host smart-0cc68b09-fda0-41e6-95da-508379773d81
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80120907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.80120907
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2159675793
Short name T61
Test name
Test status
Simulation time 181758239 ps
CPU time 10.88 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:11 PM PDT 24
Peak memory 200680 kb
Host smart-9d05f7b8-6607-4835-a023-4eb6987c435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159675793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2159675793
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2175138118
Short name T491
Test name
Test status
Simulation time 252236773 ps
CPU time 4.68 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:04 PM PDT 24
Peak memory 200672 kb
Host smart-369bd150-3384-4caa-9969-69c91c994b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175138118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2175138118
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2472895715
Short name T489
Test name
Test status
Simulation time 40333869244 ps
CPU time 2911.89 seconds
Started Aug 17 05:54:57 PM PDT 24
Finished Aug 17 06:43:29 PM PDT 24
Peak memory 812436 kb
Host smart-a9dc0e7e-e5a6-4f14-b341-97a41a1aed51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472895715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2472895715
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1821017570
Short name T205
Test name
Test status
Simulation time 941982423 ps
CPU time 50.37 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:55:49 PM PDT 24
Peak memory 200676 kb
Host smart-94dabc48-ba95-4b78-88c9-d725c5111c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821017570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1821017570
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1432381723
Short name T270
Test name
Test status
Simulation time 42167452 ps
CPU time 0.61 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:00 PM PDT 24
Peak memory 196736 kb
Host smart-85b44c7a-c231-46dd-86e4-b3f9a3cefbe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432381723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1432381723
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.201615721
Short name T502
Test name
Test status
Simulation time 1291358146 ps
CPU time 51.66 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:55:56 PM PDT 24
Peak memory 200672 kb
Host smart-4c43d76b-3f6e-4730-926a-7dcd12b2542c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=201615721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.201615721
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2481590369
Short name T533
Test name
Test status
Simulation time 22224471982 ps
CPU time 75.43 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:56:19 PM PDT 24
Peak memory 200736 kb
Host smart-16676969-0ce3-4fe8-a515-11ba6f92c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481590369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2481590369
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2359741580
Short name T362
Test name
Test status
Simulation time 15732344 ps
CPU time 0.78 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:55:02 PM PDT 24
Peak memory 198956 kb
Host smart-6abfdeca-dba2-4a00-9299-c5941deb7853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359741580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2359741580
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2684789970
Short name T1
Test name
Test status
Simulation time 3247540423 ps
CPU time 81.33 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 05:56:26 PM PDT 24
Peak memory 200592 kb
Host smart-9881235c-9b0a-4e56-8e8c-acd274ec256c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684789970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2684789970
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3934575841
Short name T167
Test name
Test status
Simulation time 4626724762 ps
CPU time 70.72 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 200744 kb
Host smart-03de8218-d26e-49d2-9c39-0c6ce72ca3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934575841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3934575841
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3511540022
Short name T474
Test name
Test status
Simulation time 943792736 ps
CPU time 3.61 seconds
Started Aug 17 05:54:59 PM PDT 24
Finished Aug 17 05:55:03 PM PDT 24
Peak memory 200672 kb
Host smart-449c4cc5-24bd-43eb-939c-da0d7f6036d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511540022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3511540022
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1797890450
Short name T2
Test name
Test status
Simulation time 20866410781 ps
CPU time 749.31 seconds
Started Aug 17 05:55:02 PM PDT 24
Finished Aug 17 06:07:32 PM PDT 24
Peak memory 637492 kb
Host smart-78517846-f523-4016-96af-68a775a4be99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797890450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1797890450
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1570039867
Short name T178
Test name
Test status
Simulation time 6066279570 ps
CPU time 42.23 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:55:41 PM PDT 24
Peak memory 200628 kb
Host smart-f38a553c-5d7b-465e-81bc-39ae22ecfe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570039867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1570039867
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2768486185
Short name T17
Test name
Test status
Simulation time 30132531 ps
CPU time 0.61 seconds
Started Aug 17 05:54:52 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 197412 kb
Host smart-a9d331f6-f091-462d-b7d4-22a475ee85d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768486185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2768486185
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.294085143
Short name T77
Test name
Test status
Simulation time 282693367 ps
CPU time 15.68 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200672 kb
Host smart-16ec1c42-4395-4a17-9689-91e113081030
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294085143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.294085143
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2769139914
Short name T324
Test name
Test status
Simulation time 1617078066 ps
CPU time 29.92 seconds
Started Aug 17 05:55:02 PM PDT 24
Finished Aug 17 05:55:32 PM PDT 24
Peak memory 200692 kb
Host smart-017151a9-ee00-474f-b2aa-d9e92fb1d54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769139914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2769139914
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4091840126
Short name T188
Test name
Test status
Simulation time 18393309206 ps
CPU time 1180.12 seconds
Started Aug 17 05:55:03 PM PDT 24
Finished Aug 17 06:14:43 PM PDT 24
Peak memory 723188 kb
Host smart-58cf061b-2290-4698-81d4-f62b9f45b281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091840126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4091840126
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2487752712
Short name T247
Test name
Test status
Simulation time 48335730884 ps
CPU time 210.77 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:58:35 PM PDT 24
Peak memory 200676 kb
Host smart-19bd97ca-b202-478f-b435-cbcb08b41f4e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487752712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2487752712
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.904185712
Short name T51
Test name
Test status
Simulation time 12668553726 ps
CPU time 117.46 seconds
Started Aug 17 05:55:06 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 217024 kb
Host smart-a9d74961-3c44-45f8-80be-1da7a10320ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904185712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.904185712
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2678629214
Short name T159
Test name
Test status
Simulation time 3392035869 ps
CPU time 10.11 seconds
Started Aug 17 05:54:58 PM PDT 24
Finished Aug 17 05:55:08 PM PDT 24
Peak memory 200644 kb
Host smart-39f9817d-d6ed-48ca-a01d-6818c0a4ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678629214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2678629214
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.489505799
Short name T182
Test name
Test status
Simulation time 64512958687 ps
CPU time 2237.13 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 06:32:23 PM PDT 24
Peak memory 750136 kb
Host smart-3730707b-8158-491a-8e4c-269b8bd4cb54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489505799 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.489505799
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2987296379
Short name T463
Test name
Test status
Simulation time 1607862231 ps
CPU time 80.4 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 05:56:24 PM PDT 24
Peak memory 200672 kb
Host smart-f6f0a9fd-52d5-4ea8-a2ff-a5ec0165ebdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987296379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2987296379
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.507499606
Short name T154
Test name
Test status
Simulation time 23652886 ps
CPU time 0.62 seconds
Started Aug 17 05:55:06 PM PDT 24
Finished Aug 17 05:55:07 PM PDT 24
Peak memory 197412 kb
Host smart-54015025-d278-40b6-a7d2-4b785c443bbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507499606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.507499606
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.883543769
Short name T220
Test name
Test status
Simulation time 5384178414 ps
CPU time 76.05 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:56:16 PM PDT 24
Peak memory 200732 kb
Host smart-7c432960-6caf-406a-8cac-572fe451e36c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=883543769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.883543769
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.193079369
Short name T299
Test name
Test status
Simulation time 1132215923 ps
CPU time 31.38 seconds
Started Aug 17 05:55:08 PM PDT 24
Finished Aug 17 05:55:40 PM PDT 24
Peak memory 200672 kb
Host smart-6603e290-b247-4e28-86cd-f9a240975780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193079369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.193079369
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2122020525
Short name T185
Test name
Test status
Simulation time 8980699786 ps
CPU time 847.41 seconds
Started Aug 17 05:55:04 PM PDT 24
Finished Aug 17 06:09:11 PM PDT 24
Peak memory 675544 kb
Host smart-af81eeb7-b7c5-4d91-ae19-b9c2555538d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2122020525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2122020525
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.589913692
Short name T494
Test name
Test status
Simulation time 4384002567 ps
CPU time 124.39 seconds
Started Aug 17 05:55:09 PM PDT 24
Finished Aug 17 05:57:14 PM PDT 24
Peak memory 200716 kb
Host smart-470f6916-efdd-44ed-aa29-2bc0668a4035
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589913692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.589913692
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1357331182
Short name T172
Test name
Test status
Simulation time 3181322251 ps
CPU time 143.46 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:57:25 PM PDT 24
Peak memory 200740 kb
Host smart-ad12b9fd-da83-457d-9d41-3d5287dc26b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357331182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1357331182
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1508768376
Short name T386
Test name
Test status
Simulation time 175248971 ps
CPU time 1.73 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:02 PM PDT 24
Peak memory 200580 kb
Host smart-b53ff6e7-1945-481f-9c6e-f3ae5f71d039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508768376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1508768376
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1908940727
Short name T252
Test name
Test status
Simulation time 69846535165 ps
CPU time 1004.71 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 06:11:46 PM PDT 24
Peak memory 728640 kb
Host smart-71158d85-e2cb-4aea-b340-137a308012c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908940727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1908940727
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1806635731
Short name T210
Test name
Test status
Simulation time 2601457385 ps
CPU time 59.48 seconds
Started Aug 17 05:55:12 PM PDT 24
Finished Aug 17 05:56:11 PM PDT 24
Peak memory 200780 kb
Host smart-f87f86be-80a2-4bb7-84f4-6161ed848007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806635731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1806635731
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2377874885
Short name T271
Test name
Test status
Simulation time 42182700 ps
CPU time 0.59 seconds
Started Aug 17 05:55:08 PM PDT 24
Finished Aug 17 05:55:09 PM PDT 24
Peak memory 197428 kb
Host smart-84505607-1cc0-423c-99bc-de5372c72698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377874885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2377874885
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3212606704
Short name T374
Test name
Test status
Simulation time 1854019570 ps
CPU time 18.95 seconds
Started Aug 17 05:55:00 PM PDT 24
Finished Aug 17 05:55:19 PM PDT 24
Peak memory 200560 kb
Host smart-c039e96e-597b-4049-b522-ec191a674210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3212606704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3212606704
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.699487990
Short name T265
Test name
Test status
Simulation time 811329383 ps
CPU time 4.14 seconds
Started Aug 17 05:55:01 PM PDT 24
Finished Aug 17 05:55:05 PM PDT 24
Peak memory 200528 kb
Host smart-802bfff5-c87f-4998-b799-6901182ce49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699487990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.699487990
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3415745217
Short name T314
Test name
Test status
Simulation time 1709671578 ps
CPU time 272.28 seconds
Started Aug 17 05:55:05 PM PDT 24
Finished Aug 17 05:59:38 PM PDT 24
Peak memory 495376 kb
Host smart-0cc5c89b-f56a-48af-bd80-105c551198f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3415745217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3415745217
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.349898166
Short name T385
Test name
Test status
Simulation time 55883945792 ps
CPU time 172.02 seconds
Started Aug 17 05:55:09 PM PDT 24
Finished Aug 17 05:58:02 PM PDT 24
Peak memory 200724 kb
Host smart-c35ea58b-d815-45f9-90b5-de5a268c6101
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349898166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.349898166
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2539798138
Short name T149
Test name
Test status
Simulation time 7013817476 ps
CPU time 125.33 seconds
Started Aug 17 05:55:06 PM PDT 24
Finished Aug 17 05:57:12 PM PDT 24
Peak memory 200792 kb
Host smart-fae1a9cc-e658-4a38-a647-65a65e5865e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539798138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2539798138
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2070858929
Short name T139
Test name
Test status
Simulation time 42969533 ps
CPU time 1.89 seconds
Started Aug 17 05:55:10 PM PDT 24
Finished Aug 17 05:55:12 PM PDT 24
Peak memory 200640 kb
Host smart-ab599230-0323-42b1-a342-6e170d97bf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070858929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2070858929
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.629457707
Short name T191
Test name
Test status
Simulation time 4250834438 ps
CPU time 46.33 seconds
Started Aug 17 05:55:09 PM PDT 24
Finished Aug 17 05:55:55 PM PDT 24
Peak memory 200652 kb
Host smart-2c3380c9-9c98-4657-b7c8-8028dfe41bfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629457707 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.629457707
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.556010053
Short name T515
Test name
Test status
Simulation time 609174128 ps
CPU time 27.3 seconds
Started Aug 17 05:55:17 PM PDT 24
Finished Aug 17 05:55:44 PM PDT 24
Peak memory 200712 kb
Host smart-88395606-973c-4492-bc34-690513628ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556010053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.556010053
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3621870076
Short name T286
Test name
Test status
Simulation time 22338963 ps
CPU time 0.59 seconds
Started Aug 17 05:55:11 PM PDT 24
Finished Aug 17 05:55:12 PM PDT 24
Peak memory 196728 kb
Host smart-720138c0-f42a-4875-bf97-b08975670a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621870076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3621870076
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2530684036
Short name T169
Test name
Test status
Simulation time 1619570856 ps
CPU time 98.48 seconds
Started Aug 17 05:55:16 PM PDT 24
Finished Aug 17 05:56:55 PM PDT 24
Peak memory 200208 kb
Host smart-834a6853-0ba6-4c83-bceb-a2e83af4e445
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530684036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2530684036
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2184830710
Short name T297
Test name
Test status
Simulation time 3877270101 ps
CPU time 37.43 seconds
Started Aug 17 05:55:10 PM PDT 24
Finished Aug 17 05:55:47 PM PDT 24
Peak memory 200684 kb
Host smart-a00b5f82-03db-40dc-8b95-337c5238d470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184830710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2184830710
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.494155427
Short name T215
Test name
Test status
Simulation time 2769754366 ps
CPU time 159.89 seconds
Started Aug 17 05:55:16 PM PDT 24
Finished Aug 17 05:57:56 PM PDT 24
Peak memory 624312 kb
Host smart-327d6ffa-a664-4bac-82d2-ae5f778387d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494155427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.494155427
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3745226236
Short name T514
Test name
Test status
Simulation time 14785215448 ps
CPU time 177.74 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:58:15 PM PDT 24
Peak memory 200672 kb
Host smart-2f651e0a-10ad-4b29-8cf8-aa48224b7e52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745226236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3745226236
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3566590668
Short name T511
Test name
Test status
Simulation time 11982358677 ps
CPU time 58.62 seconds
Started Aug 17 05:55:08 PM PDT 24
Finished Aug 17 05:56:07 PM PDT 24
Peak memory 200736 kb
Host smart-116ee1de-427f-432e-ab29-2621c7ea1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566590668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3566590668
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1901898339
Short name T461
Test name
Test status
Simulation time 75394037 ps
CPU time 3.6 seconds
Started Aug 17 05:55:15 PM PDT 24
Finished Aug 17 05:55:19 PM PDT 24
Peak memory 200692 kb
Host smart-943d913b-c1b6-4a0f-9958-1116e051051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901898339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1901898339
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3220357718
Short name T273
Test name
Test status
Simulation time 870832195264 ps
CPU time 1373.22 seconds
Started Aug 17 05:55:09 PM PDT 24
Finished Aug 17 06:18:03 PM PDT 24
Peak memory 718984 kb
Host smart-92c5c42c-a875-4d45-957c-3f246b8526c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220357718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3220357718
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1579284766
Short name T383
Test name
Test status
Simulation time 20260903253 ps
CPU time 86.36 seconds
Started Aug 17 05:55:16 PM PDT 24
Finished Aug 17 05:56:42 PM PDT 24
Peak memory 200720 kb
Host smart-f77e7cf2-9562-457e-a2d2-1a5afc8639d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579284766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1579284766
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3022105761
Short name T54
Test name
Test status
Simulation time 12769398 ps
CPU time 0.6 seconds
Started Aug 17 05:55:21 PM PDT 24
Finished Aug 17 05:55:22 PM PDT 24
Peak memory 196272 kb
Host smart-65b96198-43ee-4635-9199-d0b25b7f0ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022105761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3022105761
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1014724264
Short name T292
Test name
Test status
Simulation time 8682377363 ps
CPU time 110.55 seconds
Started Aug 17 05:55:10 PM PDT 24
Finished Aug 17 05:57:00 PM PDT 24
Peak memory 200704 kb
Host smart-d48a62aa-a497-4a42-808c-a2589f658f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1014724264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1014724264
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3053345751
Short name T165
Test name
Test status
Simulation time 1898866178 ps
CPU time 33.65 seconds
Started Aug 17 05:55:08 PM PDT 24
Finished Aug 17 05:55:42 PM PDT 24
Peak memory 200672 kb
Host smart-298bfec4-1c75-411a-91c1-ab4830c6a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053345751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3053345751
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2955344977
Short name T453
Test name
Test status
Simulation time 5637617899 ps
CPU time 1004.19 seconds
Started Aug 17 05:55:16 PM PDT 24
Finished Aug 17 06:12:01 PM PDT 24
Peak memory 688208 kb
Host smart-d4915609-d449-472f-b1cc-5272412014a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955344977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2955344977
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1874627919
Short name T457
Test name
Test status
Simulation time 6446152100 ps
CPU time 88.16 seconds
Started Aug 17 05:55:13 PM PDT 24
Finished Aug 17 05:56:42 PM PDT 24
Peak memory 200792 kb
Host smart-cdf59857-d492-46c0-8d94-df9cdd1d48c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874627919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1874627919
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.521359698
Short name T529
Test name
Test status
Simulation time 2867181639 ps
CPU time 80.35 seconds
Started Aug 17 05:55:11 PM PDT 24
Finished Aug 17 05:56:31 PM PDT 24
Peak memory 200748 kb
Host smart-49f0ad8f-ebdf-46b7-a3aa-61ac5c4ccb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521359698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.521359698
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3701663172
Short name T211
Test name
Test status
Simulation time 6526653425 ps
CPU time 12.91 seconds
Started Aug 17 05:55:09 PM PDT 24
Finished Aug 17 05:55:22 PM PDT 24
Peak memory 200700 kb
Host smart-00bc5495-1e8f-418e-bb5c-405a9cf94757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701663172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3701663172
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1982150561
Short name T522
Test name
Test status
Simulation time 39760018102 ps
CPU time 2742.93 seconds
Started Aug 17 05:55:16 PM PDT 24
Finished Aug 17 06:40:59 PM PDT 24
Peak memory 771140 kb
Host smart-19367ed7-3e51-497a-a4cc-f06d1096c149
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982150561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1982150561
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2186754813
Short name T366
Test name
Test status
Simulation time 2102956870 ps
CPU time 81.26 seconds
Started Aug 17 05:55:07 PM PDT 24
Finished Aug 17 05:56:29 PM PDT 24
Peak memory 199144 kb
Host smart-e01ffc66-a3ba-4f35-a4c3-1309a8e5b2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186754813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2186754813
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.688707433
Short name T269
Test name
Test status
Simulation time 44188930 ps
CPU time 0.61 seconds
Started Aug 17 05:55:21 PM PDT 24
Finished Aug 17 05:55:22 PM PDT 24
Peak memory 196292 kb
Host smart-a4d8fbb0-1e40-4f7a-96dd-7c0f6af7fae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688707433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.688707433
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.564942980
Short name T261
Test name
Test status
Simulation time 227111522 ps
CPU time 13.66 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:55:31 PM PDT 24
Peak memory 200516 kb
Host smart-c11138de-d680-43d3-9e5f-d363e3dcbeda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564942980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.564942980
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.72280900
Short name T507
Test name
Test status
Simulation time 33113026258 ps
CPU time 44.86 seconds
Started Aug 17 05:55:19 PM PDT 24
Finished Aug 17 05:56:04 PM PDT 24
Peak memory 200680 kb
Host smart-f7d50fa9-9615-4541-b96a-ec4a264907b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72280900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.72280900
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1644193527
Short name T379
Test name
Test status
Simulation time 227211297 ps
CPU time 16.07 seconds
Started Aug 17 05:55:20 PM PDT 24
Finished Aug 17 05:55:36 PM PDT 24
Peak memory 228880 kb
Host smart-87f98a5b-1fb1-46bb-a915-5688eee55162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644193527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1644193527
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2711093922
Short name T391
Test name
Test status
Simulation time 3846889445 ps
CPU time 53.41 seconds
Started Aug 17 05:55:19 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 200712 kb
Host smart-ad63542d-a89c-4459-aadd-b560a4797801
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711093922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2711093922
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3139912479
Short name T393
Test name
Test status
Simulation time 7884283341 ps
CPU time 26.72 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:55:45 PM PDT 24
Peak memory 200652 kb
Host smart-88444c65-0e11-4b55-a8b4-a69fb9838164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139912479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3139912479
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.455904686
Short name T177
Test name
Test status
Simulation time 2339305770 ps
CPU time 9.32 seconds
Started Aug 17 05:55:20 PM PDT 24
Finished Aug 17 05:55:30 PM PDT 24
Peak memory 200772 kb
Host smart-2f9302be-2cdc-4eb1-b3f7-8229e1b6aea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455904686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.455904686
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.1334777521
Short name T268
Test name
Test status
Simulation time 13236004905 ps
CPU time 1548.02 seconds
Started Aug 17 05:55:19 PM PDT 24
Finished Aug 17 06:21:07 PM PDT 24
Peak memory 732360 kb
Host smart-b4a39d15-04c8-4e16-8830-18d30b2c89ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334777521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.1334777521
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1889227001
Short name T342
Test name
Test status
Simulation time 2633780389 ps
CPU time 52.44 seconds
Started Aug 17 05:55:20 PM PDT 24
Finished Aug 17 05:56:13 PM PDT 24
Peak memory 200648 kb
Host smart-f8455321-e208-4542-89d9-2e5691f53ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889227001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1889227001
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.323472717
Short name T236
Test name
Test status
Simulation time 13863299 ps
CPU time 0.58 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:54:30 PM PDT 24
Peak memory 196748 kb
Host smart-3eca372c-2655-49b9-9706-9958ea8e33be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323472717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.323472717
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1066543851
Short name T81
Test name
Test status
Simulation time 1150474917 ps
CPU time 10.55 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:54:41 PM PDT 24
Peak memory 200504 kb
Host smart-feb5b52b-32e6-41c7-b30a-a5fd60f2b3b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1066543851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1066543851
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1446438056
Short name T387
Test name
Test status
Simulation time 2211988764 ps
CPU time 31.57 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 05:54:55 PM PDT 24
Peak memory 200728 kb
Host smart-17f1da3c-97ec-480a-9a04-fccb5e2a734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446438056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1446438056
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3657787630
Short name T187
Test name
Test status
Simulation time 9103572262 ps
CPU time 816.98 seconds
Started Aug 17 05:54:24 PM PDT 24
Finished Aug 17 06:08:01 PM PDT 24
Peak memory 717308 kb
Host smart-c48da4e9-77e0-4b74-aa72-127133f2dc5d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3657787630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3657787630
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2584298643
Short name T195
Test name
Test status
Simulation time 2468637840 ps
CPU time 138.14 seconds
Started Aug 17 05:54:28 PM PDT 24
Finished Aug 17 05:56:47 PM PDT 24
Peak memory 200672 kb
Host smart-eff2d273-d2b3-423a-9b70-51f4366154b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584298643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2584298643
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2401657874
Short name T358
Test name
Test status
Simulation time 2698808225 ps
CPU time 159.68 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:57:12 PM PDT 24
Peak memory 200756 kb
Host smart-0a09f80d-9e67-4796-b974-cf5b3ddaaa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401657874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2401657874
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.4141527735
Short name T56
Test name
Test status
Simulation time 511341753 ps
CPU time 0.91 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:54:31 PM PDT 24
Peak memory 218908 kb
Host smart-cf105487-b959-4e13-8d0a-5431fa70efbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141527735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.4141527735
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.683941041
Short name T404
Test name
Test status
Simulation time 2620767693 ps
CPU time 9.28 seconds
Started Aug 17 05:54:44 PM PDT 24
Finished Aug 17 05:54:53 PM PDT 24
Peak memory 200608 kb
Host smart-d941efb2-76a8-45cc-aa78-41b1a603bfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683941041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.683941041
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1374164479
Short name T284
Test name
Test status
Simulation time 177640580822 ps
CPU time 4505.3 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 07:09:33 PM PDT 24
Peak memory 886444 kb
Host smart-614873d7-7776-4d32-8dbb-ec95ce2e91de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374164479 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1374164479
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2769781661
Short name T499
Test name
Test status
Simulation time 3570433299 ps
CPU time 72.12 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:55:44 PM PDT 24
Peak memory 200756 kb
Host smart-5c85f139-0ce7-4b43-9a08-96e7649dd088
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2769781661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2769781661
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.92599857
Short name T483
Test name
Test status
Simulation time 21874340050 ps
CPU time 80.22 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:55:51 PM PDT 24
Peak memory 200624 kb
Host smart-deaca295-2aa6-4707-ae60-1a320e6d2932
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=92599857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.92599857
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3032952145
Short name T336
Test name
Test status
Simulation time 7107825325 ps
CPU time 79.68 seconds
Started Aug 17 05:54:20 PM PDT 24
Finished Aug 17 05:55:40 PM PDT 24
Peak memory 200728 kb
Host smart-a9a092ee-bcda-4043-8905-a953798d7721
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3032952145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3032952145
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.986874499
Short name T466
Test name
Test status
Simulation time 49356382946 ps
CPU time 676.4 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:05:48 PM PDT 24
Peak memory 200676 kb
Host smart-1d190062-1d17-4225-818a-12935e14f334
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=986874499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.986874499
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3555546274
Short name T526
Test name
Test status
Simulation time 696712368534 ps
CPU time 2391.72 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 06:34:24 PM PDT 24
Peak memory 216752 kb
Host smart-303e3d40-883a-4917-9bcf-7011477cf6b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3555546274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3555546274
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1438861389
Short name T448
Test name
Test status
Simulation time 2655142859528 ps
CPU time 2309.59 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 06:32:57 PM PDT 24
Peak memory 216148 kb
Host smart-cb210441-3a94-4262-bbe8-b57d92408ff7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1438861389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1438861389
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.787744355
Short name T296
Test name
Test status
Simulation time 310358405 ps
CPU time 1.46 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 05:54:24 PM PDT 24
Peak memory 200660 kb
Host smart-ca9fae84-79ea-41ea-8995-953174b50bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787744355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.787744355
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1827650406
Short name T272
Test name
Test status
Simulation time 25714617 ps
CPU time 0.6 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 05:55:35 PM PDT 24
Peak memory 195636 kb
Host smart-8e7a5903-d3a5-40b0-ba8e-45b0ec74942a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827650406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1827650406
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1592093430
Short name T49
Test name
Test status
Simulation time 621450115 ps
CPU time 36.74 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:55:55 PM PDT 24
Peak memory 200672 kb
Host smart-959e7aba-17eb-4dc2-a023-391e2d8a0d0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1592093430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1592093430
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.889713538
Short name T45
Test name
Test status
Simulation time 18372550545 ps
CPU time 58.57 seconds
Started Aug 17 05:55:20 PM PDT 24
Finished Aug 17 05:56:18 PM PDT 24
Peak memory 200744 kb
Host smart-cabed845-c647-4dfa-b686-9edf35952049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889713538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.889713538
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3772545266
Short name T352
Test name
Test status
Simulation time 22640309616 ps
CPU time 541.75 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 06:04:20 PM PDT 24
Peak memory 668236 kb
Host smart-f44a9aa1-c915-403e-8ddc-c20230008beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772545266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3772545266
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1163698529
Short name T82
Test name
Test status
Simulation time 4409547301 ps
CPU time 28.95 seconds
Started Aug 17 05:55:17 PM PDT 24
Finished Aug 17 05:55:46 PM PDT 24
Peak memory 200612 kb
Host smart-3076e2e9-18fa-4077-a30b-188b630a0f80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163698529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1163698529
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1152881360
Short name T423
Test name
Test status
Simulation time 1809123918 ps
CPU time 9 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:55:27 PM PDT 24
Peak memory 200460 kb
Host smart-1cefb1c8-1291-41aa-a486-085d3a7034dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152881360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1152881360
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.4234431382
Short name T339
Test name
Test status
Simulation time 2270228799 ps
CPU time 10.07 seconds
Started Aug 17 05:55:17 PM PDT 24
Finished Aug 17 05:55:27 PM PDT 24
Peak memory 200692 kb
Host smart-ff0b92dc-7e97-4ef8-a59f-2d974c93807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234431382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4234431382
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1513450345
Short name T27
Test name
Test status
Simulation time 17899293430 ps
CPU time 492.26 seconds
Started Aug 17 05:55:29 PM PDT 24
Finished Aug 17 06:03:41 PM PDT 24
Peak memory 200732 kb
Host smart-fe62ba82-450b-4d63-b1c9-cfcb8df90fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513450345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1513450345
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.439329010
Short name T93
Test name
Test status
Simulation time 8802490796 ps
CPU time 89.09 seconds
Started Aug 17 05:55:18 PM PDT 24
Finished Aug 17 05:56:47 PM PDT 24
Peak memory 200772 kb
Host smart-738b1247-584a-4a8e-a4a6-c56f0fe4172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439329010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.439329010
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.436835229
Short name T531
Test name
Test status
Simulation time 27764523 ps
CPU time 0.61 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 05:55:34 PM PDT 24
Peak memory 196672 kb
Host smart-c5c89922-701b-443a-a50d-f453c279ac8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436835229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.436835229
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1874344219
Short name T449
Test name
Test status
Simulation time 703007429 ps
CPU time 38.8 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:56:12 PM PDT 24
Peak memory 200632 kb
Host smart-636fc263-dd30-47d7-aa74-7970df3a9bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1874344219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1874344219
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1513477559
Short name T492
Test name
Test status
Simulation time 23903183289 ps
CPU time 18.8 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 05:55:51 PM PDT 24
Peak memory 200756 kb
Host smart-ff334610-2f42-4a04-a21f-b78a920ede51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513477559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1513477559
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1320584531
Short name T206
Test name
Test status
Simulation time 9798554059 ps
CPU time 958.23 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 06:11:31 PM PDT 24
Peak memory 749076 kb
Host smart-71e5ef3d-d163-4295-af95-89776df01b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1320584531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1320584531
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3337762352
Short name T410
Test name
Test status
Simulation time 12540972065 ps
CPU time 76.56 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:56:53 PM PDT 24
Peak memory 200692 kb
Host smart-e4949c79-df46-4cb8-ada6-2469caa142f5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337762352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3337762352
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3615295346
Short name T421
Test name
Test status
Simulation time 9634326550 ps
CPU time 65.53 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 05:56:37 PM PDT 24
Peak memory 200816 kb
Host smart-d559b509-72e1-44ee-b64c-38dcae8b3e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615295346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3615295346
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4136647653
Short name T444
Test name
Test status
Simulation time 494255244 ps
CPU time 11.36 seconds
Started Aug 17 05:55:31 PM PDT 24
Finished Aug 17 05:55:43 PM PDT 24
Peak memory 200728 kb
Host smart-a6d3f472-f2c3-44e4-bc8d-c69d159883ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136647653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4136647653
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3476856450
Short name T435
Test name
Test status
Simulation time 11522494272 ps
CPU time 582.48 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 06:05:15 PM PDT 24
Peak memory 711712 kb
Host smart-7f2d26b0-d51b-4df6-b837-82cea1b3ea02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476856450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3476856450
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2115966859
Short name T23
Test name
Test status
Simulation time 6186583140 ps
CPU time 64.1 seconds
Started Aug 17 05:55:30 PM PDT 24
Finished Aug 17 05:56:34 PM PDT 24
Peak memory 200772 kb
Host smart-6496c822-912d-41ed-993f-985512b41020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115966859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2115966859
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4046664478
Short name T258
Test name
Test status
Simulation time 43411350 ps
CPU time 0.63 seconds
Started Aug 17 05:55:35 PM PDT 24
Finished Aug 17 05:55:36 PM PDT 24
Peak memory 197344 kb
Host smart-e81a9692-4b2e-4491-ad14-66eba873da93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046664478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4046664478
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1115270146
Short name T317
Test name
Test status
Simulation time 1004114900 ps
CPU time 33.76 seconds
Started Aug 17 05:55:31 PM PDT 24
Finished Aug 17 05:56:05 PM PDT 24
Peak memory 200680 kb
Host smart-8925aade-9159-48ab-8802-080d7fc2ccf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115270146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1115270146
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1224397634
Short name T371
Test name
Test status
Simulation time 6370158993 ps
CPU time 24.02 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:55:58 PM PDT 24
Peak memory 200776 kb
Host smart-c0758023-4d7a-4eea-a740-143da77eebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224397634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1224397634
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.16457667
Short name T52
Test name
Test status
Simulation time 10616972227 ps
CPU time 1244.65 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 06:16:17 PM PDT 24
Peak memory 763680 kb
Host smart-2b13722b-edec-42f5-8043-d5462b011dd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16457667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.16457667
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.782773437
Short name T189
Test name
Test status
Simulation time 8088662779 ps
CPU time 117.52 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 05:57:29 PM PDT 24
Peak memory 200712 kb
Host smart-e6a8898c-e6c3-4722-8570-a5ef028a61b3
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782773437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.782773437
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2107762680
Short name T350
Test name
Test status
Simulation time 366654662 ps
CPU time 6.85 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:55:40 PM PDT 24
Peak memory 200628 kb
Host smart-b72381c9-1b5b-4b82-b02e-7310b4052777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107762680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2107762680
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.282500338
Short name T79
Test name
Test status
Simulation time 202758969 ps
CPU time 9.41 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:55:45 PM PDT 24
Peak memory 200464 kb
Host smart-13405dda-8e6d-4130-859a-2901d19a72ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282500338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.282500338
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3717145044
Short name T521
Test name
Test status
Simulation time 33997639467 ps
CPU time 1366.03 seconds
Started Aug 17 05:55:31 PM PDT 24
Finished Aug 17 06:18:18 PM PDT 24
Peak memory 650464 kb
Host smart-e5baa718-4480-4aac-9102-9038fb7736a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717145044 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3717145044
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1257842052
Short name T290
Test name
Test status
Simulation time 3233290022 ps
CPU time 29.98 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:56:06 PM PDT 24
Peak memory 200516 kb
Host smart-3d675274-aec2-4a6f-8207-7a4fd4cf4db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257842052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1257842052
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2687374947
Short name T471
Test name
Test status
Simulation time 13606930 ps
CPU time 0.63 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:55:34 PM PDT 24
Peak memory 196728 kb
Host smart-253c54da-2e25-4e6e-b6dc-1ab006f959cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687374947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2687374947
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2180606812
Short name T19
Test name
Test status
Simulation time 6183359647 ps
CPU time 102 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:57:15 PM PDT 24
Peak memory 200788 kb
Host smart-dba86bf7-d410-487e-80a0-57799896773a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180606812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2180606812
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.726681814
Short name T138
Test name
Test status
Simulation time 18372158624 ps
CPU time 68.08 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:56:42 PM PDT 24
Peak memory 200752 kb
Host smart-26a144c6-8c8e-469a-a538-7b0661e3f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726681814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.726681814
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2190857928
Short name T47
Test name
Test status
Simulation time 1308077171 ps
CPU time 317.65 seconds
Started Aug 17 05:55:30 PM PDT 24
Finished Aug 17 06:00:48 PM PDT 24
Peak memory 659668 kb
Host smart-dae4ddf3-c865-4baa-b139-486f0f903889
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190857928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2190857928
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.712593847
Short name T316
Test name
Test status
Simulation time 45233197744 ps
CPU time 159.98 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 05:58:14 PM PDT 24
Peak memory 200740 kb
Host smart-c135db85-308c-4c15-bd7e-67674def644b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712593847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.712593847
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1830276197
Short name T493
Test name
Test status
Simulation time 10046703787 ps
CPU time 197.78 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 05:58:50 PM PDT 24
Peak memory 208904 kb
Host smart-d887cca3-7112-47e9-94a7-7acee97a6762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830276197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1830276197
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3316844015
Short name T181
Test name
Test status
Simulation time 430716552 ps
CPU time 9.73 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:55:43 PM PDT 24
Peak memory 200668 kb
Host smart-a14d2444-6698-4c9b-92d6-cbe29005cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316844015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3316844015
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.842415066
Short name T369
Test name
Test status
Simulation time 37821645874 ps
CPU time 1058.07 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 06:13:11 PM PDT 24
Peak memory 514684 kb
Host smart-8c6ed472-d4cb-44f0-a701-3cbf470da3d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842415066 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.842415066
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1707508147
Short name T91
Test name
Test status
Simulation time 5649556061 ps
CPU time 62.62 seconds
Started Aug 17 05:55:31 PM PDT 24
Finished Aug 17 05:56:34 PM PDT 24
Peak memory 200736 kb
Host smart-863d8e31-c01c-420a-996e-00ac97fefea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707508147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1707508147
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.805045853
Short name T465
Test name
Test status
Simulation time 41221785 ps
CPU time 0.6 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:55:36 PM PDT 24
Peak memory 196740 kb
Host smart-99892301-6a7b-4104-a21b-c4f0692c9416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805045853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.805045853
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3748662207
Short name T183
Test name
Test status
Simulation time 5237291990 ps
CPU time 81.17 seconds
Started Aug 17 05:55:31 PM PDT 24
Finished Aug 17 05:56:53 PM PDT 24
Peak memory 200748 kb
Host smart-934f4cec-3fdf-40e8-879b-1e748e0319cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3748662207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3748662207
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3390494437
Short name T219
Test name
Test status
Simulation time 8456992703 ps
CPU time 45.28 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 05:56:19 PM PDT 24
Peak memory 200744 kb
Host smart-6f90f4ec-9e92-4ac7-8e4e-656bb3db5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390494437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3390494437
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1649410942
Short name T468
Test name
Test status
Simulation time 11076366791 ps
CPU time 450.18 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 06:03:07 PM PDT 24
Peak memory 668392 kb
Host smart-da2daa1e-2c60-4afc-8a99-552ec822cbc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649410942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1649410942
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1231886467
Short name T248
Test name
Test status
Simulation time 11555247387 ps
CPU time 86.07 seconds
Started Aug 17 05:55:32 PM PDT 24
Finished Aug 17 05:56:58 PM PDT 24
Peak memory 200732 kb
Host smart-68fdca00-3c67-403a-b993-ea81bf4d6eb9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231886467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1231886467
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.3314880214
Short name T253
Test name
Test status
Simulation time 290236442 ps
CPU time 4.35 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 05:55:38 PM PDT 24
Peak memory 200660 kb
Host smart-d4141936-d244-4701-baf5-5ba4933b7618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314880214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.3314880214
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.637119813
Short name T408
Test name
Test status
Simulation time 850058909 ps
CPU time 6.72 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:55:39 PM PDT 24
Peak memory 200632 kb
Host smart-b8e7f927-7543-452b-ba4d-17853615286d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637119813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.637119813
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3180209600
Short name T437
Test name
Test status
Simulation time 7352902325 ps
CPU time 100.9 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:57:17 PM PDT 24
Peak memory 200632 kb
Host smart-0cf07686-476d-4e94-a6ce-559d3a6704a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180209600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3180209600
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3932051327
Short name T458
Test name
Test status
Simulation time 13505152 ps
CPU time 0.58 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 05:55:41 PM PDT 24
Peak memory 195700 kb
Host smart-590c1746-32ee-4f70-a980-db90916cfc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932051327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3932051327
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3872742497
Short name T251
Test name
Test status
Simulation time 342456486 ps
CPU time 10.17 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 05:55:50 PM PDT 24
Peak memory 200660 kb
Host smart-cfb6fb3e-5f19-4df2-9e77-6203f4289945
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3872742497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3872742497
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3730220305
Short name T214
Test name
Test status
Simulation time 356795134 ps
CPU time 6.83 seconds
Started Aug 17 05:55:44 PM PDT 24
Finished Aug 17 05:55:51 PM PDT 24
Peak memory 200728 kb
Host smart-9dc3fe2c-a25a-4cf6-905a-5b7567502b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730220305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3730220305
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1332262599
Short name T50
Test name
Test status
Simulation time 18891180140 ps
CPU time 847.34 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 06:09:47 PM PDT 24
Peak memory 745664 kb
Host smart-f9a1d6ea-28b6-4814-8001-4573c7298f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332262599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1332262599
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1626100556
Short name T294
Test name
Test status
Simulation time 14118958243 ps
CPU time 203.45 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:58:56 PM PDT 24
Peak memory 200608 kb
Host smart-e4ce6432-5e91-49ab-91be-053c4c84ba3b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626100556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1626100556
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.623656161
Short name T443
Test name
Test status
Simulation time 2483849879 ps
CPU time 146.07 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:57:59 PM PDT 24
Peak memory 200704 kb
Host smart-cdf0f808-67ce-4039-b3d8-42ccc67ffc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623656161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.623656161
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.731525694
Short name T417
Test name
Test status
Simulation time 608256593 ps
CPU time 7.18 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:55:44 PM PDT 24
Peak memory 200548 kb
Host smart-326ee2a3-5e6e-4c38-991d-36be614876c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731525694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.731525694
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2061627331
Short name T230
Test name
Test status
Simulation time 110398867086 ps
CPU time 2849.13 seconds
Started Aug 17 05:55:35 PM PDT 24
Finished Aug 17 06:43:05 PM PDT 24
Peak memory 753224 kb
Host smart-f0e1b43a-3ba2-4ea6-af50-55c14570c3e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061627331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2061627331
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2802776936
Short name T8
Test name
Test status
Simulation time 1765496368 ps
CPU time 83.93 seconds
Started Aug 17 05:55:39 PM PDT 24
Finished Aug 17 05:57:03 PM PDT 24
Peak memory 200648 kb
Host smart-bf08946f-0105-4016-a862-8eac88d589e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802776936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2802776936
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2643811651
Short name T34
Test name
Test status
Simulation time 20538690 ps
CPU time 0.62 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:55:43 PM PDT 24
Peak memory 197424 kb
Host smart-2086aac0-07e2-47fe-a31f-8de622175de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643811651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2643811651
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3202063916
Short name T33
Test name
Test status
Simulation time 5262716544 ps
CPU time 70.48 seconds
Started Aug 17 05:55:33 PM PDT 24
Finished Aug 17 05:56:44 PM PDT 24
Peak memory 200768 kb
Host smart-6f750947-8fca-4f28-b836-7734a42f0270
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3202063916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3202063916
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1677272259
Short name T29
Test name
Test status
Simulation time 2299597884 ps
CPU time 60.34 seconds
Started Aug 17 05:55:35 PM PDT 24
Finished Aug 17 05:56:35 PM PDT 24
Peak memory 200728 kb
Host smart-6bbe4687-684f-4e75-9829-f55bc56b210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677272259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1677272259
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3434985465
Short name T411
Test name
Test status
Simulation time 9297692112 ps
CPU time 454.51 seconds
Started Aug 17 05:55:34 PM PDT 24
Finished Aug 17 06:03:08 PM PDT 24
Peak memory 667464 kb
Host smart-a0a13633-d2aa-41c1-a4a1-d513f3b9754d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3434985465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3434985465
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2697475237
Short name T179
Test name
Test status
Simulation time 18119040093 ps
CPU time 132.78 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:57:55 PM PDT 24
Peak memory 200576 kb
Host smart-fbcc9e35-e6fe-40f7-b206-7913ad58f53c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697475237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2697475237
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1013552939
Short name T53
Test name
Test status
Simulation time 44036949666 ps
CPU time 162.49 seconds
Started Aug 17 05:55:36 PM PDT 24
Finished Aug 17 05:58:18 PM PDT 24
Peak memory 200748 kb
Host smart-3d5fc782-e6c8-4e90-a102-5e0f70608c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013552939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1013552939
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.2248984153
Short name T155
Test name
Test status
Simulation time 192482290 ps
CPU time 1.27 seconds
Started Aug 17 05:55:44 PM PDT 24
Finished Aug 17 05:55:45 PM PDT 24
Peak memory 200552 kb
Host smart-0667ccc9-8347-4286-8133-5e5dc975c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248984153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.2248984153
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3112821162
Short name T359
Test name
Test status
Simulation time 19768484747 ps
CPU time 376.67 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 06:01:57 PM PDT 24
Peak memory 208968 kb
Host smart-080f4323-510f-4ed4-97b0-bb4d003133da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112821162 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3112821162
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.86244324
Short name T256
Test name
Test status
Simulation time 891572554 ps
CPU time 13.35 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 05:55:54 PM PDT 24
Peak memory 200644 kb
Host smart-8c6d0d91-467f-4cbb-a7d8-e62d9ebbe204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86244324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.86244324
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1010967207
Short name T429
Test name
Test status
Simulation time 110294306 ps
CPU time 0.6 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:55:42 PM PDT 24
Peak memory 197380 kb
Host smart-467d858e-c642-44a0-9593-2913285a1fe0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010967207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1010967207
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.4265928976
Short name T264
Test name
Test status
Simulation time 1189626031 ps
CPU time 71.19 seconds
Started Aug 17 05:55:41 PM PDT 24
Finished Aug 17 05:56:52 PM PDT 24
Peak memory 200584 kb
Host smart-0a1ecfa8-c44e-4f87-8bc0-ae78c63e8f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4265928976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.4265928976
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1582946234
Short name T143
Test name
Test status
Simulation time 1260435321 ps
CPU time 16.44 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:55:59 PM PDT 24
Peak memory 200740 kb
Host smart-27298f80-0a8e-40d9-a119-b586b4095b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582946234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1582946234
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2755347496
Short name T532
Test name
Test status
Simulation time 3119034951 ps
CPU time 186.99 seconds
Started Aug 17 05:55:41 PM PDT 24
Finished Aug 17 05:58:48 PM PDT 24
Peak memory 362064 kb
Host smart-e10540c3-b5bd-4a5d-8240-b60d9ac79a8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755347496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2755347496
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3309373029
Short name T280
Test name
Test status
Simulation time 3083869664 ps
CPU time 170.66 seconds
Started Aug 17 05:55:43 PM PDT 24
Finished Aug 17 05:58:33 PM PDT 24
Peak memory 200792 kb
Host smart-0f8e4638-ee40-4cc0-b45f-e33077ea00b5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309373029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3309373029
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.314359287
Short name T308
Test name
Test status
Simulation time 4097576141 ps
CPU time 64.49 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:56:47 PM PDT 24
Peak memory 200732 kb
Host smart-e6939071-042d-45f0-8324-8f2de74965ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314359287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.314359287
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4270584844
Short name T276
Test name
Test status
Simulation time 85766212 ps
CPU time 4.24 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 05:55:45 PM PDT 24
Peak memory 200672 kb
Host smart-77f66847-a558-4de1-a3f2-904dc1124589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270584844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4270584844
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1089193635
Short name T44
Test name
Test status
Simulation time 83881794035 ps
CPU time 905.24 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 06:10:46 PM PDT 24
Peak memory 691304 kb
Host smart-94117640-52f4-41d0-a308-023b5e85701f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089193635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1089193635
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.827569727
Short name T306
Test name
Test status
Simulation time 1088294358 ps
CPU time 18.16 seconds
Started Aug 17 05:55:43 PM PDT 24
Finished Aug 17 05:56:01 PM PDT 24
Peak memory 200588 kb
Host smart-f810fa44-394e-4cb0-9fc5-e9f315ffcd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827569727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.827569727
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2234299862
Short name T332
Test name
Test status
Simulation time 125403706 ps
CPU time 0.61 seconds
Started Aug 17 05:55:38 PM PDT 24
Finished Aug 17 05:55:39 PM PDT 24
Peak memory 197420 kb
Host smart-0e101903-455d-49aa-b902-3180b658559b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234299862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2234299862
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2664782511
Short name T26
Test name
Test status
Simulation time 3188490943 ps
CPU time 43.23 seconds
Started Aug 17 05:55:41 PM PDT 24
Finished Aug 17 05:56:24 PM PDT 24
Peak memory 200748 kb
Host smart-25bda6f1-afbb-4cd9-869a-ee1498214636
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664782511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2664782511
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2367543839
Short name T160
Test name
Test status
Simulation time 25389668987 ps
CPU time 49.48 seconds
Started Aug 17 05:55:41 PM PDT 24
Finished Aug 17 05:56:30 PM PDT 24
Peak memory 200744 kb
Host smart-bd798c21-7785-4840-85bd-f616712f5fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367543839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2367543839
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.643973372
Short name T413
Test name
Test status
Simulation time 7355611174 ps
CPU time 349.04 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 06:01:29 PM PDT 24
Peak memory 614596 kb
Host smart-3ecbcb63-780b-48ed-9c1d-abeba2e1882f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643973372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.643973372
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.359746676
Short name T450
Test name
Test status
Simulation time 38801728092 ps
CPU time 127.77 seconds
Started Aug 17 05:55:40 PM PDT 24
Finished Aug 17 05:57:48 PM PDT 24
Peak memory 200792 kb
Host smart-31c6cc1e-2ca0-4f08-871a-b5c666f9de4c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359746676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.359746676
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3059483174
Short name T233
Test name
Test status
Simulation time 11227058574 ps
CPU time 214.69 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:59:17 PM PDT 24
Peak memory 200748 kb
Host smart-e22fb394-5450-4719-8214-766c5ff03b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059483174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3059483174
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2609225819
Short name T384
Test name
Test status
Simulation time 654378797 ps
CPU time 8.8 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:55:51 PM PDT 24
Peak memory 200684 kb
Host smart-a753d8f0-836d-4768-898c-e541269c2598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609225819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2609225819
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2348381627
Short name T436
Test name
Test status
Simulation time 45040962741 ps
CPU time 570.33 seconds
Started Aug 17 05:55:43 PM PDT 24
Finished Aug 17 06:05:13 PM PDT 24
Peak memory 200728 kb
Host smart-5844b8a0-d2c3-4835-81ec-3d9ce76e59a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348381627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2348381627
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2081093538
Short name T467
Test name
Test status
Simulation time 15137810714 ps
CPU time 110.68 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:57:33 PM PDT 24
Peak memory 200700 kb
Host smart-d75c0edf-c2ac-4f5a-a861-48ae1d6208ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081093538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2081093538
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2156825017
Short name T151
Test name
Test status
Simulation time 18771714 ps
CPU time 0.59 seconds
Started Aug 17 05:55:48 PM PDT 24
Finished Aug 17 05:55:48 PM PDT 24
Peak memory 195696 kb
Host smart-7fb0bdc6-d585-469a-8c79-3f72c68589cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156825017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2156825017
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2002125757
Short name T318
Test name
Test status
Simulation time 1985789511 ps
CPU time 63.33 seconds
Started Aug 17 05:55:43 PM PDT 24
Finished Aug 17 05:56:46 PM PDT 24
Peak memory 200640 kb
Host smart-ca7ebe28-4118-429c-b2d1-914c69343eb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2002125757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2002125757
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3836350378
Short name T503
Test name
Test status
Simulation time 3764343479 ps
CPU time 45.86 seconds
Started Aug 17 05:55:39 PM PDT 24
Finished Aug 17 05:56:25 PM PDT 24
Peak memory 200744 kb
Host smart-6a345b99-aea7-4000-94f5-f9cbe6cdd654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836350378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3836350378
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3043175738
Short name T368
Test name
Test status
Simulation time 2490445159 ps
CPU time 262.1 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 06:00:04 PM PDT 24
Peak memory 652480 kb
Host smart-b4ae9891-45ea-4acf-9fd2-614349803aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3043175738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3043175738
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3538346159
Short name T428
Test name
Test status
Simulation time 3115516392 ps
CPU time 174.07 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:58:36 PM PDT 24
Peak memory 200720 kb
Host smart-9e517c9b-04ff-4675-8b1f-ae139196298a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538346159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3538346159
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1573679460
Short name T168
Test name
Test status
Simulation time 117042306087 ps
CPU time 203.31 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:59:05 PM PDT 24
Peak memory 200744 kb
Host smart-f0a41f39-aa1e-4887-bcf9-c9cba6d2af80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573679460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1573679460
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2336211770
Short name T347
Test name
Test status
Simulation time 1149014961 ps
CPU time 15.46 seconds
Started Aug 17 05:55:43 PM PDT 24
Finished Aug 17 05:55:59 PM PDT 24
Peak memory 200664 kb
Host smart-aac71acf-fb50-48f2-a7f0-c8f075ec8633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336211770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2336211770
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1856022245
Short name T173
Test name
Test status
Simulation time 1416571175 ps
CPU time 77.47 seconds
Started Aug 17 05:55:49 PM PDT 24
Finished Aug 17 05:57:07 PM PDT 24
Peak memory 200664 kb
Host smart-3eb82b4e-7d88-4120-bb0e-fc2932a9bd92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856022245 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1856022245
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4287885690
Short name T488
Test name
Test status
Simulation time 46915460192 ps
CPU time 125.95 seconds
Started Aug 17 05:55:42 PM PDT 24
Finished Aug 17 05:57:48 PM PDT 24
Peak memory 200708 kb
Host smart-62baf97e-bac5-41bb-9830-7aa46d3c6c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287885690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4287885690
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.777948221
Short name T372
Test name
Test status
Simulation time 14666085 ps
CPU time 0.59 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:54:32 PM PDT 24
Peak memory 196628 kb
Host smart-bbb6486d-26bf-446a-810d-45f179102674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777948221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.777948221
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.93507789
Short name T477
Test name
Test status
Simulation time 7823980224 ps
CPU time 92.58 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:56:02 PM PDT 24
Peak memory 208864 kb
Host smart-ca9fd6e6-279f-4408-917b-5e5e09d97c1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93507789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.93507789
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.465892646
Short name T137
Test name
Test status
Simulation time 1823772422 ps
CPU time 24.19 seconds
Started Aug 17 05:54:26 PM PDT 24
Finished Aug 17 05:54:51 PM PDT 24
Peak memory 200688 kb
Host smart-bf42d1cd-c7bc-4ff9-9f46-80d5b1678dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465892646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.465892646
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2106588192
Short name T440
Test name
Test status
Simulation time 362196517 ps
CPU time 65.51 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:55:38 PM PDT 24
Peak memory 348216 kb
Host smart-fe7dafe8-d42b-45d9-b156-6ddd7ece5951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106588192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2106588192
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.294606128
Short name T381
Test name
Test status
Simulation time 6965198122 ps
CPU time 186.34 seconds
Started Aug 17 05:54:43 PM PDT 24
Finished Aug 17 05:57:49 PM PDT 24
Peak memory 200588 kb
Host smart-853cb87c-c167-4f2c-b4e7-63a1604dfc6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294606128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.294606128
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1737979955
Short name T3
Test name
Test status
Simulation time 19284597 ps
CPU time 0.63 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 05:54:23 PM PDT 24
Peak memory 197140 kb
Host smart-9a2ee355-e960-4ed3-934f-1ad516deada1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737979955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1737979955
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2910857762
Short name T452
Test name
Test status
Simulation time 277982532 ps
CPU time 1.47 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:54:30 PM PDT 24
Peak memory 200648 kb
Host smart-9c35a6eb-73c6-436b-8e57-01d3db99c3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910857762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2910857762
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1846500152
Short name T39
Test name
Test status
Simulation time 290555527003 ps
CPU time 4010.79 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 07:01:22 PM PDT 24
Peak memory 871240 kb
Host smart-4cfa06b8-c3f1-4c65-85a9-eb92eda5a457
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846500152 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1846500152
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.938527513
Short name T380
Test name
Test status
Simulation time 22033963075 ps
CPU time 32.4 seconds
Started Aug 17 05:54:25 PM PDT 24
Finished Aug 17 05:54:58 PM PDT 24
Peak memory 200816 kb
Host smart-f0cfc5b2-1247-4a8f-b87c-5c180c039025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938527513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.938527513
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2381484307
Short name T42
Test name
Test status
Simulation time 15594871 ps
CPU time 0.59 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:54:32 PM PDT 24
Peak memory 196740 kb
Host smart-c4e63c62-89f6-41b1-a96e-451783510f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381484307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2381484307
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1285256685
Short name T166
Test name
Test status
Simulation time 2245645584 ps
CPU time 57.5 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:55:28 PM PDT 24
Peak memory 200756 kb
Host smart-d61e8ea5-e2e9-41b4-a0de-78e5f886b799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285256685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1285256685
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1174878609
Short name T395
Test name
Test status
Simulation time 10993442756 ps
CPU time 34.91 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:55:04 PM PDT 24
Peak memory 200688 kb
Host smart-fd06c827-6dca-4af2-a8c8-b8cb529073d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174878609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1174878609
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1316308681
Short name T523
Test name
Test status
Simulation time 1748380664 ps
CPU time 280.25 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 05:59:07 PM PDT 24
Peak memory 591052 kb
Host smart-4f2c1073-acfb-4af7-8b62-3c450bee81a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1316308681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1316308681
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4157926573
Short name T171
Test name
Test status
Simulation time 1494370800 ps
CPU time 81.16 seconds
Started Aug 17 05:54:37 PM PDT 24
Finished Aug 17 05:55:58 PM PDT 24
Peak memory 200536 kb
Host smart-1176a02c-d119-40ef-9323-40cff67a6479
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157926573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4157926573
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4039764787
Short name T528
Test name
Test status
Simulation time 12260533403 ps
CPU time 130.48 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:56:44 PM PDT 24
Peak memory 200732 kb
Host smart-77b0c7f0-f91a-4a0a-8b5c-6934347610fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039764787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4039764787
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3246415442
Short name T235
Test name
Test status
Simulation time 3169945257 ps
CPU time 12.12 seconds
Started Aug 17 05:54:42 PM PDT 24
Finished Aug 17 05:54:55 PM PDT 24
Peak memory 200612 kb
Host smart-c40c263f-f37c-4df2-ae56-364290682fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246415442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3246415442
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.624570400
Short name T462
Test name
Test status
Simulation time 74710602195 ps
CPU time 2236.31 seconds
Started Aug 17 05:54:23 PM PDT 24
Finished Aug 17 06:31:39 PM PDT 24
Peak memory 716512 kb
Host smart-28dd9061-d2c7-4adb-8ed3-1b8389915552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624570400 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.624570400
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1410271338
Short name T239
Test name
Test status
Simulation time 2341382833 ps
CPU time 43.35 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200812 kb
Host smart-a21dd13a-114c-46c8-be39-801d130ab487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410271338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1410271338
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.861900983
Short name T157
Test name
Test status
Simulation time 15116878 ps
CPU time 0.62 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:54:33 PM PDT 24
Peak memory 196740 kb
Host smart-d3830d70-f084-4979-bed5-5efec16ea099
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861900983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.861900983
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2922944816
Short name T398
Test name
Test status
Simulation time 2308982303 ps
CPU time 65.9 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:55:42 PM PDT 24
Peak memory 200748 kb
Host smart-8deab2bb-7ca9-489e-a626-0ea35d44ac9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922944816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2922944816
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1179804486
Short name T186
Test name
Test status
Simulation time 8080720875 ps
CPU time 36.9 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:55:15 PM PDT 24
Peak memory 200776 kb
Host smart-1b57f794-a9f8-470e-97df-4d8a9ee8a9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179804486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1179804486
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2108216014
Short name T80
Test name
Test status
Simulation time 8092244832 ps
CPU time 1302.58 seconds
Started Aug 17 05:54:41 PM PDT 24
Finished Aug 17 06:16:24 PM PDT 24
Peak memory 736248 kb
Host smart-05e55975-476e-4e68-a34c-4a6fdd24de10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108216014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2108216014
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2197799551
Short name T279
Test name
Test status
Simulation time 6086282605 ps
CPU time 216.79 seconds
Started Aug 17 05:54:32 PM PDT 24
Finished Aug 17 05:58:09 PM PDT 24
Peak memory 200676 kb
Host smart-ec215271-6d11-4bee-b2dd-de62c76ea426
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197799551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2197799551
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1940955044
Short name T255
Test name
Test status
Simulation time 13995765942 ps
CPU time 128.7 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:56:43 PM PDT 24
Peak memory 200644 kb
Host smart-eadfcaed-6e1c-437c-990f-fb93facc23cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940955044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1940955044
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2033970300
Short name T451
Test name
Test status
Simulation time 121927323 ps
CPU time 5.84 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:54:41 PM PDT 24
Peak memory 200676 kb
Host smart-26a3f51a-d48e-41b5-bd42-eb16bd86db29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033970300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2033970300
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.299242865
Short name T92
Test name
Test status
Simulation time 2818442216 ps
CPU time 39.92 seconds
Started Aug 17 05:54:38 PM PDT 24
Finished Aug 17 05:55:18 PM PDT 24
Peak memory 200724 kb
Host smart-f09ff9c6-1edf-4527-b536-3a03303729ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299242865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.299242865
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3156561262
Short name T330
Test name
Test status
Simulation time 24910630 ps
CPU time 0.58 seconds
Started Aug 17 05:54:37 PM PDT 24
Finished Aug 17 05:54:37 PM PDT 24
Peak memory 196724 kb
Host smart-945e3607-92a1-48fe-bbc3-c64d65bf0439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156561262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3156561262
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1479796990
Short name T212
Test name
Test status
Simulation time 23394053689 ps
CPU time 92.93 seconds
Started Aug 17 05:54:35 PM PDT 24
Finished Aug 17 05:56:08 PM PDT 24
Peak memory 200520 kb
Host smart-be2e1eef-5d7d-46d4-afd6-06c9919f8423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1479796990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1479796990
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.196764852
Short name T78
Test name
Test status
Simulation time 1797877642 ps
CPU time 57.15 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:55:30 PM PDT 24
Peak memory 200736 kb
Host smart-4d5058f8-2d4b-46b9-859a-856634db941d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196764852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.196764852
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1910487389
Short name T405
Test name
Test status
Simulation time 20625732399 ps
CPU time 622.85 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 06:04:56 PM PDT 24
Peak memory 649844 kb
Host smart-eaea1e50-ac6a-4117-8c77-064e0af6c790
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910487389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1910487389
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2626847543
Short name T260
Test name
Test status
Simulation time 37962950433 ps
CPU time 189.55 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:57:39 PM PDT 24
Peak memory 200772 kb
Host smart-df24f543-4f33-41b6-b39e-c78a6e475e33
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626847543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2626847543
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3085835418
Short name T406
Test name
Test status
Simulation time 4829854627 ps
CPU time 55.33 seconds
Started Aug 17 05:54:33 PM PDT 24
Finished Aug 17 05:55:28 PM PDT 24
Peak memory 200624 kb
Host smart-8137ffa9-3b25-42f2-a5e9-4609fd8538d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085835418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3085835418
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.418344916
Short name T203
Test name
Test status
Simulation time 305111762 ps
CPU time 12.62 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 05:54:44 PM PDT 24
Peak memory 200660 kb
Host smart-3ca84b6a-3aea-4308-aac5-2a8ea181fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418344916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.418344916
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2103632292
Short name T278
Test name
Test status
Simulation time 454363372238 ps
CPU time 994.76 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 06:11:09 PM PDT 24
Peak memory 729488 kb
Host smart-5c7a4011-9f67-42ec-84d9-2da094897d51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103632292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2103632292
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2448455221
Short name T202
Test name
Test status
Simulation time 3534129811 ps
CPU time 21.81 seconds
Started Aug 17 05:54:39 PM PDT 24
Finished Aug 17 05:55:00 PM PDT 24
Peak memory 200740 kb
Host smart-748526fd-9d1e-4743-b490-af2698f1054e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448455221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2448455221
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3208472850
Short name T274
Test name
Test status
Simulation time 40847272 ps
CPU time 0.59 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:54:35 PM PDT 24
Peak memory 197392 kb
Host smart-9df39bdc-0f62-428d-be21-b7f533c1fe41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208472850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3208472850
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2454735849
Short name T432
Test name
Test status
Simulation time 1957165068 ps
CPU time 60.25 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:55:29 PM PDT 24
Peak memory 200716 kb
Host smart-c9c89fab-2ec3-409a-acff-a01594f31011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454735849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2454735849
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1735146467
Short name T180
Test name
Test status
Simulation time 873632443 ps
CPU time 11.15 seconds
Started Aug 17 05:54:36 PM PDT 24
Finished Aug 17 05:54:47 PM PDT 24
Peak memory 200696 kb
Host smart-928968da-a3ac-4e52-83bb-46041188f0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735146467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1735146467
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2314050818
Short name T295
Test name
Test status
Simulation time 22589974047 ps
CPU time 1307.58 seconds
Started Aug 17 05:54:27 PM PDT 24
Finished Aug 17 06:16:15 PM PDT 24
Peak memory 763620 kb
Host smart-3fe0978f-8878-4f3c-97e2-c440507b2f71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314050818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2314050818
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3219685762
Short name T445
Test name
Test status
Simulation time 1243598410 ps
CPU time 10.06 seconds
Started Aug 17 05:54:29 PM PDT 24
Finished Aug 17 05:54:39 PM PDT 24
Peak memory 200608 kb
Host smart-e3f9ca2e-dff9-4792-bff7-1b0bc31554db
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219685762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3219685762
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3339972556
Short name T512
Test name
Test status
Simulation time 2150638877 ps
CPU time 15.97 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:54:50 PM PDT 24
Peak memory 200688 kb
Host smart-a0026b37-209d-4dcc-85a6-7ffb2788e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339972556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3339972556
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1556203186
Short name T495
Test name
Test status
Simulation time 4579130478 ps
CPU time 15.24 seconds
Started Aug 17 05:54:34 PM PDT 24
Finished Aug 17 05:54:50 PM PDT 24
Peak memory 200696 kb
Host smart-8f13b964-54f5-46c9-bf8a-dc432ef3c1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556203186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1556203186
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1156665999
Short name T249
Test name
Test status
Simulation time 77722168115 ps
CPU time 662.16 seconds
Started Aug 17 05:54:31 PM PDT 24
Finished Aug 17 06:05:34 PM PDT 24
Peak memory 702296 kb
Host smart-f059feed-7494-4b9c-858c-1e574c879c92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156665999 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1156665999
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2033702880
Short name T66
Test name
Test status
Simulation time 32781750653 ps
CPU time 128.9 seconds
Started Aug 17 05:54:30 PM PDT 24
Finished Aug 17 05:56:39 PM PDT 24
Peak memory 200792 kb
Host smart-4d88977d-c017-4737-a2c2-e96cbd81f667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033702880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2033702880
Directory /workspace/9.hmac_wipe_secret/latest
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