Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16754225	1			T1	22897		T2	34900		T3	4990
all_values[1]	16754225	1			T1	22897		T2	34900		T3	4990
all_values[2]	16754225	1			T1	22897		T2	34900		T3	4990

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289428

1

T1

3581

T2

124

T3

1040

auto[1]

49973247

1

T1

65110

T2

104576

T3

13930

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42808626

1

T1

53358

T2

81565

T3

12770

auto[1]

7454049

1

T1

15333

T2

23135

T3

2200

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102208	1			T3	520		T6	6228		T16	98
all_values[0]	auto[0]	auto[1]	329	1			T16	2		T33	4		T114	2
all_values[0]	auto[1]	auto[0]	16632828	1			T1	22892		T2	34888		T3	4465
all_values[0]	auto[1]	auto[1]	18860	1			T1	5		T2	12		T3	5
all_values[1]	auto[0]	auto[0]	104655	1			T2	124		T6	6949		T14	84
all_values[1]	auto[0]	auto[1]	185	1			T33	5		T29	3		T59	1
all_values[1]	auto[1]	auto[0]	16649110	1			T1	22897		T2	34776		T3	4990
all_values[1]	auto[1]	auto[1]	275	1			T16	4		T33	4		T28	1
all_values[2]	auto[0]	auto[0]	53713	1			T1	1815		T3	129		T6	3191
all_values[2]	auto[0]	auto[1]	28338	1			T1	1766		T3	391		T6	2974
all_values[2]	auto[1]	auto[0]	9266112	1			T1	5754		T2	11777		T3	2666
all_values[2]	auto[1]	auto[1]	7406062	1			T1	13562		T2	23123		T3	1804