Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120861

1

T1

24

T2

44

T3

10

auto[1]

130830

1

T1

30

T2

18

T3

8

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	94870	1			T1	18		T2	23		T3	5
len_1026_2046	5715	1			T2	5		T6	51		T4	3
len_514_1022	3130	1			T6	22		T16	35		T41	58
len_2_510	3051	1			T6	24		T14	6		T16	27
len_2056	174	1			T6	6		T34	2		T33	1
len_2048	363	1			T6	1		T5	1		T15	1
len_2040	174	1			T14	4		T34	3		T33	5
len_1032	201	1			T6	1		T14	8		T15	2
len_1024	1777	1			T6	5		T5	1		T14	3
len_1016	185	1			T6	1		T15	2		T34	5
len_520	158	1			T41	1		T34	1		T33	3
len_512	333	1			T6	2		T4	1		T14	4
len_504	194	1			T6	1		T14	3		T41	2
len_8	890	1			T7	10		T41	1		T33	12
len_0	14630	1			T1	9		T2	3		T3	4

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

108

1

T5

1

T16

1

T34

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	46459	1			T1	7		T2	16		T3	3
auto[0]	len_1026_2046	3447	1			T2	4		T6	23		T4	1
auto[0]	len_514_1022	1811	1			T6	17		T16	16		T41	58
auto[0]	len_2_510	2069	1			T6	15		T14	4		T16	9
auto[0]	len_2056	96	1			T6	4		T33	1		T114	1
auto[0]	len_2048	204	1			T16	3		T128	1		T33	3
auto[0]	len_2040	98	1			T14	2		T34	3		T33	2
auto[0]	len_1032	101	1			T14	7		T15	1		T33	6
auto[0]	len_1024	249	1			T6	3		T14	2		T16	4
auto[0]	len_1016	84	1			T34	2		T33	2		T129	2
auto[0]	len_520	95	1			T41	1		T34	1		T33	2
auto[0]	len_512	209	1			T6	2		T4	1		T14	3
auto[0]	len_504	119	1			T14	2		T41	2		T33	8
auto[0]	len_8	16	1			T41	1		T65	1		T130	1
auto[0]	len_0	5373	1			T1	5		T2	2		T3	2
auto[1]	len_2050_plus	48411	1			T1	11		T2	7		T3	2
auto[1]	len_1026_2046	2268	1			T2	1		T6	28		T4	2
auto[1]	len_514_1022	1319	1			T6	5		T16	19		T32	1
auto[1]	len_2_510	982	1			T6	9		T14	2		T16	18
auto[1]	len_2056	78	1			T6	2		T34	2		T114	2
auto[1]	len_2048	159	1			T6	1		T5	1		T15	1
auto[1]	len_2040	76	1			T14	2		T33	3		T20	1
auto[1]	len_1032	100	1			T6	1		T14	1		T15	1
auto[1]	len_1024	1528	1			T6	2		T5	1		T14	1
auto[1]	len_1016	101	1			T6	1		T15	2		T34	3
auto[1]	len_520	63	1			T33	1		T29	2		T59	1
auto[1]	len_512	124	1			T14	1		T16	2		T34	1
auto[1]	len_504	75	1			T6	1		T14	1		T33	1
auto[1]	len_8	874	1			T7	10		T33	12		T131	9
auto[1]	len_0	9257	1			T1	4		T2	1		T3	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

52

1

T16

1

T29

1

T132

1

auto[1]

len_upper

56

1

T5

1

T34

2

T26

2