Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4173115 1 T1 2131 T2 1829 T3 2171
auto[1] 2513916 1 T1 2050 T2 4710 T3 303


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2545410 1 T1 2155 T2 3298 T3 1413
auto[1] 4141621 1 T1 2026 T2 3241 T3 1061


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3227654 1 T1 2607 T2 4666 T3 1699
auto[1] 3459377 1 T1 1574 T2 1873 T3 775


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4115216 1 T1 3498 T2 3306 T3 528
auto[1] 2571815 1 T1 683 T2 3233 T3 1946


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6011605 1 T1 4159 T2 5933 T3 2215
fifo_depth[1] 113490 1 T1 13 T2 142 T3 41
fifo_depth[2] 87578 1 T1 7 T2 127 T3 43
fifo_depth[3] 67610 1 T1 2 T2 139 T3 50
fifo_depth[4] 58715 1 T2 88 T3 31 T6 149
fifo_depth[5] 45144 1 T2 49 T3 29 T6 63
fifo_depth[6] 35606 1 T2 38 T3 27 T6 58
fifo_depth[7] 24090 1 T2 14 T3 17 T6 26


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 675426 1 T1 22 T2 606 T3 259
auto[1] 6011605 1 T1 4159 T2 5933 T3 2215


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6667909 1 T1 4181 T2 6539 T3 2474
auto[1] 19122 1 T16 422 T20 12 T28 34


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 25771 1 T2 2 T3 47 T6 217
auto[0] auto[0] auto[0] auto[0] auto[1] 26962 1 T2 45 T6 263 T4 1
auto[0] auto[0] auto[0] auto[1] auto[0] 26210 1 T2 192 T6 190 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] 29464 1 T2 120 T6 352 T5 1
auto[0] auto[0] auto[1] auto[0] auto[0] 166844 1 T1 18 T2 90 T6 219
auto[0] auto[0] auto[1] auto[0] auto[1] 23630 1 T3 107 T6 198 T4 2
auto[0] auto[0] auto[1] auto[1] auto[0] 44100 1 T6 116 T4 3 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] 31549 1 T2 86 T6 160 T4 1
auto[0] auto[1] auto[0] auto[0] auto[0] 32737 1 T6 168 T14 7 T16 333
auto[0] auto[1] auto[0] auto[0] auto[1] 46569 1 T1 2 T3 105 T6 221
auto[0] auto[1] auto[0] auto[1] auto[0] 36890 1 T6 22 T16 155 T34 2
auto[0] auto[1] auto[0] auto[1] auto[1] 39979 1 T6 251 T5 1 T15 8
auto[0] auto[1] auto[1] auto[0] auto[0] 39065 1 T6 100 T7 223 T4 1
auto[0] auto[1] auto[1] auto[0] auto[1] 32872 1 T2 65 T6 183 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] 37529 1 T1 2 T2 6 T6 141
auto[0] auto[1] auto[1] auto[1] auto[1] 35255 1 T6 222 T4 1 T5 1
auto[1] auto[0] auto[0] auto[0] auto[0] 175478 1 T1 535 T2 35 T3 462
auto[1] auto[0] auto[0] auto[0] auto[1] 170385 1 T1 1 T2 409 T3 432
auto[1] auto[0] auto[0] auto[1] auto[0] 164023 1 T1 879 T2 1007 T6 6695
auto[1] auto[0] auto[0] auto[1] auto[1] 169289 1 T1 2 T2 1111 T6 10167
auto[1] auto[0] auto[1] auto[0] auto[0] 1683760 1 T1 840 T2 170 T6 4956
auto[1] auto[0] auto[1] auto[0] auto[1] 157964 1 T1 2 T2 2 T3 651
auto[1] auto[0] auto[1] auto[1] auto[0] 155390 1 T2 1016 T6 5336 T4 2
auto[1] auto[0] auto[1] auto[1] auto[1] 176835 1 T1 330 T2 381 T6 4577
auto[1] auto[1] auto[0] auto[0] auto[0] 358272 1 T1 387 T2 371 T3 18
auto[1] auto[1] auto[0] auto[0] auto[1] 408309 1 T1 344 T2 2 T3 349
auto[1] auto[1] auto[0] auto[1] auto[0] 414548 1 T1 3 T6 3079 T7 4190
auto[1] auto[1] auto[0] auto[1] auto[1] 420524 1 T1 2 T2 4 T6 5082
auto[1] auto[1] auto[1] auto[0] auto[0] 432740 1 T1 2 T2 2 T6 6317
auto[1] auto[1] auto[1] auto[0] auto[1] 391757 1 T2 636 T6 7110 T7 1712
auto[1] auto[1] auto[1] auto[1] auto[0] 321859 1 T1 832 T2 415 T3 1
auto[1] auto[1] auto[1] auto[1] auto[1] 410472 1 T2 372 T3 302 T6 6948


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 200571 1 T1 535 T2 37 T3 509
auto[0] auto[0] auto[0] auto[0] auto[1] 194973 1 T1 1 T2 454 T3 432
auto[0] auto[0] auto[0] auto[1] auto[0] 189719 1 T1 879 T2 1199 T6 6885
auto[0] auto[0] auto[0] auto[1] auto[1] 196983 1 T1 2 T2 1231 T6 10519
auto[0] auto[0] auto[1] auto[0] auto[0] 1850336 1 T1 858 T2 260 T6 5175
auto[0] auto[0] auto[1] auto[0] auto[1] 179815 1 T1 2 T2 2 T3 758
auto[0] auto[0] auto[1] auto[1] auto[0] 193821 1 T2 1016 T6 5452 T4 5
auto[0] auto[0] auto[1] auto[1] auto[1] 206642 1 T1 330 T2 467 T6 4737
auto[0] auto[1] auto[0] auto[0] auto[0] 390315 1 T1 387 T2 371 T3 18
auto[0] auto[1] auto[0] auto[0] auto[1] 454480 1 T1 346 T2 2 T3 454
auto[0] auto[1] auto[0] auto[1] auto[0] 450890 1 T1 3 T6 3101 T7 4190
auto[0] auto[1] auto[0] auto[1] auto[1] 459932 1 T1 2 T2 4 T6 5333
auto[0] auto[1] auto[1] auto[0] auto[0] 471660 1 T1 2 T2 2 T6 6417
auto[0] auto[1] auto[1] auto[0] auto[1] 424568 1 T2 701 T6 7293 T7 1712
auto[0] auto[1] auto[1] auto[1] auto[0] 357565 1 T1 834 T2 421 T3 1
auto[0] auto[1] auto[1] auto[1] auto[1] 445639 1 T2 372 T3 302 T6 7170
auto[1] auto[0] auto[0] auto[0] auto[0] 678 1 T16 2 T132 6 T133 54
auto[1] auto[0] auto[0] auto[0] auto[1] 2374 1 T16 339 T134 56 T135 56
auto[1] auto[0] auto[0] auto[1] auto[0] 514 1 T28 4 T134 34 T136 24
auto[1] auto[0] auto[0] auto[1] auto[1] 1770 1 T16 3 T136 1514 T137 12
auto[1] auto[0] auto[1] auto[0] auto[0] 268 1 T28 8 T132 24 T133 12
auto[1] auto[0] auto[1] auto[0] auto[1] 1779 1 T16 1 T136 49 T138 1396
auto[1] auto[0] auto[1] auto[1] auto[0] 5669 1 T16 17 T20 9 T132 1
auto[1] auto[0] auto[1] auto[1] auto[1] 1742 1 T28 2 T132 2 T135 1380
auto[1] auto[1] auto[0] auto[0] auto[0] 694 1 T13 24 T139 318 T140 34
auto[1] auto[1] auto[0] auto[0] auto[1] 398 1 T16 46 T28 18 T132 15
auto[1] auto[1] auto[0] auto[1] auto[0] 548 1 T134 162 T141 88 T136 3
auto[1] auto[1] auto[0] auto[1] auto[1] 571 1 T16 8 T28 2 T134 1
auto[1] auto[1] auto[1] auto[0] auto[0] 145 1 T16 6 T20 3 T134 1
auto[1] auto[1] auto[1] auto[0] auto[1] 61 1 T134 1 T141 40 T136 1
auto[1] auto[1] auto[1] auto[1] auto[0] 1823 1 T135 52 T136 12 T142 1
auto[1] auto[1] auto[1] auto[1] auto[1] 88 1 T133 10 T136 1 T138 2


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 175478 1 T1 535 T2 35 T3 462
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 170385 1 T1 1 T2 409 T3 432
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 164023 1 T1 879 T2 1007 T6 6695
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 169289 1 T1 2 T2 1111 T6 10167
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1683760 1 T1 840 T2 170 T6 4956
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 157964 1 T1 2 T2 2 T3 651
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 155390 1 T2 1016 T6 5336 T4 2
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 176835 1 T1 330 T2 381 T6 4577
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 358272 1 T1 387 T2 371 T3 18
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 408309 1 T1 344 T2 2 T3 349
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 414548 1 T1 3 T6 3079 T7 4190
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 420524 1 T1 2 T2 4 T6 5082
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 432740 1 T1 2 T2 2 T6 6317
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 391757 1 T2 636 T6 7110 T7 1712
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 321859 1 T1 832 T2 415 T3 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 410472 1 T2 372 T3 302 T6 6948
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3406 1 T3 10 T6 122 T14 3
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3112 1 T2 15 T6 82 T5 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3025 1 T2 34 T6 108 T16 84
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3472 1 T2 43 T6 169 T16 1
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 46082 1 T1 10 T2 12 T6 151
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 2650 1 T3 22 T6 102 T34 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3030 1 T6 68 T4 1 T143 5
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3498 1 T2 19 T6 101 T16 3
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 5596 1 T6 98 T14 1 T16 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 5798 1 T1 1 T3 9 T6 121
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5664 1 T6 13 T16 3 T144 13
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5974 1 T6 82 T15 1 T16 54
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 6597 1 T6 57 T7 37 T4 1
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5021 1 T2 18 T6 106 T15 1
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 4716 1 T1 2 T2 1 T6 72
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5849 1 T6 135 T16 2 T33 23
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2541 1 T2 1 T3 9 T6 52
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2251 1 T2 11 T6 56 T15 2
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2230 1 T2 30 T6 62 T16 89
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2768 1 T2 35 T6 101 T16 1
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 34419 1 T1 6 T2 12 T6 53
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 1972 1 T3 15 T6 50 T128 1
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2386 1 T6 35 T15 2 T144 27
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2756 1 T2 14 T6 34 T14 1
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4801 1 T6 43 T14 1 T16 19
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 4663 1 T1 1 T3 19 T6 59
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4545 1 T6 7 T16 27 T144 11
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4715 1 T6 48 T16 57 T32 11
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 4953 1 T6 29 T7 52 T14 6
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4361 1 T2 21 T6 48 T16 4
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 3748 1 T2 3 T6 53 T16 4
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4469 1 T6 58 T16 32 T128 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1738 1 T3 10 T6 11 T14 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1612 1 T2 14 T6 35 T144 16
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1656 1 T2 39 T6 19 T16 92
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2062 1 T2 31 T6 25 T5 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 25418 1 T1 2 T2 18 T6 12
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1441 1 T3 25 T6 30 T4 1
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1731 1 T6 12 T15 1 T144 8
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 1900 1 T2 15 T6 14 T14 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4185 1 T6 20 T16 5 T144 4
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 3824 1 T3 15 T6 22 T14 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3694 1 T6 1 T16 4 T34 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3802 1 T6 34 T15 1 T16 50
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 3753 1 T6 10 T7 43 T14 3
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3625 1 T2 20 T6 15 T16 6
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 3289 1 T2 2 T6 13 T14 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3880 1 T6 25 T16 8 T33 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 1805 1 T3 3 T6 12 T14 3
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1626 1 T2 4 T6 24 T15 1
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 1571 1 T2 35 T6 1 T16 90
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2108 1 T2 11 T6 39 T16 10
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 17434 1 T2 17 T6 3 T14 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1359 1 T3 15 T6 11 T16 5
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1755 1 T4 1 T15 1 T144 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2002 1 T2 16 T6 7 T14 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4044 1 T6 5 T14 1 T16 22
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 3725 1 T3 13 T6 9 T32 11
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3554 1 T6 1 T16 26 T20 64
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3649 1 T6 23 T15 1 T16 50
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 3778 1 T6 2 T7 30 T14 5
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3477 1 T2 5 T6 8 T16 4
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 3249 1 T14 2 T15 1 T16 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3579 1 T6 4 T16 32 T33 4
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1233 1 T2 1 T3 5 T6 4
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1065 1 T2 1 T6 27 T16 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1330 1 T2 25 T16 49 T32 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1503 1 T6 2 T16 18 T33 5
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 12005 1 T2 12 T16 5 T33 3
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1086 1 T3 13 T6 2 T5 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1468 1 T6 1 T5 1 T16 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1491 1 T2 9 T40 1 T20 12
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3414 1 T6 2 T14 1 T16 7
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3001 1 T3 11 T6 5 T32 17
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 2928 1 T16 5 T34 1 T17 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3082 1 T6 18 T15 2 T16 54
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 2864 1 T6 2 T7 29 T14 5
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 2937 1 T2 1 T16 6 T32 20
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2606 1 T14 4 T15 1 T131 107
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3131 1 T16 4 T81 18 T131 102
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1115 1 T3 5 T6 9 T14 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 918 1 T6 21 T4 1 T15 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1060 1 T2 18 T16 12 T33 5
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1324 1 T6 2 T16 3 T33 3
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 8258 1 T2 10 T14 1 T16 23
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 904 1 T3 11 T6 2 T16 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1141 1 T20 8 T24 6 T29 19
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1289 1 T2 10 T6 2 T4 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2680 1 T14 1 T16 26 T33 3
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2579 1 T3 11 T6 3 T4 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2350 1 T16 26 T20 55 T35 29
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2546 1 T6 15 T5 1 T16 40
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 2501 1 T7 19 T14 3 T15 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2397 1 T6 3 T15 1 T16 6
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 2140 1 T6 1 T14 3 T15 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2404 1 T16 33 T33 1 T81 11
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 672 1 T3 2 T6 2 T14 1
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 639 1 T6 12 T5 1 T20 12
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 802 1 T2 7 T16 9 T32 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 885 1 T6 1 T16 18 T33 1
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 5059 1 T2 6 T15 1 T16 11
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 625 1 T3 5 T6 1 T16 13
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 945 1 T4 1 T16 17 T20 11
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 875 1 T2 1 T16 2 T40 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1800 1 T14 1 T16 4 T80 24
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1979 1 T3 10 T32 10 T33 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1658 1 T16 1 T20 47 T35 20
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1787 1 T6 10 T15 1 T16 12
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 1560 1 T7 7 T14 3 T15 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1601 1 T5 1 T16 6 T32 8
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1469 1 T14 2 T15 1 T40 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1734 1 T16 1 T81 9 T131 40

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