Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16754225	1			T1	22897		T2	34900		T3	4990
all_pins[1]	16754225	1			T1	22897		T2	34900		T3	4990
all_pins[2]	16754225	1			T1	22897		T2	34900		T3	4990

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	42836626	1			T1	55123		T2	81564		T3	13160
values[0x1]	7426049	1			T1	13568		T2	23136		T3	1810
transitions[0x0=>0x1]	7425922	1			T1	13568		T2	23136		T3	1810
transitions[0x1=>0x0]	7425935	1			T1	13568		T2	23136		T3	1810

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16734544	1			T1	22891		T2	34887		T3	4984
all_pins[0]	values[0x1]	19681	1			T1	6		T2	13		T3	6
all_pins[0]	transitions[0x0=>0x1]	19625	1			T1	6		T2	13		T3	6
all_pins[0]	transitions[0x1=>0x0]	7406019	1			T1	13562		T2	23123		T3	1804
all_pins[1]	values[0x0]	16753919	1			T1	22897		T2	34900		T3	4990
all_pins[1]	values[0x1]	306	1			T16	5		T33	4		T28	2
all_pins[1]	transitions[0x0=>0x1]	269	1			T16	5		T33	3		T28	2
all_pins[1]	transitions[0x1=>0x0]	19644	1			T1	6		T2	13		T3	6
all_pins[2]	values[0x0]	9348163	1			T1	9335		T2	11777		T3	3186
all_pins[2]	values[0x1]	7406062	1			T1	13562		T2	23123		T3	1804
all_pins[2]	transitions[0x0=>0x1]	7406028	1			T1	13562		T2	23123		T3	1804
all_pins[2]	transitions[0x1=>0x0]	272	1			T16	5		T33	2		T28	2