Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 804 1 T33 22 T29 15 T59 4
all_values[1] 804 1 T33 22 T29 15 T59 4
all_values[2] 804 1 T33 22 T29 15 T59 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1298 1 T33 26 T29 24 T59 4
auto[1] 1114 1 T33 40 T29 21 T59 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 914 1 T33 23 T29 20 T59 2
auto[1] 1498 1 T33 43 T29 25 T59 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1383 1 T33 38 T29 29 T59 4
auto[1] 1029 1 T33 28 T29 16 T59 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 162 1 T33 5 T29 5 T72 3
all_values[0] auto[0] auto[0] auto[1] 72 1 T29 1 T49 1 T72 2
all_values[0] auto[0] auto[1] auto[0] 160 1 T33 3 T29 6 T49 2
all_values[0] auto[0] auto[1] auto[1] 68 1 T33 4 T59 1 T72 2
all_values[0] auto[1] auto[0] auto[1] 174 1 T33 4 T29 2 T59 2
all_values[0] auto[1] auto[1] auto[1] 168 1 T33 6 T29 1 T59 1
all_values[1] auto[0] auto[0] auto[0] 150 1 T33 4 T29 3 T59 1
all_values[1] auto[0] auto[0] auto[1] 107 1 T33 3 T29 3 T49 1
all_values[1] auto[0] auto[1] auto[0] 111 1 T33 4 T29 3 T49 4
all_values[1] auto[0] auto[1] auto[1] 92 1 T33 2 T29 1 T59 1
all_values[1] auto[1] auto[0] auto[1] 197 1 T33 4 T29 4 T59 1
all_values[1] auto[1] auto[1] auto[1] 147 1 T33 5 T29 1 T59 1
all_values[2] auto[0] auto[0] auto[0] 180 1 T49 1 T72 3 T64 4
all_values[2] auto[0] auto[0] auto[1] 71 1 T33 3 T29 4 T49 2
all_values[2] auto[0] auto[1] auto[0] 151 1 T33 7 T29 3 T59 1
all_values[2] auto[0] auto[1] auto[1] 59 1 T33 3 T72 2 T115 3
all_values[2] auto[1] auto[0] auto[1] 185 1 T33 3 T29 2 T72 3
all_values[2] auto[1] auto[1] auto[1] 158 1 T33 6 T29 6 T59 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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