Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3906	1			T1	8		T2	4		T3	3
sha2_none	3870	1			T1	9		T2	3		T3	2
sha2_512	7330	1			T1	6		T2	11		T3	3
sha2_384	7098	1			T1	5		T2	9		T6	96
sha2_256	5856	1			T1	2		T2	1		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17888

1

T1

14

T2

16

T3

8

auto[1]

10531

1

T1

16

T2

13

T3

2

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10516

1

T1

15

T2

16

T3

6

auto[1]

17903

1

T1

15

T2

13

T3

4

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14374

1

T1

19

T2

11

T3

5

disabled

14045

1

T1

11

T2

18

T3

5

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4323	1			T1	14		T2	7		T3	2
key_none	7472	1			T1	1		T2	3		T6	52
key_1024	4175	1			T1	2		T2	1		T3	3
key_512	3528	1			T1	3		T2	2		T3	1
key_384	3212	1			T1	3		T2	5		T3	2
key_256	2883	1			T1	3		T2	5		T3	1
key_128	2739	1			T1	3		T2	6		T3	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17954

1

T1

20

T2

16

T3

5

auto[1]

10465

1

T1

10

T2

13

T3

5

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28188

1

T1

27

T2

27

T3

10

disabled

231

1

T1

3

T2

2

T6

6

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1450

1

T1

3

T2

2

T3

2

enabled

auto[0]

auto[0]

auto[1]

1518

1

T1

2

T2

2

T3

1

enabled

auto[0]

auto[1]

auto[0]

1438

1

T1

3

T6

27

T7

2

enabled

auto[0]

auto[1]

auto[1]

1476

1

T1

3

T2

2

T6

21

enabled

auto[1]

auto[0]

auto[0]

4101

1

T1

3

T2

1

T6

31

enabled

auto[1]

auto[0]

auto[1]

1438

1

T2

1

T6

32

T7

3

enabled

auto[1]

auto[1]

auto[0]

1472

1

T1

4

T2

2

T3

1

enabled

auto[1]

auto[1]

auto[1]

1481

1

T1

1

T2

1

T3

1

disabled

auto[0]

auto[0]

auto[0]

1161

1

T1

2

T2

2

T3

2

disabled

auto[0]

auto[0]

auto[1]

1138

1

T2

4

T3

1

T6

31

disabled

auto[0]

auto[1]

auto[0]

1195

1

T1

1

T2

2

T6

29

disabled

auto[0]

auto[1]

auto[1]

1140

1

T1

1

T2

2

T6

36

disabled

auto[1]

auto[0]

auto[0]

5986

1

T1

3

T2

4

T6

25

disabled

auto[1]

auto[0]

auto[1]

1096

1

T1

1

T3

2

T6

26

disabled

auto[1]

auto[1]

auto[0]

1151

1

T1

1

T2

3

T6

26

disabled

auto[1]

auto[1]

auto[1]

1178

1

T1

2

T2

1

T6

26

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14289

1

T1

18

T2

11

T3

5

enabled

disabled

85

1

T1

1

T6

2

T127

1

disabled

disabled

146

1

T1

2

T2

2

T6

4

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13899

1

T1

9

T2

16

T3

5

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1034	1			T1	5		T2	3		T6	22
key_invalid	sha2_none	806	1			T1	5		T6	16		T7	1
key_invalid	sha2_512	817	1			T1	3		T3	2		T6	14
key_invalid	sha2_384	796	1			T1	1		T2	3		T6	12
key_invalid	sha2_256	773	1			T6	22		T7	1		T4	1
key_none	sha2_invalid	465	1			T6	10		T4	1		T5	3
key_none	sha2_none	468	1			T1	1		T2	1		T6	8
key_none	sha2_512	2480	1			T2	1		T6	6		T7	2
key_none	sha2_384	2499	1			T2	1		T6	16		T5	2
key_none	sha2_256	1515	1			T6	11		T7	2		T4	4
key_1024	sha2_invalid	493	1			T3	1		T6	13		T4	1
key_1024	sha2_none	505	1			T1	1		T3	1		T6	11
key_1024	sha2_512	1724	1			T1	1		T2	1		T6	11
key_1024	sha2_384	860	1			T6	14		T4	2		T5	4
key_512	sha2_invalid	482	1			T1	2		T2	1		T3	1
key_512	sha2_none	527	1			T6	19		T4	1		T5	2
key_512	sha2_512	566	1			T6	12		T4	2		T5	2
key_512	sha2_384	1161	1			T1	1		T2	1		T6	14
key_512	sha2_256	756	1			T6	8		T7	1		T4	1
key_384	sha2_invalid	484	1			T3	1		T6	10		T14	1
key_384	sha2_none	516	1			T1	1		T2	1		T6	14
key_384	sha2_512	559	1			T1	1		T6	8		T7	1
key_384	sha2_384	598	1			T2	3		T6	14		T14	2
key_384	sha2_256	1002	1			T1	1		T2	1		T3	1
key_256	sha2_invalid	450	1			T6	6		T14	3		T15	1
key_256	sha2_none	523	1			T1	1		T3	1		T6	11
key_256	sha2_512	591	1			T2	4		T6	16		T7	1
key_256	sha2_384	626	1			T1	2		T2	1		T6	18
key_256	sha2_256	651	1			T6	15		T7	1		T4	2
key_128	sha2_invalid	482	1			T6	13		T4	2		T14	1
key_128	sha2_none	504	1			T2	1		T6	9		T7	2
key_128	sha2_512	583	1			T1	1		T2	5		T3	1
key_128	sha2_384	544	1			T1	1		T6	8		T5	2
key_128	sha2_256	587	1			T1	1		T6	13		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

548

1

T3

1

T6

12

T7

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1034	1			T1	5		T2	3		T6	22
key_invalid	sha2_none	806	1			T1	5		T6	16		T7	1
key_invalid	sha2_512	817	1			T1	3		T3	2		T6	14
key_invalid	sha2_384	796	1			T1	1		T2	3		T6	12
key_invalid	sha2_256	773	1			T6	22		T7	1		T4	1
key_none	sha2_invalid	465	1			T6	10		T4	1		T5	3
key_none	sha2_none	468	1			T1	1		T2	1		T6	8
key_none	sha2_512	2480	1			T2	1		T6	6		T7	2
key_none	sha2_384	2499	1			T2	1		T6	16		T5	2
key_none	sha2_256	1515	1			T6	11		T7	2		T4	4
key_1024	sha2_invalid	493	1			T3	1		T6	13		T4	1
key_1024	sha2_none	505	1			T1	1		T3	1		T6	11
key_1024	sha2_512	1724	1			T1	1		T2	1		T6	11
key_1024	sha2_384	860	1			T6	14		T4	2		T5	4
key_1024	sha2_256	548	1			T3	1		T6	12		T7	1
key_512	sha2_invalid	482	1			T1	2		T2	1		T3	1
key_512	sha2_none	527	1			T6	19		T4	1		T5	2
key_512	sha2_512	566	1			T6	12		T4	2		T5	2
key_512	sha2_384	1161	1			T1	1		T2	1		T6	14
key_512	sha2_256	756	1			T6	8		T7	1		T4	1
key_384	sha2_invalid	484	1			T3	1		T6	10		T14	1
key_384	sha2_none	516	1			T1	1		T2	1		T6	14
key_384	sha2_512	559	1			T1	1		T6	8		T7	1
key_384	sha2_384	598	1			T2	3		T6	14		T14	2
key_384	sha2_256	1002	1			T1	1		T2	1		T3	1
key_256	sha2_invalid	450	1			T6	6		T14	3		T15	1
key_256	sha2_none	523	1			T1	1		T3	1		T6	11
key_256	sha2_512	591	1			T2	4		T6	16		T7	1
key_256	sha2_384	626	1			T1	2		T2	1		T6	18
key_256	sha2_256	651	1			T6	15		T7	1		T4	2
key_128	sha2_invalid	482	1			T6	13		T4	2		T14	1
key_128	sha2_none	504	1			T2	1		T6	9		T7	2
key_128	sha2_512	583	1			T1	1		T2	5		T3	1
key_128	sha2_384	544	1			T1	1		T6	8		T5	2
key_128	sha2_256	587	1			T1	1		T6	13		T4	2