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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.93 95.26 97.22 100.00 97.06 98.12 97.97 99.85


Total test records in report: 653
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T90 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4057622194 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:48 PM PDT 24 742876593 ps
T91 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3900244540 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:48 PM PDT 24 27731611 ps
T107 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1314835463 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:50 PM PDT 24 35036047 ps
T533 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1886489224 Aug 18 05:47:04 PM PDT 24 Aug 18 05:47:05 PM PDT 24 39362664 ps
T534 /workspace/coverage/cover_reg_top/46.hmac_intr_test.346368006 Aug 18 05:47:09 PM PDT 24 Aug 18 05:47:09 PM PDT 24 14730522 ps
T535 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2343178372 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 26216150 ps
T63 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1742151236 Aug 18 05:46:31 PM PDT 24 Aug 18 05:46:32 PM PDT 24 42758709 ps
T84 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3680119250 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:41 PM PDT 24 126250907 ps
T92 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1321302908 Aug 18 05:47:06 PM PDT 24 Aug 18 05:47:07 PM PDT 24 16439279 ps
T108 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1792639562 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:41 PM PDT 24 35994553 ps
T536 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3003360007 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 13835355 ps
T537 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2839705435 Aug 18 05:46:38 PM PDT 24 Aug 18 05:46:38 PM PDT 24 31910854 ps
T538 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3351008939 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 38884195 ps
T539 /workspace/coverage/cover_reg_top/1.hmac_intr_test.51049441 Aug 18 05:46:35 PM PDT 24 Aug 18 05:46:36 PM PDT 24 42176104 ps
T540 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.382011726 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:51 PM PDT 24 70875914 ps
T541 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2443388578 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:52 PM PDT 24 47852560 ps
T109 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.799431026 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:45 PM PDT 24 53682042 ps
T542 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2418548243 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:52 PM PDT 24 21573111 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3334946607 Aug 18 05:47:02 PM PDT 24 Aug 18 05:47:04 PM PDT 24 467769040 ps
T543 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2843186287 Aug 18 05:46:45 PM PDT 24 Aug 18 05:46:47 PM PDT 24 295402382 ps
T544 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1772151955 Aug 18 05:47:03 PM PDT 24 Aug 18 05:47:04 PM PDT 24 30710916 ps
T545 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2294014152 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:05 PM PDT 24 16919604 ps
T119 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.539609839 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:47 PM PDT 24 222367720 ps
T124 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3153809658 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:53 PM PDT 24 569987534 ps
T116 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1453621206 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:45 PM PDT 24 624616266 ps
T546 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2621770329 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:40 PM PDT 24 16450153 ps
T547 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.347991128 Aug 18 05:46:46 PM PDT 24 Aug 18 05:46:48 PM PDT 24 405852526 ps
T548 /workspace/coverage/cover_reg_top/12.hmac_intr_test.471881745 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:49 PM PDT 24 29697661 ps
T549 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.343659182 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:55 PM PDT 24 470471835 ps
T550 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.116766779 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:52 PM PDT 24 177868941 ps
T93 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.702794838 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:44 PM PDT 24 20674079 ps
T111 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3119736060 Aug 18 05:46:56 PM PDT 24 Aug 18 05:46:57 PM PDT 24 25721885 ps
T94 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3712589317 Aug 18 05:46:33 PM PDT 24 Aug 18 05:46:36 PM PDT 24 306457939 ps
T551 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3374716620 Aug 18 05:46:46 PM PDT 24 Aug 18 05:46:49 PM PDT 24 111223354 ps
T552 /workspace/coverage/cover_reg_top/31.hmac_intr_test.228879070 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 16150310 ps
T120 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2888732467 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:51 PM PDT 24 81585554 ps
T95 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3548572672 Aug 18 05:46:35 PM PDT 24 Aug 18 05:46:43 PM PDT 24 1996689581 ps
T553 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2430876897 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:53 PM PDT 24 96358938 ps
T554 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2269311529 Aug 18 05:47:06 PM PDT 24 Aug 18 05:47:07 PM PDT 24 28281967 ps
T555 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1174139327 Aug 18 05:47:08 PM PDT 24 Aug 18 05:47:08 PM PDT 24 17726170 ps
T556 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2707845631 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:53 PM PDT 24 289718817 ps
T557 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.486071290 Aug 18 05:46:34 PM PDT 24 Aug 18 05:46:37 PM PDT 24 321864374 ps
T558 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1746608400 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:44 PM PDT 24 16215694 ps
T559 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1302032492 Aug 18 05:46:32 PM PDT 24 Aug 18 05:46:33 PM PDT 24 57736650 ps
T96 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3285963417 Aug 18 05:46:45 PM PDT 24 Aug 18 05:46:45 PM PDT 24 294775954 ps
T560 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3961323864 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:44 PM PDT 24 108821679 ps
T561 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2088776638 Aug 18 05:46:50 PM PDT 24 Aug 18 05:46:53 PM PDT 24 677407581 ps
T562 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2468635109 Aug 18 05:46:52 PM PDT 24 Aug 18 05:46:53 PM PDT 24 291011467 ps
T563 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.90930068 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:41 PM PDT 24 32679419 ps
T125 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2643261237 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:47 PM PDT 24 244406159 ps
T564 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3364354811 Aug 18 05:47:06 PM PDT 24 Aug 18 05:47:09 PM PDT 24 129414461 ps
T97 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1004366330 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:49 PM PDT 24 28250028 ps
T565 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2388062658 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:43 PM PDT 24 735839957 ps
T98 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4085250188 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:48 PM PDT 24 25079689 ps
T566 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2854607839 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:46 PM PDT 24 718704016 ps
T567 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1733716923 Aug 18 05:46:44 PM PDT 24 Aug 18 05:46:48 PM PDT 24 206264555 ps
T568 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2509154447 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:51 PM PDT 24 412727038 ps
T569 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2639634434 Aug 18 05:47:03 PM PDT 24 Aug 18 05:47:04 PM PDT 24 137473228 ps
T570 /workspace/coverage/cover_reg_top/48.hmac_intr_test.394142645 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 19360493 ps
T571 /workspace/coverage/cover_reg_top/34.hmac_intr_test.808410486 Aug 18 05:47:02 PM PDT 24 Aug 18 05:47:03 PM PDT 24 41424348 ps
T121 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4071410455 Aug 18 05:46:55 PM PDT 24 Aug 18 05:46:58 PM PDT 24 141053278 ps
T572 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1435690063 Aug 18 05:46:34 PM PDT 24 Aug 18 05:46:48 PM PDT 24 1272323181 ps
T573 /workspace/coverage/cover_reg_top/26.hmac_intr_test.610804364 Aug 18 05:47:03 PM PDT 24 Aug 18 05:47:04 PM PDT 24 25812665 ps
T574 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1026033778 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:51 PM PDT 24 17642029 ps
T575 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1704685574 Aug 18 05:46:54 PM PDT 24 Aug 18 05:46:57 PM PDT 24 501412573 ps
T576 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.624898702 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:53 PM PDT 24 329240448 ps
T577 /workspace/coverage/cover_reg_top/39.hmac_intr_test.339453707 Aug 18 05:47:04 PM PDT 24 Aug 18 05:47:05 PM PDT 24 18261436 ps
T578 /workspace/coverage/cover_reg_top/21.hmac_intr_test.4216875193 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 18986957 ps
T579 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.598453293 Aug 18 05:46:44 PM PDT 24 Aug 18 05:46:46 PM PDT 24 132560471 ps
T580 /workspace/coverage/cover_reg_top/35.hmac_intr_test.4141772725 Aug 18 05:47:04 PM PDT 24 Aug 18 05:47:05 PM PDT 24 38577730 ps
T581 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1226406138 Aug 18 05:46:56 PM PDT 24 Aug 18 05:46:57 PM PDT 24 22297875 ps
T99 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2332126396 Aug 18 05:46:35 PM PDT 24 Aug 18 05:46:51 PM PDT 24 5805727849 ps
T582 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1264435075 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:49 PM PDT 24 1585128206 ps
T583 /workspace/coverage/cover_reg_top/32.hmac_intr_test.4000469275 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 20690864 ps
T584 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2676669766 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 27784961 ps
T585 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1001281659 Aug 18 05:47:03 PM PDT 24 Aug 18 05:47:04 PM PDT 24 14736032 ps
T586 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2727287474 Aug 18 05:47:04 PM PDT 24 Aug 18 05:47:05 PM PDT 24 118777418 ps
T587 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.107536165 Aug 18 05:47:01 PM PDT 24 Aug 18 05:47:02 PM PDT 24 38209246 ps
T588 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1163310528 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:44 PM PDT 24 22361625 ps
T126 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1410907866 Aug 18 05:46:56 PM PDT 24 Aug 18 05:47:00 PM PDT 24 239430497 ps
T589 /workspace/coverage/cover_reg_top/18.hmac_intr_test.1137580498 Aug 18 05:46:58 PM PDT 24 Aug 18 05:46:59 PM PDT 24 49816021 ps
T590 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2827626678 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:50 PM PDT 24 152465251 ps
T591 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1459995906 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:50 PM PDT 24 163020929 ps
T101 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2470413738 Aug 18 05:46:59 PM PDT 24 Aug 18 05:47:00 PM PDT 24 101997512 ps
T592 /workspace/coverage/cover_reg_top/27.hmac_intr_test.689441534 Aug 18 05:47:07 PM PDT 24 Aug 18 05:47:08 PM PDT 24 16116396 ps
T593 /workspace/coverage/cover_reg_top/38.hmac_intr_test.4059475926 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 58509569 ps
T100 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.386407646 Aug 18 05:46:43 PM PDT 24 Aug 18 05:47:00 PM PDT 24 1641936980 ps
T594 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1056247398 Aug 18 05:46:50 PM PDT 24 Aug 18 05:52:11 PM PDT 24 32629415055 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.988383804 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 97897595 ps
T596 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4069113999 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:50 PM PDT 24 62215546 ps
T122 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4172453837 Aug 18 05:46:36 PM PDT 24 Aug 18 05:46:40 PM PDT 24 910012936 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2309301660 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:45 PM PDT 24 526761984 ps
T598 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1497832937 Aug 18 05:47:07 PM PDT 24 Aug 18 05:47:08 PM PDT 24 49594120 ps
T102 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2251968596 Aug 18 05:46:37 PM PDT 24 Aug 18 05:46:38 PM PDT 24 21528455 ps
T599 /workspace/coverage/cover_reg_top/47.hmac_intr_test.628110208 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 14731053 ps
T600 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1812722216 Aug 18 05:46:45 PM PDT 24 Aug 18 05:46:46 PM PDT 24 61397711 ps
T601 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2180160765 Aug 18 05:46:46 PM PDT 24 Aug 18 05:46:46 PM PDT 24 23803065 ps
T602 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1243403269 Aug 18 05:47:07 PM PDT 24 Aug 18 05:47:07 PM PDT 24 26379262 ps
T603 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1719108286 Aug 18 05:46:56 PM PDT 24 Aug 18 05:47:00 PM PDT 24 260444617 ps
T604 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2643188256 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:47 PM PDT 24 610565235 ps
T605 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1265077776 Aug 18 05:46:57 PM PDT 24 Aug 18 05:46:58 PM PDT 24 76582589 ps
T103 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2075521613 Aug 18 05:46:44 PM PDT 24 Aug 18 05:46:45 PM PDT 24 57775943 ps
T606 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1092296809 Aug 18 05:46:59 PM PDT 24 Aug 18 05:47:00 PM PDT 24 21755520 ps
T607 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3172256561 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:49 PM PDT 24 23117609 ps
T608 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3638325825 Aug 18 05:47:02 PM PDT 24 Aug 18 05:47:02 PM PDT 24 20154993 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2333322200 Aug 18 05:46:33 PM PDT 24 Aug 18 05:46:35 PM PDT 24 62951126 ps
T610 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.47231284 Aug 18 05:46:45 PM PDT 24 Aug 18 05:46:46 PM PDT 24 24051655 ps
T611 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3579135410 Aug 18 05:46:56 PM PDT 24 Aug 18 05:46:57 PM PDT 24 64970237 ps
T612 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1852843010 Aug 18 05:47:06 PM PDT 24 Aug 18 05:47:09 PM PDT 24 981938953 ps
T613 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.604532403 Aug 18 05:46:57 PM PDT 24 Aug 18 05:47:00 PM PDT 24 88013428 ps
T614 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1217955957 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:50 PM PDT 24 34317723 ps
T615 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3392593952 Aug 18 05:46:34 PM PDT 24 Aug 18 05:46:35 PM PDT 24 187643666 ps
T616 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1503577680 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:43 PM PDT 24 73845157 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.19542298 Aug 18 05:46:31 PM PDT 24 Aug 18 05:46:32 PM PDT 24 117403526 ps
T618 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4233124873 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:49 PM PDT 24 264163990 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3869114793 Aug 18 05:46:45 PM PDT 24 Aug 18 05:46:47 PM PDT 24 259941816 ps
T620 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4029027377 Aug 18 05:46:33 PM PDT 24 Aug 18 05:46:34 PM PDT 24 15949506 ps
T621 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3712918904 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:43 PM PDT 24 29856390 ps
T622 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2697919422 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:40 PM PDT 24 105557014 ps
T623 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4255106114 Aug 18 05:46:32 PM PDT 24 Aug 18 05:57:06 PM PDT 24 176512613056 ps
T624 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2349882472 Aug 18 05:46:51 PM PDT 24 Aug 18 05:46:52 PM PDT 24 81025407 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3830643184 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:43 PM PDT 24 810676851 ps
T626 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1193696558 Aug 18 05:46:54 PM PDT 24 Aug 18 05:46:54 PM PDT 24 39717897 ps
T627 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1918108043 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:05 PM PDT 24 30262296 ps
T628 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2163454667 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:45 PM PDT 24 53096793 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3687903909 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:50 PM PDT 24 140530605 ps
T630 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2112471773 Aug 18 05:47:07 PM PDT 24 Aug 18 05:47:08 PM PDT 24 11517093 ps
T631 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2601304973 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 100003467 ps
T632 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1609387202 Aug 18 05:46:58 PM PDT 24 Aug 18 05:47:01 PM PDT 24 395343366 ps
T633 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1864510191 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:45 PM PDT 24 1111726935 ps
T634 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2780205721 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:40 PM PDT 24 847752162 ps
T635 /workspace/coverage/cover_reg_top/14.hmac_intr_test.86431308 Aug 18 05:46:50 PM PDT 24 Aug 18 05:46:51 PM PDT 24 15097801 ps
T636 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2863621674 Aug 18 05:46:49 PM PDT 24 Aug 18 05:46:50 PM PDT 24 45630104 ps
T637 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3511024723 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:44 PM PDT 24 277894959 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2106841277 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:55 PM PDT 24 2107176916 ps
T639 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2039226444 Aug 18 05:46:34 PM PDT 24 Aug 18 05:46:36 PM PDT 24 54953734 ps
T640 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2232641165 Aug 18 05:46:34 PM PDT 24 Aug 18 05:54:20 PM PDT 24 50771145218 ps
T641 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3669814944 Aug 18 05:46:47 PM PDT 24 Aug 18 05:46:50 PM PDT 24 54321859 ps
T642 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.868786139 Aug 18 05:47:01 PM PDT 24 Aug 18 05:47:03 PM PDT 24 26555550 ps
T643 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4147613474 Aug 18 05:46:50 PM PDT 24 Aug 18 05:46:51 PM PDT 24 180207104 ps
T644 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3074959787 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:42 PM PDT 24 33650972 ps
T645 /workspace/coverage/cover_reg_top/29.hmac_intr_test.48704124 Aug 18 05:47:03 PM PDT 24 Aug 18 05:47:04 PM PDT 24 23149102 ps
T646 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4028838966 Aug 18 05:47:04 PM PDT 24 Aug 18 05:47:05 PM PDT 24 28230235 ps
T647 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1102726586 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:39 PM PDT 24 171185616 ps
T648 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.292442980 Aug 18 05:46:41 PM PDT 24 Aug 18 05:46:42 PM PDT 24 103354958 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_intr_test.167953596 Aug 18 05:46:40 PM PDT 24 Aug 18 05:46:40 PM PDT 24 20449922 ps
T117 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1459547221 Aug 18 05:46:39 PM PDT 24 Aug 18 05:46:43 PM PDT 24 600901612 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1782561584 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:45 PM PDT 24 394527077 ps
T650 /workspace/coverage/cover_reg_top/45.hmac_intr_test.4148188919 Aug 18 05:47:05 PM PDT 24 Aug 18 05:47:06 PM PDT 24 14673334 ps
T118 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1715991036 Aug 18 05:46:48 PM PDT 24 Aug 18 05:46:50 PM PDT 24 49368457 ps
T651 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1337853905 Aug 18 05:46:43 PM PDT 24 Aug 18 05:46:45 PM PDT 24 24248920 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1330884225 Aug 18 05:46:44 PM PDT 24 Aug 18 05:46:47 PM PDT 24 107489767 ps
T653 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1083598461 Aug 18 05:46:42 PM PDT 24 Aug 18 05:46:42 PM PDT 24 16750526 ps

Test location /workspace/coverage/default/3.hmac_burst_wr.3717728033
Short name T16
Test name
Test status
Simulation time 1188965763 ps
CPU time 65.92 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 06:29:45 PM PDT 24
Peak memory 200692 kb
Host smart-38458904-cd03-4f7f-b6bf-73a7c75f47fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717728033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3717728033
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2560831298
Short name T8
Test name
Test status
Simulation time 5385936275 ps
CPU time 74.96 seconds
Started Aug 18 06:28:45 PM PDT 24
Finished Aug 18 06:30:00 PM PDT 24
Peak memory 217268 kb
Host smart-ac3be0ed-f0be-4cb6-9894-8ae45f730242
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2560831298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2560831298
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_stress_all.4202044040
Short name T33
Test name
Test status
Simulation time 140106838191 ps
CPU time 1261.85 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:49:38 PM PDT 24
Peak memory 674984 kb
Host smart-3eaae8fd-82b7-4706-b2cd-e7ec35716fd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202044040 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.4202044040
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3153809658
Short name T124
Test name
Test status
Simulation time 569987534 ps
CPU time 3.88 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200216 kb
Host smart-445d7316-08eb-4536-b77f-41c938c549e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153809658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3153809658
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.757378161
Short name T10
Test name
Test status
Simulation time 31361283964 ps
CPU time 485.53 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:37:11 PM PDT 24
Peak memory 468000 kb
Host smart-5b081aad-91e1-49f5-a251-960538060dd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757378161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.757378161
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.489077964
Short name T42
Test name
Test status
Simulation time 37364264 ps
CPU time 0.83 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:28:43 PM PDT 24
Peak memory 219040 kb
Host smart-3c25e3e7-b31a-4aad-955a-4c40272370d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489077964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.489077964
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1321302908
Short name T92
Test name
Test status
Simulation time 16439279 ps
CPU time 0.94 seconds
Started Aug 18 05:47:06 PM PDT 24
Finished Aug 18 05:47:07 PM PDT 24
Peak memory 200092 kb
Host smart-099e5797-cb16-4169-9903-4d0d3265df03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321302908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1321302908
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/default/18.hmac_stress_all.977244233
Short name T134
Test name
Test status
Simulation time 5742450160 ps
CPU time 289.7 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:33:49 PM PDT 24
Peak memory 200740 kb
Host smart-51068cac-2474-4b1c-81be-b38f2901e180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977244233 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.977244233
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2690044895
Short name T11
Test name
Test status
Simulation time 385663888 ps
CPU time 11.24 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200640 kb
Host smart-d4402394-94f5-4738-af00-c9de8e414b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690044895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2690044895
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2882538419
Short name T29
Test name
Test status
Simulation time 58571804168 ps
CPU time 1514.95 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:53:56 PM PDT 24
Peak memory 721472 kb
Host smart-046184ce-340a-4036-8b40-e557ea0810e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882538419 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2882538419
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1459547221
Short name T117
Test name
Test status
Simulation time 600901612 ps
CPU time 4.01 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200240 kb
Host smart-e56d04a9-79fc-4d2d-9bd0-b606f951c95f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459547221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1459547221
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1645352893
Short name T39
Test name
Test status
Simulation time 20106476 ps
CPU time 0.57 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:19 PM PDT 24
Peak memory 196424 kb
Host smart-9811d1fb-b2fe-484c-a75d-d280b0af00e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645352893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1645352893
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2155513107
Short name T136
Test name
Test status
Simulation time 32366794613 ps
CPU time 451.52 seconds
Started Aug 18 06:29:22 PM PDT 24
Finished Aug 18 06:36:54 PM PDT 24
Peak memory 338736 kb
Host smart-44782458-4d9d-45bc-b27b-c09904c9a017
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155513107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2155513107
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3609036708
Short name T165
Test name
Test status
Simulation time 314185431 ps
CPU time 10.31 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:29:30 PM PDT 24
Peak memory 217040 kb
Host smart-fbdc785e-801d-4f69-9d1f-99f921641f10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609036708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3609036708
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.4172453837
Short name T122
Test name
Test status
Simulation time 910012936 ps
CPU time 3.9 seconds
Started Aug 18 05:46:36 PM PDT 24
Finished Aug 18 05:46:40 PM PDT 24
Peak memory 200328 kb
Host smart-cd17661c-5cdb-4b6a-b457-f9b281cf9585
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172453837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.4172453837
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1136264176
Short name T41
Test name
Test status
Simulation time 420584415556 ps
CPU time 2844.32 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 07:16:04 PM PDT 24
Peak memory 217040 kb
Host smart-a8e8c132-5e9d-4d99-9625-0716bb3d40a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1136264176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1136264176
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2713811081
Short name T421
Test name
Test status
Simulation time 36011841465 ps
CPU time 518.89 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:37:42 PM PDT 24
Peak memory 208984 kb
Host smart-bc06f7e8-a65e-4abc-8d0a-cf51a07dff72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713811081 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2713811081
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.302109448
Short name T58
Test name
Test status
Simulation time 613145241 ps
CPU time 3.02 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200252 kb
Host smart-62b67fa8-4723-4f47-a084-ed7e67f12e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302109448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.302109448
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3712589317
Short name T94
Test name
Test status
Simulation time 306457939 ps
CPU time 3.12 seconds
Started Aug 18 05:46:33 PM PDT 24
Finished Aug 18 05:46:36 PM PDT 24
Peak memory 199196 kb
Host smart-2fb96886-e402-4417-a930-d23b37331a05
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712589317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3712589317
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1435690063
Short name T572
Test name
Test status
Simulation time 1272323181 ps
CPU time 14.32 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200272 kb
Host smart-a87c73bd-44ca-4d64-ac86-b0e6bdb4a935
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435690063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1435690063
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.19542298
Short name T617
Test name
Test status
Simulation time 117403526 ps
CPU time 0.97 seconds
Started Aug 18 05:46:31 PM PDT 24
Finished Aug 18 05:46:32 PM PDT 24
Peak memory 200048 kb
Host smart-7828f007-1241-4e94-9be7-2d2a6a9f8f57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19542298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.19542298
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4255106114
Short name T623
Test name
Test status
Simulation time 176512613056 ps
CPU time 634.62 seconds
Started Aug 18 05:46:32 PM PDT 24
Finished Aug 18 05:57:06 PM PDT 24
Peak memory 216748 kb
Host smart-74476fcd-3c6f-43db-83c9-9eae0cd2cdad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255106114 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4255106114
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3338267977
Short name T89
Test name
Test status
Simulation time 18047783 ps
CPU time 0.7 seconds
Started Aug 18 05:46:33 PM PDT 24
Finished Aug 18 05:46:34 PM PDT 24
Peak memory 198556 kb
Host smart-1f9d2105-64b8-4cf8-9fd8-2dc47c294099
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338267977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3338267977
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2621770329
Short name T546
Test name
Test status
Simulation time 16450153 ps
CPU time 0.6 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:40 PM PDT 24
Peak memory 195240 kb
Host smart-8185a43b-89b4-43de-9b95-8f46c5bd5ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621770329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2621770329
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2333322200
Short name T609
Test name
Test status
Simulation time 62951126 ps
CPU time 1.65 seconds
Started Aug 18 05:46:33 PM PDT 24
Finished Aug 18 05:46:35 PM PDT 24
Peak memory 200252 kb
Host smart-589e3459-eea7-4667-aceb-b8ee81579bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333322200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2333322200
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1742151236
Short name T63
Test name
Test status
Simulation time 42758709 ps
CPU time 1.27 seconds
Started Aug 18 05:46:31 PM PDT 24
Finished Aug 18 05:46:32 PM PDT 24
Peak memory 200272 kb
Host smart-eae5d01c-755e-4955-b281-b9c47bd751b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742151236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1742151236
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2643188256
Short name T604
Test name
Test status
Simulation time 610565235 ps
CPU time 8.02 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200160 kb
Host smart-1342e1c5-fb77-4ce2-8d58-365d507e58a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643188256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2643188256
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2332126396
Short name T99
Test name
Test status
Simulation time 5805727849 ps
CPU time 15.81 seconds
Started Aug 18 05:46:35 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 199784 kb
Host smart-5ca93ffd-18da-4c06-bb93-87e17617f1ac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332126396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2332126396
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3392593952
Short name T615
Test name
Test status
Simulation time 187643666 ps
CPU time 0.98 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:35 PM PDT 24
Peak memory 199640 kb
Host smart-98702005-f920-46e0-864b-4a514ca8b65f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392593952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3392593952
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2232641165
Short name T640
Test name
Test status
Simulation time 50771145218 ps
CPU time 465.99 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:54:20 PM PDT 24
Peak memory 216484 kb
Host smart-de6f0908-b724-4c93-82a1-199eca30ff9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232641165 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2232641165
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4029027377
Short name T620
Test name
Test status
Simulation time 15949506 ps
CPU time 0.7 seconds
Started Aug 18 05:46:33 PM PDT 24
Finished Aug 18 05:46:34 PM PDT 24
Peak memory 198396 kb
Host smart-0aeb14f6-de01-46ff-a8f6-353f4a46f13f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029027377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4029027377
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.51049441
Short name T539
Test name
Test status
Simulation time 42176104 ps
CPU time 0.57 seconds
Started Aug 18 05:46:35 PM PDT 24
Finished Aug 18 05:46:36 PM PDT 24
Peak memory 195344 kb
Host smart-f7903692-d35d-4eb5-9045-6e91ec12a257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51049441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.51049441
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.799431026
Short name T109
Test name
Test status
Simulation time 53682042 ps
CPU time 2.02 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200232 kb
Host smart-b8807b5f-8410-4d1e-b680-bdeb8b022881
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799431026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.799431026
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2163454667
Short name T628
Test name
Test status
Simulation time 53096793 ps
CPU time 2.57 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200228 kb
Host smart-8284746a-8597-49dd-88fc-bbb2f67c8c8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163454667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2163454667
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2039226444
Short name T639
Test name
Test status
Simulation time 54953734 ps
CPU time 1.7 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:36 PM PDT 24
Peak memory 200344 kb
Host smart-611d81f0-2498-47ab-828f-e4b341bbb7d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039226444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2039226444
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2509154447
Short name T568
Test name
Test status
Simulation time 412727038 ps
CPU time 1.2 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 200116 kb
Host smart-85c015c8-78ac-4b26-a931-513a347a5500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509154447 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2509154447
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2075521613
Short name T103
Test name
Test status
Simulation time 57775943 ps
CPU time 0.93 seconds
Started Aug 18 05:46:44 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200072 kb
Host smart-2db5f0b8-8311-4452-a810-1a5a25326ff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075521613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2075521613
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1083598461
Short name T653
Test name
Test status
Simulation time 16750526 ps
CPU time 0.62 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 195308 kb
Host smart-680c0d69-d0ad-41e1-a7ae-deeb1dc0b75f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083598461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1083598461
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1314835463
Short name T107
Test name
Test status
Simulation time 35036047 ps
CPU time 1.72 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200284 kb
Host smart-b1e62bb0-89de-4747-8967-e23a00a938ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314835463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1314835463
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2697919422
Short name T622
Test name
Test status
Simulation time 105557014 ps
CPU time 1.57 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:40 PM PDT 24
Peak memory 200324 kb
Host smart-1b7aa368-b41d-4a1c-9702-4b2dc8eec872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697919422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2697919422
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3869114793
Short name T619
Test name
Test status
Simulation time 259941816 ps
CPU time 1.82 seconds
Started Aug 18 05:46:45 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200276 kb
Host smart-bf715fd4-5515-4da9-813a-f219d033d174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869114793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3869114793
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1459995906
Short name T591
Test name
Test status
Simulation time 163020929 ps
CPU time 2.23 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200328 kb
Host smart-419fd3ec-d3f1-4049-ae48-c3cc26e4e25c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459995906 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1459995906
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4147613474
Short name T643
Test name
Test status
Simulation time 180207104 ps
CPU time 0.92 seconds
Started Aug 18 05:46:50 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 200068 kb
Host smart-ff6f6310-d5a8-4460-b5a2-a46fd018b79a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147613474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4147613474
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1905927440
Short name T532
Test name
Test status
Simulation time 12353511 ps
CPU time 0.58 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 195236 kb
Host smart-717ec31b-c84b-4648-88a6-80b1c1d63bd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905927440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1905927440
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2707845631
Short name T556
Test name
Test status
Simulation time 289718817 ps
CPU time 1.77 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200260 kb
Host smart-a37d433e-b3fe-436b-b153-9fd684a546cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707845631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2707845631
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.116766779
Short name T550
Test name
Test status
Simulation time 177868941 ps
CPU time 3.04 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 200272 kb
Host smart-99d83564-e1c1-42da-8ecd-71d936f075e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116766779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.116766779
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1056247398
Short name T594
Test name
Test status
Simulation time 32629415055 ps
CPU time 320.78 seconds
Started Aug 18 05:46:50 PM PDT 24
Finished Aug 18 05:52:11 PM PDT 24
Peak memory 216816 kb
Host smart-faf1719f-8de3-4fbb-8354-36be4f89b66c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056247398 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1056247398
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2443388578
Short name T541
Test name
Test status
Simulation time 47852560 ps
CPU time 0.95 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 200044 kb
Host smart-18d2fd56-b523-4655-b0c0-b87da1d66255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443388578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2443388578
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.471881745
Short name T548
Test name
Test status
Simulation time 29697661 ps
CPU time 0.66 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 195308 kb
Host smart-2f247955-a7b4-4964-b5e0-9ada742ba2ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471881745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.471881745
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2863621674
Short name T636
Test name
Test status
Simulation time 45630104 ps
CPU time 1.14 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200188 kb
Host smart-694020a4-ebbb-4020-be9d-946371ca4f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863621674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2863621674
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2468635109
Short name T562
Test name
Test status
Simulation time 291011467 ps
CPU time 1.82 seconds
Started Aug 18 05:46:52 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200252 kb
Host smart-9efae0d3-4950-406e-b135-a2a032bd4073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468635109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2468635109
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1715991036
Short name T118
Test name
Test status
Simulation time 49368457 ps
CPU time 1.7 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200268 kb
Host smart-6419a620-4d3f-4e54-9139-644b3a70cb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715991036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1715991036
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.624898702
Short name T576
Test name
Test status
Simulation time 329240448 ps
CPU time 2.23 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200516 kb
Host smart-e3b77616-4da6-45cc-902b-bbf78ab19713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624898702 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.624898702
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4069113999
Short name T596
Test name
Test status
Simulation time 62215546 ps
CPU time 0.73 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 198160 kb
Host smart-57019890-571d-4c2d-b291-18973cc5a005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069113999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4069113999
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2418548243
Short name T542
Test name
Test status
Simulation time 21573111 ps
CPU time 0.6 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 195212 kb
Host smart-088a7b23-6d48-450b-8da9-a26dfa22e312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418548243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2418548243
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1217955957
Short name T614
Test name
Test status
Simulation time 34317723 ps
CPU time 1.58 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200168 kb
Host smart-71dc4ad7-f64e-45e3-9d24-e05b59426b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217955957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1217955957
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3687903909
Short name T629
Test name
Test status
Simulation time 140530605 ps
CPU time 1.54 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200272 kb
Host smart-4395e3bd-a9f5-4871-b1e9-3c7af48b1f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687903909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3687903909
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2349882472
Short name T624
Test name
Test status
Simulation time 81025407 ps
CPU time 1.75 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:52 PM PDT 24
Peak memory 200192 kb
Host smart-5f6444c3-6084-4791-a0b8-ad3c40768c56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349882472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2349882472
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3172256561
Short name T607
Test name
Test status
Simulation time 23117609 ps
CPU time 1.44 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 200264 kb
Host smart-555b6733-f497-455c-9d25-1efda6400324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172256561 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3172256561
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.4085250188
Short name T98
Test name
Test status
Simulation time 25079689 ps
CPU time 0.78 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200084 kb
Host smart-eec0c90e-0bd8-421a-b7a1-0f653551ef86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085250188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.4085250188
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.86431308
Short name T635
Test name
Test status
Simulation time 15097801 ps
CPU time 0.58 seconds
Started Aug 18 05:46:50 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 195124 kb
Host smart-5df292c7-906a-4ef7-bff3-115231878714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86431308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.86431308
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.4233124873
Short name T618
Test name
Test status
Simulation time 264163990 ps
CPU time 1.72 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 200252 kb
Host smart-11c0737a-b532-4b4e-929e-9a728bb38b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233124873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.4233124873
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.343659182
Short name T549
Test name
Test status
Simulation time 470471835 ps
CPU time 4.22 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:55 PM PDT 24
Peak memory 200288 kb
Host smart-0bf4922b-e1dd-4399-b21f-4bf71b605143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343659182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.343659182
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2888732467
Short name T120
Test name
Test status
Simulation time 81585554 ps
CPU time 1.8 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 200172 kb
Host smart-0da94f69-ca9b-4e0b-b887-8ae97c462236
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888732467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2888732467
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.382011726
Short name T540
Test name
Test status
Simulation time 70875914 ps
CPU time 2.46 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 216708 kb
Host smart-0138b1d7-99de-42b4-b8d9-669f26dca0b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382011726 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.382011726
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1004366330
Short name T97
Test name
Test status
Simulation time 28250028 ps
CPU time 0.78 seconds
Started Aug 18 05:46:48 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 200088 kb
Host smart-84f3600b-ab15-489e-b31f-0a3897325807
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004366330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1004366330
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1026033778
Short name T574
Test name
Test status
Simulation time 17642029 ps
CPU time 0.66 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 195332 kb
Host smart-3d94fe7a-f991-4080-a99a-f216f04adf7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026033778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1026033778
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1939993982
Short name T106
Test name
Test status
Simulation time 48431032 ps
CPU time 2.19 seconds
Started Aug 18 05:46:49 PM PDT 24
Finished Aug 18 05:46:51 PM PDT 24
Peak memory 200312 kb
Host smart-8f205c6c-ac1b-4b0d-806f-5bcdaa2d1ab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939993982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1939993982
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2088776638
Short name T561
Test name
Test status
Simulation time 677407581 ps
CPU time 3.19 seconds
Started Aug 18 05:46:50 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200152 kb
Host smart-a876100e-d910-4555-9bcf-cfad339e35b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088776638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2088776638
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2430876897
Short name T553
Test name
Test status
Simulation time 96358938 ps
CPU time 1.86 seconds
Started Aug 18 05:46:51 PM PDT 24
Finished Aug 18 05:46:53 PM PDT 24
Peak memory 200216 kb
Host smart-e4f59550-f3b8-4b8d-9ecf-338a24877028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430876897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2430876897
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.604532403
Short name T613
Test name
Test status
Simulation time 88013428 ps
CPU time 2.86 seconds
Started Aug 18 05:46:57 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 200416 kb
Host smart-2fb5a617-f4c5-49be-aba7-357f8d98e4a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604532403 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.604532403
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2470413738
Short name T101
Test name
Test status
Simulation time 101997512 ps
CPU time 0.93 seconds
Started Aug 18 05:46:59 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 200096 kb
Host smart-3fe412d4-fbc8-46ea-9103-bb08a0645a35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470413738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2470413738
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1193696558
Short name T626
Test name
Test status
Simulation time 39717897 ps
CPU time 0.56 seconds
Started Aug 18 05:46:54 PM PDT 24
Finished Aug 18 05:46:54 PM PDT 24
Peak memory 195260 kb
Host smart-e7b71858-ca56-4d5f-be2e-d2ff71adb747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193696558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1193696558
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3334946607
Short name T110
Test name
Test status
Simulation time 467769040 ps
CPU time 2.02 seconds
Started Aug 18 05:47:02 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 200188 kb
Host smart-9ece5ef7-7609-4dd8-b6c4-cc4fc7bbaa3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334946607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3334946607
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1704685574
Short name T575
Test name
Test status
Simulation time 501412573 ps
CPU time 2.64 seconds
Started Aug 18 05:46:54 PM PDT 24
Finished Aug 18 05:46:57 PM PDT 24
Peak memory 200268 kb
Host smart-c75ae1b6-9f97-48c0-82ab-de0ce33e5634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704685574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1704685574
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1852843010
Short name T612
Test name
Test status
Simulation time 981938953 ps
CPU time 2.72 seconds
Started Aug 18 05:47:06 PM PDT 24
Finished Aug 18 05:47:09 PM PDT 24
Peak memory 200248 kb
Host smart-de1d5fa9-9fbf-497b-8854-c844df8769c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852843010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1852843010
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.868786139
Short name T642
Test name
Test status
Simulation time 26555550 ps
CPU time 1.67 seconds
Started Aug 18 05:47:01 PM PDT 24
Finished Aug 18 05:47:03 PM PDT 24
Peak memory 200184 kb
Host smart-c7774bc4-9ca5-4dad-b68a-8f312c01d363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868786139 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.868786139
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3119736060
Short name T111
Test name
Test status
Simulation time 25721885 ps
CPU time 0.79 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:46:57 PM PDT 24
Peak memory 199420 kb
Host smart-aba0b3dc-7a36-4f6e-b848-d394b23d62e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119736060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3119736060
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1838764572
Short name T531
Test name
Test status
Simulation time 12210153 ps
CPU time 0.57 seconds
Started Aug 18 05:46:59 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 195240 kb
Host smart-e4bbad0b-c840-4bd6-a22f-1c8f95b3c064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838764572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1838764572
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1226406138
Short name T581
Test name
Test status
Simulation time 22297875 ps
CPU time 1.05 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:46:57 PM PDT 24
Peak memory 198148 kb
Host smart-8e28aaf0-b4e6-4bd9-ba12-9e66c6e9e204
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226406138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1226406138
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1265077776
Short name T605
Test name
Test status
Simulation time 76582589 ps
CPU time 1.55 seconds
Started Aug 18 05:46:57 PM PDT 24
Finished Aug 18 05:46:58 PM PDT 24
Peak memory 200248 kb
Host smart-d2bef490-7a5f-4887-b9af-4c95bf577404
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265077776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1265077776
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4071410455
Short name T121
Test name
Test status
Simulation time 141053278 ps
CPU time 2.87 seconds
Started Aug 18 05:46:55 PM PDT 24
Finished Aug 18 05:46:58 PM PDT 24
Peak memory 200268 kb
Host smart-a5b1a988-07c0-4563-8919-637710a0712b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071410455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4071410455
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1609387202
Short name T632
Test name
Test status
Simulation time 395343366 ps
CPU time 2.18 seconds
Started Aug 18 05:46:58 PM PDT 24
Finished Aug 18 05:47:01 PM PDT 24
Peak memory 200392 kb
Host smart-9a3df1c0-ea36-499e-8dee-ac7f71a5cb49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609387202 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1609387202
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1137580498
Short name T589
Test name
Test status
Simulation time 49816021 ps
CPU time 0.55 seconds
Started Aug 18 05:46:58 PM PDT 24
Finished Aug 18 05:46:59 PM PDT 24
Peak memory 195256 kb
Host smart-a0d0ab43-b32b-41e1-a332-69c849237bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137580498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1137580498
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.90620883
Short name T104
Test name
Test status
Simulation time 23225011 ps
CPU time 1.1 seconds
Started Aug 18 05:46:59 PM PDT 24
Finished Aug 18 05:47:01 PM PDT 24
Peak memory 200056 kb
Host smart-25537e83-5f18-42b2-9ac8-78509230fd74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90620883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_
outstanding.90620883
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3364354811
Short name T564
Test name
Test status
Simulation time 129414461 ps
CPU time 2.39 seconds
Started Aug 18 05:47:06 PM PDT 24
Finished Aug 18 05:47:09 PM PDT 24
Peak memory 200240 kb
Host smart-a63d8a78-d181-46b3-b4a7-ac133c51b660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364354811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3364354811
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1410907866
Short name T126
Test name
Test status
Simulation time 239430497 ps
CPU time 3.95 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 200332 kb
Host smart-62e3df65-feed-4904-a6e1-9a69ba6ca180
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410907866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1410907866
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.107536165
Short name T587
Test name
Test status
Simulation time 38209246 ps
CPU time 1.25 seconds
Started Aug 18 05:47:01 PM PDT 24
Finished Aug 18 05:47:02 PM PDT 24
Peak memory 200024 kb
Host smart-072a52ad-3dba-4c98-9843-28df4aedf1a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107536165 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.107536165
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3579135410
Short name T611
Test name
Test status
Simulation time 64970237 ps
CPU time 0.69 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:46:57 PM PDT 24
Peak memory 197812 kb
Host smart-7dd79601-34fb-4b3d-b6fe-0473f0819317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579135410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3579135410
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1092296809
Short name T606
Test name
Test status
Simulation time 21755520 ps
CPU time 0.58 seconds
Started Aug 18 05:46:59 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 195224 kb
Host smart-00e6e067-b95c-4ff5-9b81-fa987d63414a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092296809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1092296809
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1020726135
Short name T105
Test name
Test status
Simulation time 107688248 ps
CPU time 1.81 seconds
Started Aug 18 05:47:06 PM PDT 24
Finished Aug 18 05:47:08 PM PDT 24
Peak memory 199972 kb
Host smart-95d5241c-1ab4-4dc4-8572-3dd7ae867cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020726135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1020726135
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1719108286
Short name T603
Test name
Test status
Simulation time 260444617 ps
CPU time 3.72 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 200168 kb
Host smart-4d64a07b-d103-4fd7-aea0-37c909c15dde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719108286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1719108286
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3416773002
Short name T57
Test name
Test status
Simulation time 326464256 ps
CPU time 2.8 seconds
Started Aug 18 05:46:56 PM PDT 24
Finished Aug 18 05:46:59 PM PDT 24
Peak memory 200328 kb
Host smart-928a1c80-3878-438c-9660-af9b9716162b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416773002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3416773002
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3548572672
Short name T95
Test name
Test status
Simulation time 1996689581 ps
CPU time 8.52 seconds
Started Aug 18 05:46:35 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200232 kb
Host smart-43e039fd-4cc8-44ca-bd13-0772d5d3e008
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548572672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3548572672
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.386407646
Short name T100
Test name
Test status
Simulation time 1641936980 ps
CPU time 16.79 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:47:00 PM PDT 24
Peak memory 200248 kb
Host smart-6d78d818-3831-4f44-9ed5-c8b7e4699f13
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386407646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.386407646
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.702794838
Short name T93
Test name
Test status
Simulation time 20674079 ps
CPU time 0.76 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 198320 kb
Host smart-70fbb486-6888-4e67-912c-7e3fffdb1734
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702794838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.702794838
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2566405185
Short name T62
Test name
Test status
Simulation time 97262634 ps
CPU time 2.28 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:37 PM PDT 24
Peak memory 200308 kb
Host smart-7225509d-e209-44fc-bfab-c71a91886baa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566405185 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2566405185
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1163310528
Short name T588
Test name
Test status
Simulation time 22361625 ps
CPU time 0.82 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 199948 kb
Host smart-5aa4a41b-6c7e-4fe5-9bec-ead7c79cfbb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163310528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1163310528
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1746608400
Short name T558
Test name
Test status
Simulation time 16215694 ps
CPU time 0.6 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 195364 kb
Host smart-937b426f-9d71-4ef1-8d96-2dc233b24472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746608400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1746608400
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1302032492
Short name T559
Test name
Test status
Simulation time 57736650 ps
CPU time 1.15 seconds
Started Aug 18 05:46:32 PM PDT 24
Finished Aug 18 05:46:33 PM PDT 24
Peak memory 198884 kb
Host smart-bcc8fd16-277a-4dfc-95f6-c21de564529d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302032492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1302032492
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3830643184
Short name T625
Test name
Test status
Simulation time 810676851 ps
CPU time 3.72 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200268 kb
Host smart-4b4ff852-8994-4058-b18d-462501b8363d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830643184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3830643184
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.2140674498
Short name T56
Test name
Test status
Simulation time 220218363 ps
CPU time 4.14 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:39 PM PDT 24
Peak memory 200348 kb
Host smart-409f2e06-c282-4a0c-a844-0496760aefda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140674498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.2140674498
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2269311529
Short name T554
Test name
Test status
Simulation time 28281967 ps
CPU time 0.6 seconds
Started Aug 18 05:47:06 PM PDT 24
Finished Aug 18 05:47:07 PM PDT 24
Peak memory 195000 kb
Host smart-ff25e990-980a-4ea7-a786-4ebda5fc7945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269311529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2269311529
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.4216875193
Short name T578
Test name
Test status
Simulation time 18986957 ps
CPU time 0.61 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195348 kb
Host smart-a2bf6e81-6d0f-4a80-ae1c-091dea0d06de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216875193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.4216875193
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1001281659
Short name T585
Test name
Test status
Simulation time 14736032 ps
CPU time 0.6 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195280 kb
Host smart-00e98518-54a0-4ff0-94ac-fbfeb7ffe64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001281659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1001281659
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2112471773
Short name T630
Test name
Test status
Simulation time 11517093 ps
CPU time 0.57 seconds
Started Aug 18 05:47:07 PM PDT 24
Finished Aug 18 05:47:08 PM PDT 24
Peak memory 195308 kb
Host smart-efbfa74d-9829-4685-86ee-0fae44fd6522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112471773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2112471773
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2639634434
Short name T569
Test name
Test status
Simulation time 137473228 ps
CPU time 0.6 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195360 kb
Host smart-194bfae6-5a8f-46cf-bf3c-01723519f5f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639634434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2639634434
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3003360007
Short name T536
Test name
Test status
Simulation time 13835355 ps
CPU time 0.66 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195364 kb
Host smart-671e39a9-95ce-457f-adde-8bd44f406017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003360007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3003360007
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.610804364
Short name T573
Test name
Test status
Simulation time 25812665 ps
CPU time 0.63 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195272 kb
Host smart-fe2ecf10-4159-4e59-b26a-7c52c909dca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610804364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.610804364
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.689441534
Short name T592
Test name
Test status
Simulation time 16116396 ps
CPU time 0.6 seconds
Started Aug 18 05:47:07 PM PDT 24
Finished Aug 18 05:47:08 PM PDT 24
Peak memory 195252 kb
Host smart-aa668b72-35a7-4744-8468-814b3e8f58ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689441534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.689441534
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1918108043
Short name T627
Test name
Test status
Simulation time 30262296 ps
CPU time 0.58 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195208 kb
Host smart-59933503-53d3-43f5-a938-560ceef5ab65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918108043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1918108043
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.48704124
Short name T645
Test name
Test status
Simulation time 23149102 ps
CPU time 0.6 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195296 kb
Host smart-859f2a35-24b0-457e-a351-b84765508dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48704124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.48704124
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2827626678
Short name T590
Test name
Test status
Simulation time 152465251 ps
CPU time 7.87 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 200108 kb
Host smart-268e7129-71a6-4382-8fb1-1b50fdc6daf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827626678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2827626678
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2854607839
Short name T566
Test name
Test status
Simulation time 718704016 ps
CPU time 5.64 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 200268 kb
Host smart-45702d0e-b9e2-44e5-b1a1-22aab357df6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854607839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2854607839
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.988383804
Short name T595
Test name
Test status
Simulation time 97897595 ps
CPU time 0.83 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 199816 kb
Host smart-888cb546-e79c-426a-8038-c7300a1da113
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988383804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.988383804
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3680119250
Short name T84
Test name
Test status
Simulation time 126250907 ps
CPU time 1.2 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:41 PM PDT 24
Peak memory 200172 kb
Host smart-4f4252ce-2e32-4cb6-a76a-83e3ec0d55af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680119250 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3680119250
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.292442980
Short name T648
Test name
Test status
Simulation time 103354958 ps
CPU time 0.8 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 199680 kb
Host smart-08a8a84f-c4a3-4e47-b9c4-7fd0c34989cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292442980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.292442980
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2839705435
Short name T537
Test name
Test status
Simulation time 31910854 ps
CPU time 0.57 seconds
Started Aug 18 05:46:38 PM PDT 24
Finished Aug 18 05:46:38 PM PDT 24
Peak memory 195380 kb
Host smart-840e8054-45bc-4a43-816b-2fddf2037221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839705435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2839705435
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2309301660
Short name T597
Test name
Test status
Simulation time 526761984 ps
CPU time 1.64 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200248 kb
Host smart-f00bb2c9-29c7-466b-bd22-487b7879f3fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309301660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2309301660
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.486071290
Short name T557
Test name
Test status
Simulation time 321864374 ps
CPU time 1.96 seconds
Started Aug 18 05:46:34 PM PDT 24
Finished Aug 18 05:46:37 PM PDT 24
Peak memory 200324 kb
Host smart-17cb1d88-b306-451d-bfe4-9c624252809b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486071290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.486071290
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2643261237
Short name T125
Test name
Test status
Simulation time 244406159 ps
CPU time 3.91 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200308 kb
Host smart-25d585ab-eb56-420d-a44d-895f3bad49db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643261237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2643261237
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.203437457
Short name T530
Test name
Test status
Simulation time 21152550 ps
CPU time 0.55 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195164 kb
Host smart-cc0fbe2e-fc03-4e2b-be69-03b1072ccd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203437457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.203437457
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.228879070
Short name T552
Test name
Test status
Simulation time 16150310 ps
CPU time 0.62 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195336 kb
Host smart-a8cfda07-088e-4f52-8e3e-b69f2e408c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228879070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.228879070
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.4000469275
Short name T583
Test name
Test status
Simulation time 20690864 ps
CPU time 0.6 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195220 kb
Host smart-a8bba930-9f0e-4b8e-aa1e-20b95fa2749a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000469275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.4000469275
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1772151955
Short name T544
Test name
Test status
Simulation time 30710916 ps
CPU time 0.58 seconds
Started Aug 18 05:47:03 PM PDT 24
Finished Aug 18 05:47:04 PM PDT 24
Peak memory 195172 kb
Host smart-cdaa10f5-0ca1-401f-b018-0c6037307f7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772151955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1772151955
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.808410486
Short name T571
Test name
Test status
Simulation time 41424348 ps
CPU time 0.59 seconds
Started Aug 18 05:47:02 PM PDT 24
Finished Aug 18 05:47:03 PM PDT 24
Peak memory 195280 kb
Host smart-db544c3d-be4e-4f71-8d43-a94fd3d2fed8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808410486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.808410486
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.4141772725
Short name T580
Test name
Test status
Simulation time 38577730 ps
CPU time 0.59 seconds
Started Aug 18 05:47:04 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195272 kb
Host smart-e031aa4e-8341-4abc-8640-0f74b57bb6be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141772725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4141772725
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1174139327
Short name T555
Test name
Test status
Simulation time 17726170 ps
CPU time 0.64 seconds
Started Aug 18 05:47:08 PM PDT 24
Finished Aug 18 05:47:08 PM PDT 24
Peak memory 195336 kb
Host smart-f8f997fe-541d-4b0c-a2b1-aee32814c3de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174139327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1174139327
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1886489224
Short name T533
Test name
Test status
Simulation time 39362664 ps
CPU time 0.64 seconds
Started Aug 18 05:47:04 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195324 kb
Host smart-49e08e76-a53f-4970-8d6d-26be8b7b8279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886489224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1886489224
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.4059475926
Short name T593
Test name
Test status
Simulation time 58509569 ps
CPU time 0.57 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195344 kb
Host smart-11fc5ef4-2a8b-49d2-91cb-aa9a76c85178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059475926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.4059475926
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.339453707
Short name T577
Test name
Test status
Simulation time 18261436 ps
CPU time 0.65 seconds
Started Aug 18 05:47:04 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195428 kb
Host smart-2567a8b6-1be5-4850-b7db-71e671bac58f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339453707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.339453707
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.4057622194
Short name T90
Test name
Test status
Simulation time 742876593 ps
CPU time 5.66 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200196 kb
Host smart-a36dcebb-6b1a-48e8-bf85-7bb0d9508b79
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057622194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4057622194
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2106841277
Short name T638
Test name
Test status
Simulation time 2107176916 ps
CPU time 15.74 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:55 PM PDT 24
Peak memory 200164 kb
Host smart-474bb31b-db20-48e0-8515-3ba4d48cc1c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106841277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2106841277
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1102726586
Short name T647
Test name
Test status
Simulation time 171185616 ps
CPU time 0.7 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:39 PM PDT 24
Peak memory 198372 kb
Host smart-8654a821-3d3d-4e40-809a-fe66fcbca5e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102726586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1102726586
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2388062658
Short name T565
Test name
Test status
Simulation time 735839957 ps
CPU time 2.34 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200352 kb
Host smart-2bec54d7-0e1a-4b32-908d-82a0a3eaacfb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388062658 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2388062658
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3900244540
Short name T91
Test name
Test status
Simulation time 27731611 ps
CPU time 0.82 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200012 kb
Host smart-db2fdd44-35aa-493a-a675-d3b7619d327f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900244540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3900244540
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2676669766
Short name T584
Test name
Test status
Simulation time 27784961 ps
CPU time 0.58 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 195160 kb
Host smart-c1bbad75-065c-4e06-8ed8-5ba510b27b45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676669766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2676669766
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2780205721
Short name T634
Test name
Test status
Simulation time 847752162 ps
CPU time 1.16 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:40 PM PDT 24
Peak memory 200240 kb
Host smart-38533633-415a-4fe6-9673-448bbad64698
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780205721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2780205721
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3961323864
Short name T560
Test name
Test status
Simulation time 108821679 ps
CPU time 2.65 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 200184 kb
Host smart-85be0f92-8f90-4520-9c69-97352bc919d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961323864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3961323864
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1782561584
Short name T123
Test name
Test status
Simulation time 394527077 ps
CPU time 2.85 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200240 kb
Host smart-71adb921-cf86-4716-bf2f-2f415f3279b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782561584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1782561584
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4028838966
Short name T646
Test name
Test status
Simulation time 28230235 ps
CPU time 0.6 seconds
Started Aug 18 05:47:04 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195216 kb
Host smart-20e2237e-93cf-4adb-a08e-c2115815d3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028838966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4028838966
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1243403269
Short name T602
Test name
Test status
Simulation time 26379262 ps
CPU time 0.6 seconds
Started Aug 18 05:47:07 PM PDT 24
Finished Aug 18 05:47:07 PM PDT 24
Peak memory 195240 kb
Host smart-783dc17e-4c41-4bc7-a658-91c93bbb2c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243403269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1243403269
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1497832937
Short name T598
Test name
Test status
Simulation time 49594120 ps
CPU time 0.63 seconds
Started Aug 18 05:47:07 PM PDT 24
Finished Aug 18 05:47:08 PM PDT 24
Peak memory 195256 kb
Host smart-b45dcd96-13f1-4f60-a1c6-2e561fcb2817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497832937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1497832937
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2294014152
Short name T545
Test name
Test status
Simulation time 16919604 ps
CPU time 0.6 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195336 kb
Host smart-a3f40a20-f043-4192-b64c-a596eb2de1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294014152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2294014152
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3638325825
Short name T608
Test name
Test status
Simulation time 20154993 ps
CPU time 0.62 seconds
Started Aug 18 05:47:02 PM PDT 24
Finished Aug 18 05:47:02 PM PDT 24
Peak memory 195280 kb
Host smart-a9f80e91-6c24-4797-a508-cd042fea5ce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638325825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3638325825
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.4148188919
Short name T650
Test name
Test status
Simulation time 14673334 ps
CPU time 0.56 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195216 kb
Host smart-a297345f-ac9d-46be-a85c-5c455a098311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148188919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.4148188919
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.346368006
Short name T534
Test name
Test status
Simulation time 14730522 ps
CPU time 0.58 seconds
Started Aug 18 05:47:09 PM PDT 24
Finished Aug 18 05:47:09 PM PDT 24
Peak memory 195244 kb
Host smart-672f2932-8336-4d31-9fb4-035c5e05fb0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346368006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.346368006
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.628110208
Short name T599
Test name
Test status
Simulation time 14731053 ps
CPU time 0.61 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195244 kb
Host smart-860e960c-d4cb-4ab1-be1c-708f91021916
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628110208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.628110208
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.394142645
Short name T570
Test name
Test status
Simulation time 19360493 ps
CPU time 0.64 seconds
Started Aug 18 05:47:05 PM PDT 24
Finished Aug 18 05:47:06 PM PDT 24
Peak memory 195304 kb
Host smart-f3cdea07-127e-4415-bf23-9e2ae6b18f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394142645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.394142645
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2727287474
Short name T586
Test name
Test status
Simulation time 118777418 ps
CPU time 0.61 seconds
Started Aug 18 05:47:04 PM PDT 24
Finished Aug 18 05:47:05 PM PDT 24
Peak memory 195364 kb
Host smart-96f8ba3d-f12f-4152-858d-26e32656251d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727287474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2727287474
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.90930068
Short name T563
Test name
Test status
Simulation time 32679419 ps
CPU time 1.14 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:41 PM PDT 24
Peak memory 200048 kb
Host smart-07d8a474-f392-4575-8a9d-d36870e94177
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90930068 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.90930068
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1812722216
Short name T600
Test name
Test status
Simulation time 61397711 ps
CPU time 0.7 seconds
Started Aug 18 05:46:45 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 198836 kb
Host smart-a01fed9b-f37c-44fa-bf97-18f017934fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812722216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1812722216
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2180160765
Short name T601
Test name
Test status
Simulation time 23803065 ps
CPU time 0.59 seconds
Started Aug 18 05:46:46 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 195300 kb
Host smart-5051946b-84b9-4073-a1bd-8a1c86125216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180160765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2180160765
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3374716620
Short name T551
Test name
Test status
Simulation time 111223354 ps
CPU time 2.27 seconds
Started Aug 18 05:46:46 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 200248 kb
Host smart-cb87058c-3537-46a5-9cbb-eda15371ce5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374716620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3374716620
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1330884225
Short name T652
Test name
Test status
Simulation time 107489767 ps
CPU time 2.75 seconds
Started Aug 18 05:46:44 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200272 kb
Host smart-e32c96cc-9a68-4688-b8bf-c2c4994e26c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330884225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1330884225
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3669814944
Short name T641
Test name
Test status
Simulation time 54321859 ps
CPU time 2.69 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:50 PM PDT 24
Peak memory 208532 kb
Host smart-c22b9917-e797-4cdc-a72e-5d0d94e977f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669814944 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3669814944
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2601304973
Short name T631
Test name
Test status
Simulation time 100003467 ps
CPU time 0.7 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 198620 kb
Host smart-f4631076-d8c3-4200-a4f2-cd2d8568481d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601304973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2601304973
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3074959787
Short name T644
Test name
Test status
Simulation time 33650972 ps
CPU time 0.56 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 195172 kb
Host smart-69b909f3-4ae9-4ce3-aa3f-82a5ac238653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074959787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3074959787
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1264435075
Short name T582
Test name
Test status
Simulation time 1585128206 ps
CPU time 1.9 seconds
Started Aug 18 05:46:47 PM PDT 24
Finished Aug 18 05:46:49 PM PDT 24
Peak memory 200252 kb
Host smart-1cabc6f7-7313-4dc4-8660-74c0af0e1d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264435075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1264435075
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.347991128
Short name T547
Test name
Test status
Simulation time 405852526 ps
CPU time 1.78 seconds
Started Aug 18 05:46:46 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200208 kb
Host smart-11e334ad-f1e3-4371-9f10-c232985cf52b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347991128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.347991128
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.539609839
Short name T119
Test name
Test status
Simulation time 222367720 ps
CPU time 4.43 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200276 kb
Host smart-55c1e677-8a55-4b86-b043-2b3031ca5102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539609839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.539609839
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3511024723
Short name T637
Test name
Test status
Simulation time 277894959 ps
CPU time 3.15 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:44 PM PDT 24
Peak memory 200464 kb
Host smart-9eb6b4b3-9dcb-469e-8afe-2823c8b338a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511024723 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3511024723
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3285963417
Short name T96
Test name
Test status
Simulation time 294775954 ps
CPU time 0.77 seconds
Started Aug 18 05:46:45 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 199344 kb
Host smart-498d85a4-e720-46cb-a070-b39d1a87137d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285963417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3285963417
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2343178372
Short name T535
Test name
Test status
Simulation time 26216150 ps
CPU time 0.58 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 195124 kb
Host smart-8710cbdd-2e64-4b47-b98d-8ae0b916a694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343178372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2343178372
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1792639562
Short name T108
Test name
Test status
Simulation time 35994553 ps
CPU time 1.55 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:41 PM PDT 24
Peak memory 200272 kb
Host smart-162ef87f-2462-4c5e-80e0-e74e210422ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792639562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1792639562
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3712918904
Short name T621
Test name
Test status
Simulation time 29856390 ps
CPU time 1.58 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200240 kb
Host smart-5e368f62-cb27-4dee-86e7-c5074d5262f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712918904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3712918904
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1453621206
Short name T116
Test name
Test status
Simulation time 624616266 ps
CPU time 1.93 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200212 kb
Host smart-21e6fc81-9520-4721-b188-665c7017a40e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453621206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1453621206
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.389756884
Short name T61
Test name
Test status
Simulation time 453995818 ps
CPU time 2.44 seconds
Started Aug 18 05:46:39 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 208544 kb
Host smart-a53fde23-ddda-4e59-beef-11c89be92b12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389756884 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.389756884
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2251968596
Short name T102
Test name
Test status
Simulation time 21528455 ps
CPU time 0.68 seconds
Started Aug 18 05:46:37 PM PDT 24
Finished Aug 18 05:46:38 PM PDT 24
Peak memory 198152 kb
Host smart-d225616b-21da-442d-867d-2e4d99d5fe71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251968596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2251968596
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3351008939
Short name T538
Test name
Test status
Simulation time 38884195 ps
CPU time 0.58 seconds
Started Aug 18 05:46:41 PM PDT 24
Finished Aug 18 05:46:42 PM PDT 24
Peak memory 195268 kb
Host smart-25a21b69-8d57-4cc7-953a-95e02b9e82f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351008939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3351008939
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1503577680
Short name T616
Test name
Test status
Simulation time 73845157 ps
CPU time 1.07 seconds
Started Aug 18 05:46:42 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 200164 kb
Host smart-7b43825b-4e8f-48a8-b806-6d06bfe3a5d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503577680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1503577680
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1733716923
Short name T567
Test name
Test status
Simulation time 206264555 ps
CPU time 3.6 seconds
Started Aug 18 05:46:44 PM PDT 24
Finished Aug 18 05:46:48 PM PDT 24
Peak memory 200268 kb
Host smart-d5c9b272-8bfe-444c-a477-210ff6b78786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733716923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1733716923
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.598453293
Short name T579
Test name
Test status
Simulation time 132560471 ps
CPU time 1.88 seconds
Started Aug 18 05:46:44 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 200328 kb
Host smart-2121cb0f-2645-43c6-b57c-623e96e0c088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598453293 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.598453293
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.47231284
Short name T610
Test name
Test status
Simulation time 24051655 ps
CPU time 0.8 seconds
Started Aug 18 05:46:45 PM PDT 24
Finished Aug 18 05:46:46 PM PDT 24
Peak memory 200092 kb
Host smart-1088fe2a-91bf-41b6-ab5b-4250d045531e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47231284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.47231284
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.167953596
Short name T649
Test name
Test status
Simulation time 20449922 ps
CPU time 0.6 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:40 PM PDT 24
Peak memory 195252 kb
Host smart-96221b36-e069-47a0-9a5d-03dc5b386d28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167953596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.167953596
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1337853905
Short name T651
Test name
Test status
Simulation time 24248920 ps
CPU time 1.08 seconds
Started Aug 18 05:46:43 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 198952 kb
Host smart-acee15ff-942c-4c65-be06-67cb0c595fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337853905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1337853905
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2843186287
Short name T543
Test name
Test status
Simulation time 295402382 ps
CPU time 1.83 seconds
Started Aug 18 05:46:45 PM PDT 24
Finished Aug 18 05:46:47 PM PDT 24
Peak memory 200268 kb
Host smart-9a04fe74-7cca-450d-ac13-cfaa1f7803d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843186287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2843186287
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1864510191
Short name T633
Test name
Test status
Simulation time 1111726935 ps
CPU time 3.94 seconds
Started Aug 18 05:46:40 PM PDT 24
Finished Aug 18 05:46:45 PM PDT 24
Peak memory 200276 kb
Host smart-4b8b7603-0287-4c7e-b338-92f36ea0f2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864510191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1864510191
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4143956757
Short name T443
Test name
Test status
Simulation time 93090260 ps
CPU time 0.59 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:28:38 PM PDT 24
Peak memory 196700 kb
Host smart-a04e435a-cd6f-4bc0-af46-9c5084812d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143956757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4143956757
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2697520025
Short name T339
Test name
Test status
Simulation time 2784401533 ps
CPU time 78.91 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:29:59 PM PDT 24
Peak memory 200732 kb
Host smart-760658ad-de87-4f17-848d-9072799b8dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2697520025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2697520025
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1595318581
Short name T162
Test name
Test status
Simulation time 159180559 ps
CPU time 8.9 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:29:17 PM PDT 24
Peak memory 200712 kb
Host smart-2fe662db-11c8-446a-a201-a8f7ac91c9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595318581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1595318581
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.153616888
Short name T435
Test name
Test status
Simulation time 1406072451 ps
CPU time 218.96 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:32:45 PM PDT 24
Peak memory 599460 kb
Host smart-6753ce0d-4a81-4b34-bb48-a42e4e5b0475
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153616888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.153616888
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2761630605
Short name T185
Test name
Test status
Simulation time 2118599420 ps
CPU time 110.83 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:30:27 PM PDT 24
Peak memory 200640 kb
Host smart-f5878cd5-d483-48a6-b62e-3dd547e6ca79
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761630605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2761630605
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3681076855
Short name T357
Test name
Test status
Simulation time 24159274802 ps
CPU time 198.62 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 06:32:06 PM PDT 24
Peak memory 200764 kb
Host smart-2cd5897c-38ff-47c6-bf35-675fc5b34acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681076855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3681076855
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3984872522
Short name T43
Test name
Test status
Simulation time 203347018 ps
CPU time 0.78 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:28:36 PM PDT 24
Peak memory 219004 kb
Host smart-731491f8-611f-4da8-9add-9d9c65c206bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984872522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3984872522
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3731274963
Short name T380
Test name
Test status
Simulation time 243218207 ps
CPU time 3.22 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:29:06 PM PDT 24
Peak memory 200672 kb
Host smart-3567e763-8a93-42dc-8e4f-e1458d36133a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731274963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3731274963
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2677170470
Short name T308
Test name
Test status
Simulation time 19184067785 ps
CPU time 61.89 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:30:04 PM PDT 24
Peak memory 200596 kb
Host smart-1bd75dc7-75b4-4d0f-acc4-1ceca1b0ba34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2677170470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2677170470
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.4166294328
Short name T282
Test name
Test status
Simulation time 8633497663 ps
CPU time 103.25 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:30:25 PM PDT 24
Peak memory 200680 kb
Host smart-462abbc0-3106-47e4-8a73-4d15286b478e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4166294328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.4166294328
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1405446785
Short name T318
Test name
Test status
Simulation time 2964644489 ps
CPU time 106.03 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:30:28 PM PDT 24
Peak memory 200824 kb
Host smart-65cb6ce9-8f4f-4fd4-bdfc-b494c421c75e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1405446785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1405446785
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.839246763
Short name T189
Test name
Test status
Simulation time 10654512580 ps
CPU time 599.11 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:38:40 PM PDT 24
Peak memory 200700 kb
Host smart-6f723c98-44d0-4add-b79c-587bf35c65ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=839246763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.839246763
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2883964573
Short name T130
Test name
Test status
Simulation time 557539673180 ps
CPU time 2434.09 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 07:09:42 PM PDT 24
Peak memory 216916 kb
Host smart-e5ddbced-bd1a-442c-9b04-50df1e22f4d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2883964573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2883964573
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1930399835
Short name T206
Test name
Test status
Simulation time 4263917973 ps
CPU time 47.47 seconds
Started Aug 18 06:28:54 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200760 kb
Host smart-ffc3c1d8-b019-419f-aa1b-067656b42fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930399835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1930399835
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3290909061
Short name T214
Test name
Test status
Simulation time 12504017 ps
CPU time 0.6 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:28:43 PM PDT 24
Peak memory 195740 kb
Host smart-17f609ad-7190-4439-96fc-dad809f90211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290909061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3290909061
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.846753979
Short name T298
Test name
Test status
Simulation time 983830903 ps
CPU time 61.14 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 06:29:49 PM PDT 24
Peak memory 200692 kb
Host smart-57d41d73-f311-49b7-8b8c-b6b03923c36b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846753979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.846753979
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3575767971
Short name T148
Test name
Test status
Simulation time 4407035970 ps
CPU time 20.08 seconds
Started Aug 18 06:28:34 PM PDT 24
Finished Aug 18 06:28:55 PM PDT 24
Peak memory 200824 kb
Host smart-ff7396a6-a510-4432-b27b-53a2fd0f6c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575767971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3575767971
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3711092484
Short name T363
Test name
Test status
Simulation time 1146838877 ps
CPU time 52.3 seconds
Started Aug 18 06:28:32 PM PDT 24
Finished Aug 18 06:29:24 PM PDT 24
Peak memory 331332 kb
Host smart-d18e1014-9983-4453-af8e-064f515a79c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3711092484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3711092484
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3648758324
Short name T322
Test name
Test status
Simulation time 32658630022 ps
CPU time 208.42 seconds
Started Aug 18 06:29:04 PM PDT 24
Finished Aug 18 06:32:32 PM PDT 24
Peak memory 200720 kb
Host smart-917686be-4e8f-4334-825f-d5aef0e810e5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648758324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3648758324
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1788992689
Short name T294
Test name
Test status
Simulation time 14467648367 ps
CPU time 48.12 seconds
Started Aug 18 06:28:46 PM PDT 24
Finished Aug 18 06:29:34 PM PDT 24
Peak memory 208880 kb
Host smart-47d738ff-eaf2-4f8b-9c86-0e25cb097eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788992689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1788992689
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.4259547923
Short name T361
Test name
Test status
Simulation time 3141502634 ps
CPU time 10.57 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:28:49 PM PDT 24
Peak memory 200796 kb
Host smart-aa4039ad-1c66-47d1-91a6-c1d100d59c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259547923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.4259547923
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3433402348
Short name T184
Test name
Test status
Simulation time 31609329590 ps
CPU time 1140 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 06:47:39 PM PDT 24
Peak memory 670604 kb
Host smart-c127bee0-2e76-46a5-ab1a-5239ba759106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433402348 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3433402348
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3238908862
Short name T271
Test name
Test status
Simulation time 21530546311 ps
CPU time 50.05 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 200800 kb
Host smart-7e3b1660-89cc-4fec-ac97-dbd23d1931d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3238908862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3238908862
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.2960996457
Short name T176
Test name
Test status
Simulation time 26162964351 ps
CPU time 100.21 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:30:20 PM PDT 24
Peak memory 200776 kb
Host smart-865b0dae-0e3e-406b-b3b6-e1bcab9f23bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2960996457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.2960996457
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1437725795
Short name T52
Test name
Test status
Simulation time 10804951979 ps
CPU time 140.28 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:31:00 PM PDT 24
Peak memory 200760 kb
Host smart-aa422b04-a0e6-4fca-b05c-71a3f866e159
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1437725795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1437725795
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2158126899
Short name T287
Test name
Test status
Simulation time 47638045579 ps
CPU time 652.18 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:39:33 PM PDT 24
Peak memory 200688 kb
Host smart-fd3bf579-03be-4d36-a420-e2512e59b7e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2158126899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2158126899
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.272268078
Short name T65
Test name
Test status
Simulation time 39645688931 ps
CPU time 2228.56 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 07:05:57 PM PDT 24
Peak memory 216212 kb
Host smart-3956edf6-01d8-4dd2-9700-4a41ffa7cffd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=272268078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.272268078
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2154242530
Short name T307
Test name
Test status
Simulation time 45086001933 ps
CPU time 2715.51 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 07:13:57 PM PDT 24
Peak memory 217012 kb
Host smart-0c5f022f-ca53-4dad-a8c8-029b6b92e1c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2154242530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2154242530
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.151527189
Short name T86
Test name
Test status
Simulation time 31966327163 ps
CPU time 84.77 seconds
Started Aug 18 06:28:57 PM PDT 24
Finished Aug 18 06:30:22 PM PDT 24
Peak memory 200736 kb
Host smart-214c49d0-e03b-4f18-8854-5517387235e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151527189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.151527189
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1317784954
Short name T38
Test name
Test status
Simulation time 34920935 ps
CPU time 0.55 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:28:38 PM PDT 24
Peak memory 195576 kb
Host smart-f2da6b63-26e8-436b-b75d-beb2c6f7614f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317784954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1317784954
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.725746903
Short name T156
Test name
Test status
Simulation time 247924785 ps
CPU time 7.02 seconds
Started Aug 18 06:28:44 PM PDT 24
Finished Aug 18 06:28:51 PM PDT 24
Peak memory 200680 kb
Host smart-80542da2-9561-4e90-857d-afc52a615d22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725746903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.725746903
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2615103614
Short name T497
Test name
Test status
Simulation time 1116025602 ps
CPU time 58.88 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 200644 kb
Host smart-7282bb7c-125d-44bc-8a1f-9765eb867d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615103614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2615103614
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.531812239
Short name T521
Test name
Test status
Simulation time 18404049777 ps
CPU time 883.22 seconds
Started Aug 18 06:28:50 PM PDT 24
Finished Aug 18 06:43:34 PM PDT 24
Peak memory 720084 kb
Host smart-a63e40f3-02e6-411a-ba25-f5da73540116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531812239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.531812239
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2498909683
Short name T303
Test name
Test status
Simulation time 38748230581 ps
CPU time 126.91 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:30:48 PM PDT 24
Peak memory 200764 kb
Host smart-8317d848-a04b-469f-8376-2bf1beaf8104
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498909683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2498909683
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3531421781
Short name T396
Test name
Test status
Simulation time 2491917564 ps
CPU time 147.25 seconds
Started Aug 18 06:29:01 PM PDT 24
Finished Aug 18 06:31:29 PM PDT 24
Peak memory 200676 kb
Host smart-3609f5c0-27d7-4709-98f9-0d00e3686b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531421781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3531421781
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3383000914
Short name T14
Test name
Test status
Simulation time 1468333927 ps
CPU time 12.01 seconds
Started Aug 18 06:29:01 PM PDT 24
Finished Aug 18 06:29:18 PM PDT 24
Peak memory 200680 kb
Host smart-e96111ec-6e7b-48d4-942e-d103c33c665d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383000914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3383000914
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.885252591
Short name T512
Test name
Test status
Simulation time 17717188749 ps
CPU time 533.03 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:37:56 PM PDT 24
Peak memory 651840 kb
Host smart-705fa5e5-6284-44e8-b213-f048756ba285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885252591 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.885252591
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2767452486
Short name T113
Test name
Test status
Simulation time 14254166 ps
CPU time 0.67 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:28:41 PM PDT 24
Peak memory 197080 kb
Host smart-956e635c-5258-41eb-aef9-34ad9962d2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767452486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2767452486
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4045387781
Short name T186
Test name
Test status
Simulation time 44855603 ps
CPU time 0.58 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:28:37 PM PDT 24
Peak memory 194952 kb
Host smart-c72e9d36-c16d-43b3-8ffb-7af4743a3ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045387781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4045387781
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3489992338
Short name T352
Test name
Test status
Simulation time 3947676924 ps
CPU time 62.51 seconds
Started Aug 18 06:28:49 PM PDT 24
Finished Aug 18 06:29:52 PM PDT 24
Peak memory 200788 kb
Host smart-4e0bcc34-9a12-4527-ab0d-4758c920d0c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3489992338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3489992338
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2290823059
Short name T133
Test name
Test status
Simulation time 3527945481 ps
CPU time 25.37 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:29:08 PM PDT 24
Peak memory 200720 kb
Host smart-ce18243d-c735-4307-9452-4075f176145f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290823059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2290823059
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1841170360
Short name T158
Test name
Test status
Simulation time 16214579934 ps
CPU time 953.99 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:44:30 PM PDT 24
Peak memory 748708 kb
Host smart-e705c2ab-12e7-408e-b31d-2cef69cb1070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1841170360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1841170360
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3372871620
Short name T172
Test name
Test status
Simulation time 933639928 ps
CPU time 12.61 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:28:56 PM PDT 24
Peak memory 200584 kb
Host smart-f8f76f84-0fa3-46c9-8424-011ef21c510f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372871620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3372871620
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2329744219
Short name T388
Test name
Test status
Simulation time 16741549638 ps
CPU time 170.45 seconds
Started Aug 18 06:28:50 PM PDT 24
Finished Aug 18 06:31:41 PM PDT 24
Peak memory 201168 kb
Host smart-f8d765c0-df6a-484a-9603-ccc5c6845380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329744219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2329744219
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1089608214
Short name T463
Test name
Test status
Simulation time 865274865 ps
CPU time 13.36 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:28:51 PM PDT 24
Peak memory 200696 kb
Host smart-fc1d6220-8668-4fa6-aedc-6cc637dacaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089608214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1089608214
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3055108649
Short name T141
Test name
Test status
Simulation time 11014097832 ps
CPU time 733.42 seconds
Started Aug 18 06:28:55 PM PDT 24
Finished Aug 18 06:41:09 PM PDT 24
Peak memory 457016 kb
Host smart-6cef78a6-4bd4-4f90-8bcb-a556a2281dad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055108649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3055108649
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1348117033
Short name T67
Test name
Test status
Simulation time 40775305046 ps
CPU time 121.61 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:30:43 PM PDT 24
Peak memory 199264 kb
Host smart-cf283ab5-dd62-46d2-9c09-1e3c63524812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348117033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1348117033
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4036144949
Short name T422
Test name
Test status
Simulation time 26076760 ps
CPU time 0.56 seconds
Started Aug 18 06:29:04 PM PDT 24
Finished Aug 18 06:29:05 PM PDT 24
Peak memory 195588 kb
Host smart-a3813f0f-ab14-4533-a8bc-b3a4226739fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036144949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4036144949
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1535679575
Short name T21
Test name
Test status
Simulation time 3859348867 ps
CPU time 38.48 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:29:19 PM PDT 24
Peak memory 200860 kb
Host smart-3b1b7cd0-8a19-407a-b85d-fb6dfcc9d1b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535679575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1535679575
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2353534762
Short name T220
Test name
Test status
Simulation time 3039716190 ps
CPU time 43.35 seconds
Started Aug 18 06:28:56 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 200716 kb
Host smart-0ddc7176-8e1f-490e-a0bc-5274b1cc5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353534762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2353534762
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3048060375
Short name T7
Test name
Test status
Simulation time 3249937529 ps
CPU time 618.29 seconds
Started Aug 18 06:28:57 PM PDT 24
Finished Aug 18 06:39:16 PM PDT 24
Peak memory 686632 kb
Host smart-d45cc4bf-4011-4078-a1ab-344f7096f043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048060375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3048060375
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3489060261
Short name T428
Test name
Test status
Simulation time 39761970684 ps
CPU time 275.17 seconds
Started Aug 18 06:28:53 PM PDT 24
Finished Aug 18 06:33:29 PM PDT 24
Peak memory 200708 kb
Host smart-e000c395-2598-45f6-9cb4-b349556f155c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489060261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3489060261
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.290161305
Short name T232
Test name
Test status
Simulation time 733775426 ps
CPU time 43.83 seconds
Started Aug 18 06:28:56 PM PDT 24
Finished Aug 18 06:29:40 PM PDT 24
Peak memory 200700 kb
Host smart-a6c2b658-5fc2-4c2f-8dce-2947d53eddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290161305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.290161305
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.745551536
Short name T147
Test name
Test status
Simulation time 658949026 ps
CPU time 9.02 seconds
Started Aug 18 06:28:48 PM PDT 24
Finished Aug 18 06:28:57 PM PDT 24
Peak memory 200632 kb
Host smart-14d1fbfd-851a-4482-9bfe-394f80eac926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745551536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.745551536
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.724532015
Short name T336
Test name
Test status
Simulation time 39273640160 ps
CPU time 579.27 seconds
Started Aug 18 06:28:59 PM PDT 24
Finished Aug 18 06:38:39 PM PDT 24
Peak memory 358668 kb
Host smart-ccfcaa09-84f1-4099-9b01-f849c358fb0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724532015 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.724532015
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.402201582
Short name T85
Test name
Test status
Simulation time 44002019191 ps
CPU time 144.15 seconds
Started Aug 18 06:28:59 PM PDT 24
Finished Aug 18 06:31:23 PM PDT 24
Peak memory 200712 kb
Host smart-3f3bca59-a756-4fbd-8c5f-9797fcaca4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402201582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.402201582
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4120071202
Short name T524
Test name
Test status
Simulation time 28477834 ps
CPU time 0.59 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:29:03 PM PDT 24
Peak memory 195704 kb
Host smart-70b78b02-4c34-4c9f-b100-d1380038e672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120071202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4120071202
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3072702446
Short name T513
Test name
Test status
Simulation time 749160979 ps
CPU time 19.2 seconds
Started Aug 18 06:28:57 PM PDT 24
Finished Aug 18 06:29:16 PM PDT 24
Peak memory 200688 kb
Host smart-1545f096-bb70-467e-8376-1ab131747b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072702446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3072702446
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2648975663
Short name T194
Test name
Test status
Simulation time 1995003632 ps
CPU time 35.47 seconds
Started Aug 18 06:28:52 PM PDT 24
Finished Aug 18 06:29:28 PM PDT 24
Peak memory 200732 kb
Host smart-a6090c11-3ae0-479a-a9d0-757f3bc9c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648975663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2648975663
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1413378766
Short name T419
Test name
Test status
Simulation time 8480951036 ps
CPU time 361.15 seconds
Started Aug 18 06:28:57 PM PDT 24
Finished Aug 18 06:34:59 PM PDT 24
Peak memory 476596 kb
Host smart-ed2abedb-8523-4998-97d3-0c20c6ce384c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1413378766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1413378766
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3937423564
Short name T69
Test name
Test status
Simulation time 8418546301 ps
CPU time 107.54 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:30:49 PM PDT 24
Peak memory 200660 kb
Host smart-28ba9bc9-1eb2-41de-9aa1-e34af21a55d6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937423564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3937423564
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.280735485
Short name T477
Test name
Test status
Simulation time 33460735609 ps
CPU time 147.76 seconds
Started Aug 18 06:28:56 PM PDT 24
Finished Aug 18 06:31:24 PM PDT 24
Peak memory 200752 kb
Host smart-810ad093-f00b-4103-b5fe-f9b3b0221f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280735485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.280735485
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2355893661
Short name T442
Test name
Test status
Simulation time 636766778 ps
CPU time 9.92 seconds
Started Aug 18 06:28:54 PM PDT 24
Finished Aug 18 06:29:04 PM PDT 24
Peak memory 200556 kb
Host smart-f6b2d77d-4ca6-4178-844c-bb0e9889a0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355893661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2355893661
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.4046156197
Short name T59
Test name
Test status
Simulation time 36982713388 ps
CPU time 1580.56 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:55:30 PM PDT 24
Peak memory 718212 kb
Host smart-e436f24e-28b0-4696-ba08-aefd84e3b6ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046156197 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.4046156197
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1213355344
Short name T529
Test name
Test status
Simulation time 13926359500 ps
CPU time 120.53 seconds
Started Aug 18 06:29:04 PM PDT 24
Finished Aug 18 06:31:05 PM PDT 24
Peak memory 200776 kb
Host smart-a04e44f2-7cbd-4925-abff-c63e54e92951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213355344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1213355344
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.487501000
Short name T258
Test name
Test status
Simulation time 18932167 ps
CPU time 0.57 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:06 PM PDT 24
Peak memory 195736 kb
Host smart-d8992e88-26b9-45c0-aa6f-74f5be231012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487501000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.487501000
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.589497752
Short name T12
Test name
Test status
Simulation time 7449364733 ps
CPU time 82.38 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:30:26 PM PDT 24
Peak memory 208968 kb
Host smart-2f860465-b1c5-4616-8bf9-57e7654d2959
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=589497752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.589497752
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2539283775
Short name T225
Test name
Test status
Simulation time 939613326 ps
CPU time 3.34 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:28:46 PM PDT 24
Peak memory 200624 kb
Host smart-8a5c1968-d0dd-450b-9210-3979a08b3ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539283775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2539283775
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2313222618
Short name T239
Test name
Test status
Simulation time 1498291743 ps
CPU time 259.04 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:33:01 PM PDT 24
Peak memory 492024 kb
Host smart-02200b67-a313-4631-b4bf-48ad23509d1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2313222618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2313222618
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1154441337
Short name T350
Test name
Test status
Simulation time 49619380755 ps
CPU time 206.73 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:32:35 PM PDT 24
Peak memory 200820 kb
Host smart-7e5139f1-00dd-4bf1-8cfa-f6252f119b3e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154441337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1154441337
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1839188318
Short name T83
Test name
Test status
Simulation time 31437076693 ps
CPU time 149.91 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:31:40 PM PDT 24
Peak memory 200752 kb
Host smart-41f16b3c-83c0-4a51-9554-8097156e19a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839188318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1839188318
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.30253237
Short name T406
Test name
Test status
Simulation time 3651564617 ps
CPU time 12.91 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:29:21 PM PDT 24
Peak memory 200832 kb
Host smart-249c34c2-29b0-4e85-9efc-3b120b03ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30253237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.30253237
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3015547881
Short name T333
Test name
Test status
Simulation time 151115741889 ps
CPU time 840.04 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:43:10 PM PDT 24
Peak memory 641596 kb
Host smart-679e3d71-dec3-4f5e-8044-2a996fc8083c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015547881 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3015547881
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2686370246
Short name T456
Test name
Test status
Simulation time 86395358321 ps
CPU time 129.79 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:31:15 PM PDT 24
Peak memory 200708 kb
Host smart-f4cb5049-b55a-4d4e-830b-04f8037724e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686370246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2686370246
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.818004219
Short name T401
Test name
Test status
Simulation time 12715748 ps
CPU time 0.58 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:07 PM PDT 24
Peak memory 196496 kb
Host smart-82f9233a-e4ae-40f4-b2e1-e9a9575c8523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818004219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.818004219
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2444938077
Short name T17
Test name
Test status
Simulation time 4809937361 ps
CPU time 36.89 seconds
Started Aug 18 06:28:51 PM PDT 24
Finished Aug 18 06:29:28 PM PDT 24
Peak memory 200756 kb
Host smart-f9105006-ec35-4fa6-acfe-1c751d4f841b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444938077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2444938077
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2725255030
Short name T291
Test name
Test status
Simulation time 3525949377 ps
CPU time 64.22 seconds
Started Aug 18 06:28:59 PM PDT 24
Finished Aug 18 06:30:03 PM PDT 24
Peak memory 200720 kb
Host smart-07afe0e9-dace-4181-9c88-c2d5731a424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725255030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2725255030
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3300510801
Short name T295
Test name
Test status
Simulation time 3875867767 ps
CPU time 294.52 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:33:55 PM PDT 24
Peak memory 646316 kb
Host smart-37a6e8fa-96d2-43a0-b962-123d37b7df05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300510801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3300510801
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3841299741
Short name T79
Test name
Test status
Simulation time 2995318391 ps
CPU time 37.99 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:44 PM PDT 24
Peak memory 200696 kb
Host smart-c6217c4c-ca66-431c-969a-0697584d597d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841299741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3841299741
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1092346048
Short name T393
Test name
Test status
Simulation time 1435344628 ps
CPU time 79.92 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:30:01 PM PDT 24
Peak memory 200668 kb
Host smart-2d1d1870-b7e0-4425-ac1c-87b729f82376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092346048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1092346048
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2935060981
Short name T304
Test name
Test status
Simulation time 4382646267 ps
CPU time 7.4 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:29:18 PM PDT 24
Peak memory 200816 kb
Host smart-f5b52547-4946-4970-82cc-de96fba4b18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935060981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2935060981
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3956524267
Short name T40
Test name
Test status
Simulation time 170934738886 ps
CPU time 135.65 seconds
Started Aug 18 06:29:07 PM PDT 24
Finished Aug 18 06:31:28 PM PDT 24
Peak memory 201144 kb
Host smart-3ac4ac5b-6673-432a-a209-b62e127187f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956524267 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3956524267
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.397080464
Short name T493
Test name
Test status
Simulation time 8312322553 ps
CPU time 35.24 seconds
Started Aug 18 06:28:54 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 200720 kb
Host smart-ddd1bc8d-5b28-45b9-8541-cb9e84e0382f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397080464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.397080464
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2054346762
Short name T403
Test name
Test status
Simulation time 25687074 ps
CPU time 0.61 seconds
Started Aug 18 06:28:59 PM PDT 24
Finished Aug 18 06:29:00 PM PDT 24
Peak memory 197428 kb
Host smart-4636dd86-a7ff-4195-9b81-51e3c972441a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054346762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2054346762
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.550148653
Short name T22
Test name
Test status
Simulation time 1364896130 ps
CPU time 92.85 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:30:38 PM PDT 24
Peak memory 200700 kb
Host smart-67d09ca3-d476-4ade-aab5-3e128f4306be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=550148653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.550148653
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2529869092
Short name T312
Test name
Test status
Simulation time 1222911254 ps
CPU time 32.54 seconds
Started Aug 18 06:28:51 PM PDT 24
Finished Aug 18 06:29:24 PM PDT 24
Peak memory 200724 kb
Host smart-72885128-cf61-4968-b060-32dc6070c5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529869092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2529869092
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2974282208
Short name T251
Test name
Test status
Simulation time 1062449789 ps
CPU time 207.76 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:32:34 PM PDT 24
Peak memory 633228 kb
Host smart-f0ce6545-55ec-4781-a4bf-25b4028d43e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974282208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2974282208
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.518623865
Short name T190
Test name
Test status
Simulation time 7700154792 ps
CPU time 105.38 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:30:51 PM PDT 24
Peak memory 200692 kb
Host smart-66ca6e40-12c9-4c8a-bbcf-2bfdf08b1024
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518623865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.518623865
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1797977817
Short name T238
Test name
Test status
Simulation time 38951777932 ps
CPU time 114.27 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:31:05 PM PDT 24
Peak memory 200828 kb
Host smart-abb8e1a7-858c-4400-813d-e95e33f877b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797977817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1797977817
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.41974633
Short name T453
Test name
Test status
Simulation time 1187307215 ps
CPU time 15.23 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:21 PM PDT 24
Peak memory 200704 kb
Host smart-b6ae70b5-58e8-4c9f-8219-837ac53791b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41974633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.41974633
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1648113249
Short name T503
Test name
Test status
Simulation time 17012226038 ps
CPU time 239.29 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:33:02 PM PDT 24
Peak memory 200740 kb
Host smart-989b8211-90cb-48a5-93bc-9bad82fb4517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648113249 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1648113249
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2924080491
Short name T432
Test name
Test status
Simulation time 25794033952 ps
CPU time 76.37 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:30:25 PM PDT 24
Peak memory 200952 kb
Host smart-18522f7b-e537-4bd2-95fe-958c3e1f3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924080491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2924080491
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1001449114
Short name T347
Test name
Test status
Simulation time 60351240 ps
CPU time 0.67 seconds
Started Aug 18 06:29:07 PM PDT 24
Finished Aug 18 06:29:07 PM PDT 24
Peak memory 196760 kb
Host smart-0d3927e1-b1ee-46bc-b1a1-68c54bccb993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001449114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1001449114
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.923546848
Short name T264
Test name
Test status
Simulation time 2111262781 ps
CPU time 64.58 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:30:13 PM PDT 24
Peak memory 200700 kb
Host smart-44fe0169-031f-464d-93cb-614b7f7f0940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=923546848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.923546848
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.964286181
Short name T28
Test name
Test status
Simulation time 3443345668 ps
CPU time 45.9 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:29:51 PM PDT 24
Peak memory 200744 kb
Host smart-2d3dcd15-a65d-43f7-92c4-92428ab6e1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964286181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.964286181
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1844775527
Short name T416
Test name
Test status
Simulation time 2805332457 ps
CPU time 111.05 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:30:58 PM PDT 24
Peak memory 568496 kb
Host smart-44bda076-be70-4234-8b58-c7bd14a6f8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844775527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1844775527
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.2729100080
Short name T201
Test name
Test status
Simulation time 8568793176 ps
CPU time 115.12 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:30:57 PM PDT 24
Peak memory 200800 kb
Host smart-bfe34814-f3d6-42e0-adc3-5ee8468e506c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729100080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2729100080
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.350292984
Short name T509
Test name
Test status
Simulation time 1033517662 ps
CPU time 56.71 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:29:57 PM PDT 24
Peak memory 200716 kb
Host smart-4d702521-2458-4760-9fe3-8302d8b35ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350292984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.350292984
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.771074167
Short name T467
Test name
Test status
Simulation time 4313118963 ps
CPU time 17.18 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:29:17 PM PDT 24
Peak memory 200768 kb
Host smart-1c5fc89d-c9c6-4b2a-8961-4f76dc93acea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771074167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.771074167
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.929818397
Short name T76
Test name
Test status
Simulation time 158805511617 ps
CPU time 1079.95 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:47:10 PM PDT 24
Peak memory 200736 kb
Host smart-e22e6725-7d94-475f-8e78-4386fb52e569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929818397 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.929818397
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.4111319132
Short name T260
Test name
Test status
Simulation time 7265126904 ps
CPU time 117.86 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 200748 kb
Host smart-f353a6f8-6605-4161-bc0f-de1befcf72b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111319132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.4111319132
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3323692066
Short name T470
Test name
Test status
Simulation time 15360390 ps
CPU time 0.56 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:29:10 PM PDT 24
Peak memory 196744 kb
Host smart-6cd00a14-7f3e-49d5-a1b1-80820d9c428b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323692066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3323692066
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2777037300
Short name T266
Test name
Test status
Simulation time 3189564606 ps
CPU time 85.81 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:30:30 PM PDT 24
Peak memory 200808 kb
Host smart-e4f29e9b-80c2-4cb8-a057-fbd3073ed0f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2777037300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2777037300
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.608540734
Short name T382
Test name
Test status
Simulation time 21379001372 ps
CPU time 62.7 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:30:09 PM PDT 24
Peak memory 217004 kb
Host smart-50ada21e-79b5-49d0-944d-7f102745e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608540734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.608540734
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.249064843
Short name T349
Test name
Test status
Simulation time 1110128702 ps
CPU time 305.12 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:34:09 PM PDT 24
Peak memory 671464 kb
Host smart-a33c24e8-dae8-4b4c-b445-30d55731917a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=249064843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.249064843
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.386587130
Short name T387
Test name
Test status
Simulation time 58381937055 ps
CPU time 178.47 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:32:05 PM PDT 24
Peak memory 200736 kb
Host smart-ef1549b6-1fcf-4784-9fc2-e9cbeafd9341
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386587130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.386587130
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.860661890
Short name T215
Test name
Test status
Simulation time 15775290903 ps
CPU time 107.86 seconds
Started Aug 18 06:29:07 PM PDT 24
Finished Aug 18 06:30:55 PM PDT 24
Peak memory 200764 kb
Host smart-b70ff995-86d7-43d6-8355-6058d32d7ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860661890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.860661890
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1188653740
Short name T504
Test name
Test status
Simulation time 855307869 ps
CPU time 13.31 seconds
Started Aug 18 06:29:16 PM PDT 24
Finished Aug 18 06:29:30 PM PDT 24
Peak memory 200696 kb
Host smart-e9b1fdc5-e5e1-40e8-b327-28325cd93092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188653740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1188653740
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3064164058
Short name T269
Test name
Test status
Simulation time 1233382126 ps
CPU time 6.04 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:29:15 PM PDT 24
Peak memory 200580 kb
Host smart-aac50be2-cc7b-49ba-9e3e-309b08e760fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064164058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3064164058
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1062222600
Short name T216
Test name
Test status
Simulation time 41114587 ps
CPU time 0.58 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:21 PM PDT 24
Peak memory 197448 kb
Host smart-dbeab051-e1e7-4d5f-a56e-eafad1645310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062222600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1062222600
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2327194166
Short name T429
Test name
Test status
Simulation time 848606722 ps
CPU time 52.58 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:30:04 PM PDT 24
Peak memory 200588 kb
Host smart-35b44e2b-70ac-495a-b6d0-240df67e1c11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327194166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2327194166
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1731405055
Short name T179
Test name
Test status
Simulation time 756482771 ps
CPU time 19.92 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:26 PM PDT 24
Peak memory 200692 kb
Host smart-8f65db4b-d0bb-4100-b3b0-85748dd7310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731405055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1731405055
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1163049966
Short name T270
Test name
Test status
Simulation time 6345500634 ps
CPU time 450.75 seconds
Started Aug 18 06:29:14 PM PDT 24
Finished Aug 18 06:36:45 PM PDT 24
Peak memory 658564 kb
Host smart-7aa1a70d-3fa7-4793-9616-8b0758b3f605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1163049966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1163049966
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2959735839
Short name T55
Test name
Test status
Simulation time 1059356153 ps
CPU time 14.83 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:29:24 PM PDT 24
Peak memory 200736 kb
Host smart-2137b4fa-e646-4faf-8dfe-d49241c1dea6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959735839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2959735839
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4271523801
Short name T368
Test name
Test status
Simulation time 3500333843 ps
CPU time 153.05 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:31:46 PM PDT 24
Peak memory 200772 kb
Host smart-b2cfdb98-7946-49aa-819d-b1082e834bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271523801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4271523801
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.250399588
Short name T459
Test name
Test status
Simulation time 666189720 ps
CPU time 8.27 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:29:31 PM PDT 24
Peak memory 200544 kb
Host smart-7d17db01-982e-44b7-a1c7-732c41f14da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250399588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.250399588
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2751464306
Short name T81
Test name
Test status
Simulation time 2635950203 ps
CPU time 18.88 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 200720 kb
Host smart-20403e4f-849c-41b7-9c19-62356f622713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751464306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2751464306
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3844494010
Short name T499
Test name
Test status
Simulation time 16831111 ps
CPU time 0.6 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:29:01 PM PDT 24
Peak memory 196776 kb
Host smart-fdf03567-e849-47fd-8a33-d527bfc6364f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844494010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3844494010
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2609688863
Short name T310
Test name
Test status
Simulation time 2481292485 ps
CPU time 11.11 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:28:47 PM PDT 24
Peak memory 200712 kb
Host smart-7fa907a2-46b1-45cc-8712-83c90d71f85d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609688863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2609688863
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.412176243
Short name T281
Test name
Test status
Simulation time 9222991874 ps
CPU time 40.16 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:29:20 PM PDT 24
Peak memory 200748 kb
Host smart-7a5fd745-c966-4d11-a735-81e27d9c8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412176243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.412176243
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.500408073
Short name T414
Test name
Test status
Simulation time 6048918801 ps
CPU time 494.67 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 06:36:54 PM PDT 24
Peak memory 612000 kb
Host smart-6aeff5eb-a495-41e0-8719-712daebd12e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=500408073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.500408073
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1676825075
Short name T472
Test name
Test status
Simulation time 2426186874 ps
CPU time 33.04 seconds
Started Aug 18 06:28:39 PM PDT 24
Finished Aug 18 06:29:12 PM PDT 24
Peak memory 200568 kb
Host smart-8e00a3e3-620c-482d-aa15-6a236fc46b83
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676825075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1676825075
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1213156731
Short name T517
Test name
Test status
Simulation time 51685065458 ps
CPU time 169.55 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:31:26 PM PDT 24
Peak memory 208936 kb
Host smart-bffc4269-8f99-4136-856d-c2ff62b1891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213156731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1213156731
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3340037685
Short name T46
Test name
Test status
Simulation time 36619768 ps
CPU time 0.83 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:29:08 PM PDT 24
Peak memory 218964 kb
Host smart-de46aab1-982a-45b9-b9f6-678e6e234dff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340037685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3340037685
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3590545481
Short name T114
Test name
Test status
Simulation time 1321960532 ps
CPU time 14.51 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:28:55 PM PDT 24
Peak memory 200708 kb
Host smart-c83ef471-1e33-4d2d-9527-9bcf862096d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590545481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3590545481
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1549023793
Short name T329
Test name
Test status
Simulation time 67525908893 ps
CPU time 1623.72 seconds
Started Aug 18 06:28:34 PM PDT 24
Finished Aug 18 06:55:39 PM PDT 24
Peak memory 658408 kb
Host smart-9a0310fd-a543-4a0b-b4e1-c826389105e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549023793 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1549023793
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2732576101
Short name T495
Test name
Test status
Simulation time 25351165283 ps
CPU time 67.92 seconds
Started Aug 18 06:28:54 PM PDT 24
Finished Aug 18 06:30:02 PM PDT 24
Peak memory 200748 kb
Host smart-993301fa-c8be-414b-9eef-233a338bef25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2732576101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2732576101
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.815607560
Short name T525
Test name
Test status
Simulation time 67638234298 ps
CPU time 109.17 seconds
Started Aug 18 06:28:59 PM PDT 24
Finished Aug 18 06:30:49 PM PDT 24
Peak memory 200724 kb
Host smart-519f3a06-b686-4f4e-aa43-19df9a1a207a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=815607560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.815607560
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1952174399
Short name T31
Test name
Test status
Simulation time 2964848990 ps
CPU time 111.43 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:30:27 PM PDT 24
Peak memory 200800 kb
Host smart-63b94aa5-5d36-4dd4-b490-34dcb0270cbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1952174399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1952174399
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1684834565
Short name T263
Test name
Test status
Simulation time 46790288680 ps
CPU time 597.4 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:38:33 PM PDT 24
Peak memory 200644 kb
Host smart-45143ff8-ea6a-44a6-8085-449050202d19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1684834565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1684834565
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1717951255
Short name T441
Test name
Test status
Simulation time 177449285870 ps
CPU time 2413.01 seconds
Started Aug 18 06:28:52 PM PDT 24
Finished Aug 18 07:09:07 PM PDT 24
Peak memory 216144 kb
Host smart-c738bffc-0ea2-4ad3-a9a8-8e07bbadda4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1717951255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1717951255
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.2250204162
Short name T410
Test name
Test status
Simulation time 657971866102 ps
CPU time 2467.56 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 07:09:51 PM PDT 24
Peak memory 216968 kb
Host smart-2941a6df-0a92-44c0-baa4-1022e6844abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2250204162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.2250204162
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3634050693
Short name T492
Test name
Test status
Simulation time 29949489261 ps
CPU time 113 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:30:32 PM PDT 24
Peak memory 200776 kb
Host smart-dfdee4c5-5136-494e-a252-aba3cb7ba4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634050693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3634050693
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3299788320
Short name T375
Test name
Test status
Simulation time 11267874 ps
CPU time 0.57 seconds
Started Aug 18 06:29:16 PM PDT 24
Finished Aug 18 06:29:16 PM PDT 24
Peak memory 196412 kb
Host smart-f11faad4-152b-4498-ad7a-b0121aa697f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299788320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3299788320
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.697176299
Short name T219
Test name
Test status
Simulation time 235255348 ps
CPU time 7.19 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:29:10 PM PDT 24
Peak memory 200624 kb
Host smart-a01d6cd6-e995-4431-8c0e-8d6e4a5e8c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697176299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.697176299
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.19372761
Short name T390
Test name
Test status
Simulation time 2235453325 ps
CPU time 30.42 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 200744 kb
Host smart-5351b1f0-cafa-486a-a893-1fcff4ce883f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19372761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.19372761
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.588573654
Short name T280
Test name
Test status
Simulation time 2367254441 ps
CPU time 313.28 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:34:24 PM PDT 24
Peak memory 445856 kb
Host smart-58a77c0c-17ae-4e09-9f49-4087c3cfa603
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=588573654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.588573654
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.768830311
Short name T448
Test name
Test status
Simulation time 2228631405 ps
CPU time 125.99 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:31:15 PM PDT 24
Peak memory 200804 kb
Host smart-909f254b-7c1d-4ac8-9982-093cfd9667f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768830311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.768830311
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3584641665
Short name T299
Test name
Test status
Simulation time 7025902087 ps
CPU time 115.44 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 200788 kb
Host smart-fa358460-2358-4780-8c5e-fb76141e32c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584641665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3584641665
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.269870894
Short name T34
Test name
Test status
Simulation time 1855113806 ps
CPU time 7.77 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:29:10 PM PDT 24
Peak memory 200700 kb
Host smart-2bb19c27-4159-465d-994c-aa3bb6f86f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269870894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.269870894
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3174602697
Short name T325
Test name
Test status
Simulation time 49949438883 ps
CPU time 44.16 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:29:55 PM PDT 24
Peak memory 200672 kb
Host smart-d472ab56-c9a2-413f-bd8c-2cba321658ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174602697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3174602697
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2444668564
Short name T267
Test name
Test status
Simulation time 17376296 ps
CPU time 0.57 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:29:13 PM PDT 24
Peak memory 196776 kb
Host smart-c3c0391d-3b78-49cb-899d-76e501d96616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444668564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2444668564
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.4221317193
Short name T464
Test name
Test status
Simulation time 6370212993 ps
CPU time 91.52 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:30:44 PM PDT 24
Peak memory 200732 kb
Host smart-46476093-bbac-4110-a6e0-ef4b6861034a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221317193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.4221317193
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3650029983
Short name T519
Test name
Test status
Simulation time 1096306318 ps
CPU time 20.68 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 200604 kb
Host smart-dd82167f-5f3e-4476-ba8d-007a3432eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650029983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3650029983
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1732459897
Short name T218
Test name
Test status
Simulation time 2107040634 ps
CPU time 321.55 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:34:35 PM PDT 24
Peak memory 462644 kb
Host smart-c3850cab-3a5a-4fc5-b49a-918d71275f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732459897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1732459897
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1812705330
Short name T384
Test name
Test status
Simulation time 43910624635 ps
CPU time 158.56 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:31:59 PM PDT 24
Peak memory 200724 kb
Host smart-58a10a3d-0339-43d6-98f2-350791432928
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812705330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1812705330
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.777208678
Short name T170
Test name
Test status
Simulation time 3144441940 ps
CPU time 12.56 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:26 PM PDT 24
Peak memory 200728 kb
Host smart-9f84d314-1c4f-4127-bbce-666c84ffe1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777208678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.777208678
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.318384555
Short name T482
Test name
Test status
Simulation time 281755455 ps
CPU time 12.96 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:29:23 PM PDT 24
Peak memory 200660 kb
Host smart-3e887b0a-44d6-49e1-b373-42a4a3c51c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318384555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.318384555
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2639114621
Short name T510
Test name
Test status
Simulation time 689719417911 ps
CPU time 3556.08 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 07:28:41 PM PDT 24
Peak memory 791464 kb
Host smart-f88f7a22-46c1-4b39-b87f-1deed95742f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639114621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2639114621
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3409009919
Short name T205
Test name
Test status
Simulation time 1875307178 ps
CPU time 98.86 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:30:59 PM PDT 24
Peak memory 200752 kb
Host smart-b776535d-3110-4ad9-b5f8-295f5e075441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409009919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3409009919
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.730658126
Short name T174
Test name
Test status
Simulation time 12768635 ps
CPU time 0.58 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:22 PM PDT 24
Peak memory 196412 kb
Host smart-0d5a8da3-6fe5-4b45-b8af-70202a9d6fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730658126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.730658126
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2487765427
Short name T317
Test name
Test status
Simulation time 1394470696 ps
CPU time 42.67 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:30:07 PM PDT 24
Peak memory 200708 kb
Host smart-81c17ee2-8288-4eb0-b446-eb3bc2538c8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487765427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2487765427
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1403844651
Short name T132
Test name
Test status
Simulation time 1850285020 ps
CPU time 50.97 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 06:30:09 PM PDT 24
Peak memory 200692 kb
Host smart-a725d98d-2401-46ed-872a-140531040bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403844651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1403844651
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3815281703
Short name T332
Test name
Test status
Simulation time 30077955238 ps
CPU time 1482.44 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:54:02 PM PDT 24
Peak memory 737056 kb
Host smart-4980492c-3c78-4c37-abee-9b2ed5092f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3815281703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3815281703
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.939890191
Short name T461
Test name
Test status
Simulation time 8327389392 ps
CPU time 74.5 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:34 PM PDT 24
Peak memory 200744 kb
Host smart-5574f6ee-4267-4cbc-b53a-bdab76c05fb7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939890191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.939890191
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4176489936
Short name T498
Test name
Test status
Simulation time 42168767107 ps
CPU time 156.25 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:32:02 PM PDT 24
Peak memory 200772 kb
Host smart-6ab51f9b-3547-4bde-9a0a-a3fd82e0d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176489936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4176489936
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3126521643
Short name T227
Test name
Test status
Simulation time 667930161 ps
CPU time 3.1 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:29:14 PM PDT 24
Peak memory 200640 kb
Host smart-f8990fe4-4dd4-4761-a799-15241e1f80b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126521643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3126521643
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2612538554
Short name T77
Test name
Test status
Simulation time 298912235573 ps
CPU time 762.54 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:41:51 PM PDT 24
Peak memory 200748 kb
Host smart-52f188dc-1ee2-40f8-95a5-fa669fc369cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612538554 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2612538554
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3118512831
Short name T209
Test name
Test status
Simulation time 1106946064 ps
CPU time 24.81 seconds
Started Aug 18 06:29:10 PM PDT 24
Finished Aug 18 06:29:34 PM PDT 24
Peak memory 200684 kb
Host smart-97d42a0e-9853-4ff0-8746-a354b44232d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118512831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3118512831
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.196152075
Short name T208
Test name
Test status
Simulation time 6074189749 ps
CPU time 87.43 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:46 PM PDT 24
Peak memory 200688 kb
Host smart-2da691d0-0ff2-41ac-940e-7382c082998d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=196152075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.196152075
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2100513356
Short name T250
Test name
Test status
Simulation time 4478308702 ps
CPU time 64.71 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:30:16 PM PDT 24
Peak memory 208948 kb
Host smart-d228bbc3-ec68-477d-838a-8cdb40df2ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100513356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2100513356
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.2405575655
Short name T202
Test name
Test status
Simulation time 12740765572 ps
CPU time 636.29 seconds
Started Aug 18 06:29:07 PM PDT 24
Finished Aug 18 06:39:43 PM PDT 24
Peak memory 714064 kb
Host smart-3e939909-a323-42ca-9339-26b4f542136b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405575655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2405575655
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1304362804
Short name T528
Test name
Test status
Simulation time 7244062526 ps
CPU time 81.72 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:30:47 PM PDT 24
Peak memory 200808 kb
Host smart-d7f3c612-ad1f-4708-ad87-b9abb1a1a036
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304362804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1304362804
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2316568297
Short name T3
Test name
Test status
Simulation time 1786264254 ps
CPU time 25.16 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 06:29:43 PM PDT 24
Peak memory 200764 kb
Host smart-f1f39fea-acf4-4d4f-8ce0-f60c522b8699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316568297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2316568297
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2669379550
Short name T502
Test name
Test status
Simulation time 187282898 ps
CPU time 8.01 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:33 PM PDT 24
Peak memory 200688 kb
Host smart-7410bb82-a5db-49b0-b41e-acb6281b1c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669379550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2669379550
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1753634718
Short name T452
Test name
Test status
Simulation time 46232811791 ps
CPU time 2049.28 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 07:03:29 PM PDT 24
Peak memory 800100 kb
Host smart-01ca39aa-2a5e-4bef-8528-ea97aeab10d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753634718 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1753634718
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1734526795
Short name T30
Test name
Test status
Simulation time 8870515042 ps
CPU time 98.87 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:30:42 PM PDT 24
Peak memory 200736 kb
Host smart-7c6321e9-adc2-4adb-8eec-3361b35a7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734526795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1734526795
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3449894515
Short name T326
Test name
Test status
Simulation time 11677380 ps
CPU time 0.57 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:14 PM PDT 24
Peak memory 195732 kb
Host smart-5b058143-a393-4ead-901c-5a2147ee895a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449894515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3449894515
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.4215527636
Short name T254
Test name
Test status
Simulation time 4265778587 ps
CPU time 14.39 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:29:26 PM PDT 24
Peak memory 200732 kb
Host smart-5e118fd9-5ee8-49f9-ab7c-9e8155335add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4215527636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.4215527636
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3882875048
Short name T188
Test name
Test status
Simulation time 8996531108 ps
CPU time 28.22 seconds
Started Aug 18 06:29:14 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 208944 kb
Host smart-10a34eff-11b0-4330-bfd3-9723909a622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882875048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3882875048
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4224395888
Short name T80
Test name
Test status
Simulation time 1527016710 ps
CPU time 279.49 seconds
Started Aug 18 06:29:14 PM PDT 24
Finished Aug 18 06:33:54 PM PDT 24
Peak memory 640484 kb
Host smart-2687c019-f0b9-43ab-a283-6735d789121d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4224395888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4224395888
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.391674044
Short name T425
Test name
Test status
Simulation time 1250068231 ps
CPU time 31.1 seconds
Started Aug 18 06:29:05 PM PDT 24
Finished Aug 18 06:29:37 PM PDT 24
Peak memory 200672 kb
Host smart-05022e06-244a-4eba-8ab5-fa67e4d2dd95
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391674044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.391674044
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.3019927136
Short name T54
Test name
Test status
Simulation time 161339593491 ps
CPU time 114.13 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:31:07 PM PDT 24
Peak memory 200860 kb
Host smart-57d8f712-0285-4132-aacc-4626109e8a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019927136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3019927136
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2453299710
Short name T196
Test name
Test status
Simulation time 303550799 ps
CPU time 13.31 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 200692 kb
Host smart-b4016481-67a8-4fcf-be99-bcd69b028765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453299710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2453299710
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2788365946
Short name T450
Test name
Test status
Simulation time 24556943126 ps
CPU time 324.5 seconds
Started Aug 18 06:29:09 PM PDT 24
Finished Aug 18 06:34:33 PM PDT 24
Peak memory 200716 kb
Host smart-ae504463-a69e-41eb-90aa-8bf3cbcd9cf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788365946 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2788365946
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3797979888
Short name T433
Test name
Test status
Simulation time 6594027383 ps
CPU time 84.38 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:30:35 PM PDT 24
Peak memory 200744 kb
Host smart-b8e034c1-540b-4588-99aa-0e5dbaddd4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797979888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3797979888
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.596742643
Short name T36
Test name
Test status
Simulation time 21968646 ps
CPU time 0.6 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:29:16 PM PDT 24
Peak memory 196400 kb
Host smart-95137b08-ea07-477b-8f67-0342bf52f0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596742643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.596742643
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3487103637
Short name T279
Test name
Test status
Simulation time 4429721363 ps
CPU time 66.39 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 06:30:24 PM PDT 24
Peak memory 200740 kb
Host smart-b54d2f23-632b-4b5c-b647-431f1b87567a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487103637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3487103637
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1672599261
Short name T142
Test name
Test status
Simulation time 1078886322 ps
CPU time 58.7 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:30:12 PM PDT 24
Peak memory 200688 kb
Host smart-777af5e6-9bfc-49c8-92d0-1eca2ccbfd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672599261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1672599261
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.865474397
Short name T27
Test name
Test status
Simulation time 3597865139 ps
CPU time 674.99 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:40:41 PM PDT 24
Peak memory 737652 kb
Host smart-220baa55-f955-4009-a3ba-ff6f04ee8b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=865474397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.865474397
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2450196521
Short name T145
Test name
Test status
Simulation time 9369642258 ps
CPU time 121.27 seconds
Started Aug 18 06:29:22 PM PDT 24
Finished Aug 18 06:31:23 PM PDT 24
Peak memory 200824 kb
Host smart-968983f8-4aba-42c8-86ea-a5453caf1204
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450196521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2450196521
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3372877141
Short name T383
Test name
Test status
Simulation time 14811897594 ps
CPU time 124.2 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:31:18 PM PDT 24
Peak memory 200712 kb
Host smart-1917b084-2683-44ea-b330-d3fba32cbc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372877141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3372877141
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1566170873
Short name T213
Test name
Test status
Simulation time 231871688 ps
CPU time 4.18 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:29:17 PM PDT 24
Peak memory 200624 kb
Host smart-5d170309-7856-4315-8b1a-3788d33bf933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566170873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1566170873
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1618222621
Short name T140
Test name
Test status
Simulation time 20411429555 ps
CPU time 2191.67 seconds
Started Aug 18 06:29:16 PM PDT 24
Finished Aug 18 07:05:48 PM PDT 24
Peak memory 744660 kb
Host smart-e4965612-8da3-41d3-b04f-137684645cd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618222621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1618222621
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.1219135823
Short name T447
Test name
Test status
Simulation time 15030190446 ps
CPU time 127.13 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:31:31 PM PDT 24
Peak memory 200816 kb
Host smart-4dd70eaa-493c-4d88-95d9-397b9bdf39bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219135823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.1219135823
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.254958527
Short name T169
Test name
Test status
Simulation time 42311755 ps
CPU time 0.57 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:29:27 PM PDT 24
Peak memory 196572 kb
Host smart-97d56353-413c-48de-9247-b70393d506c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254958527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.254958527
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1725527019
Short name T244
Test name
Test status
Simulation time 173356194 ps
CPU time 7.07 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:29:19 PM PDT 24
Peak memory 200612 kb
Host smart-7ee8fbfd-b9d9-4347-9567-28690744bdfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1725527019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1725527019
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2394720007
Short name T50
Test name
Test status
Simulation time 110422044 ps
CPU time 5.61 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:19 PM PDT 24
Peak memory 200696 kb
Host smart-aba9e1db-71cb-452a-aa93-48452125520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394720007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2394720007
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3167366668
Short name T261
Test name
Test status
Simulation time 29048387467 ps
CPU time 890.61 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:44:11 PM PDT 24
Peak memory 536028 kb
Host smart-1266d887-ea68-477c-b14f-c32868ab6b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167366668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3167366668
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2755565598
Short name T330
Test name
Test status
Simulation time 3626419842 ps
CPU time 222.77 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:32:55 PM PDT 24
Peak memory 200748 kb
Host smart-d8acfade-445f-499e-80ac-316757917c34
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755565598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2755565598
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3567349942
Short name T301
Test name
Test status
Simulation time 10238722598 ps
CPU time 188.14 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:32:29 PM PDT 24
Peak memory 200948 kb
Host smart-d51a3e69-39a5-4b54-b373-44fb6e78528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567349942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3567349942
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2894005913
Short name T501
Test name
Test status
Simulation time 226220280 ps
CPU time 3.38 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 200704 kb
Host smart-8929c448-cd95-44fd-b28b-f9073a48f436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894005913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2894005913
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2314362123
Short name T74
Test name
Test status
Simulation time 90059121319 ps
CPU time 994.23 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:46:02 PM PDT 24
Peak memory 682672 kb
Host smart-5856345c-17a7-4db6-906f-91688b89d853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314362123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2314362123
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1403184867
Short name T437
Test name
Test status
Simulation time 11552236788 ps
CPU time 126.11 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:31:26 PM PDT 24
Peak memory 200756 kb
Host smart-3edcd803-4110-46f4-bf1c-98a169dfe94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403184867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1403184867
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1538093935
Short name T376
Test name
Test status
Simulation time 165566575 ps
CPU time 0.59 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 196428 kb
Host smart-cdf6317b-f42f-40fa-9d33-24a45ccfb496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538093935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1538093935
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1019091417
Short name T516
Test name
Test status
Simulation time 872330760 ps
CPU time 51.69 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 200592 kb
Host smart-26866815-8847-45f9-99b6-58e36f89ce16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019091417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1019091417
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2799923905
Short name T135
Test name
Test status
Simulation time 6326896357 ps
CPU time 74.06 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:30:41 PM PDT 24
Peak memory 208980 kb
Host smart-5d80e8c7-5ec0-449b-92b4-027facc15dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799923905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2799923905
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_error.2022857217
Short name T473
Test name
Test status
Simulation time 1838750690 ps
CPU time 96.49 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:30:50 PM PDT 24
Peak memory 200672 kb
Host smart-e6d7bfc5-3611-4d05-bd40-61faa3e3a64d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022857217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2022857217
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2211859532
Short name T334
Test name
Test status
Simulation time 992694008 ps
CPU time 16.06 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200676 kb
Host smart-acc10b80-9192-4a7e-a9f3-f6518101469d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211859532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2211859532
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2764515925
Short name T182
Test name
Test status
Simulation time 1893755653 ps
CPU time 11.86 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:37 PM PDT 24
Peak memory 200720 kb
Host smart-e399d818-4b8d-41d1-a0ae-41cd9f8e3b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764515925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2764515925
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1875603028
Short name T236
Test name
Test status
Simulation time 81268475609 ps
CPU time 335.89 seconds
Started Aug 18 06:29:11 PM PDT 24
Finished Aug 18 06:34:48 PM PDT 24
Peak memory 217160 kb
Host smart-589bc343-d9aa-4cca-b3fa-1bbe630d9bd5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875603028 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1875603028
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2600353501
Short name T395
Test name
Test status
Simulation time 1023238879 ps
CPU time 14.49 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200544 kb
Host smart-2cd18201-216e-45d2-8be1-32b69160fd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600353501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2600353501
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2629859382
Short name T268
Test name
Test status
Simulation time 49912962 ps
CPU time 0.56 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:29:32 PM PDT 24
Peak memory 195740 kb
Host smart-f141ac51-0b9e-4055-a6ff-f924babc5e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629859382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2629859382
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3242550060
Short name T348
Test name
Test status
Simulation time 3109447325 ps
CPU time 45.19 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:30:18 PM PDT 24
Peak memory 200728 kb
Host smart-dc1fdc94-4ee2-4256-b310-a8e3ff470bc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3242550060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3242550060
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2642294242
Short name T222
Test name
Test status
Simulation time 1379034690 ps
CPU time 25.37 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:29:56 PM PDT 24
Peak memory 200592 kb
Host smart-099107d4-5216-47cf-8c3a-12dd76c11a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642294242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2642294242
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4293803380
Short name T35
Test name
Test status
Simulation time 4980331133 ps
CPU time 808.05 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:42:55 PM PDT 24
Peak memory 619532 kb
Host smart-5212a03d-19ac-4ece-99ba-75ef7b7ac1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293803380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4293803380
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2896696299
Short name T415
Test name
Test status
Simulation time 687921544 ps
CPU time 38.41 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:30:06 PM PDT 24
Peak memory 200684 kb
Host smart-305ee632-1d05-4b91-8c9f-fa8e40699204
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896696299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2896696299
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1461890533
Short name T68
Test name
Test status
Simulation time 3575781873 ps
CPU time 97.4 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 200768 kb
Host smart-7d2b1d27-eb6e-483f-92aa-54ecd88df907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461890533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1461890533
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.97832497
Short name T518
Test name
Test status
Simulation time 683554847 ps
CPU time 16.94 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:29:46 PM PDT 24
Peak memory 200660 kb
Host smart-cfb7f2d4-be20-40db-9787-682d5ad33e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97832497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.97832497
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1507817488
Short name T49
Test name
Test status
Simulation time 32825664417 ps
CPU time 104.03 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:31:05 PM PDT 24
Peak memory 200764 kb
Host smart-5d2518c9-3013-4dea-a4a6-da07d1b17dce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507817488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1507817488
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.239231141
Short name T315
Test name
Test status
Simulation time 28353372904 ps
CPU time 89.85 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:49 PM PDT 24
Peak memory 200736 kb
Host smart-e8f4fcb8-a070-4750-821c-39a2376b72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239231141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.239231141
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1166325002
Short name T178
Test name
Test status
Simulation time 20348581 ps
CPU time 0.58 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:22 PM PDT 24
Peak memory 195720 kb
Host smart-60d66c7f-b5b4-4c29-9b9b-8696b931e252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166325002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1166325002
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2328469017
Short name T486
Test name
Test status
Simulation time 14518793980 ps
CPU time 81.44 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:40 PM PDT 24
Peak memory 200952 kb
Host smart-c9e1600b-2fd0-4c5a-bf0a-65d31fd93966
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328469017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2328469017
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3433790351
Short name T233
Test name
Test status
Simulation time 26569682908 ps
CPU time 48.25 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:30:03 PM PDT 24
Peak memory 200712 kb
Host smart-55d3fc0b-141a-4525-a068-e6bc75852c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433790351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3433790351
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2494340841
Short name T198
Test name
Test status
Simulation time 4591815861 ps
CPU time 856.32 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:43:31 PM PDT 24
Peak memory 702708 kb
Host smart-a55bfe82-1e0e-435e-8a3c-9d1aab716e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494340841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2494340841
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2037582517
Short name T305
Test name
Test status
Simulation time 11467180802 ps
CPU time 67.75 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:30:21 PM PDT 24
Peak memory 200812 kb
Host smart-0242aa63-5158-4bc7-9d1e-ee36e6eb46fc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037582517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2037582517
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3910874499
Short name T500
Test name
Test status
Simulation time 884986735 ps
CPU time 13.55 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 200652 kb
Host smart-3d1bec68-9f8b-4abd-b94e-098fb538133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910874499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3910874499
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.4208285040
Short name T252
Test name
Test status
Simulation time 5958644895 ps
CPU time 8.34 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:21 PM PDT 24
Peak memory 200684 kb
Host smart-905f3354-70d0-4830-8bb4-471be4ca1c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208285040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.4208285040
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2928794664
Short name T187
Test name
Test status
Simulation time 5956982755 ps
CPU time 109.6 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:31:18 PM PDT 24
Peak memory 200736 kb
Host smart-13d199be-0c4b-462a-b141-aefee52f1829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928794664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2928794664
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2174559638
Short name T476
Test name
Test status
Simulation time 13056797510 ps
CPU time 87.89 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:30:48 PM PDT 24
Peak memory 200744 kb
Host smart-cd3fc601-9e5e-4f93-96c5-5cb65acd017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174559638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2174559638
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3482974151
Short name T514
Test name
Test status
Simulation time 53427125 ps
CPU time 0.59 seconds
Started Aug 18 06:28:58 PM PDT 24
Finished Aug 18 06:28:59 PM PDT 24
Peak memory 196604 kb
Host smart-23d77014-fbce-4c4b-b6c8-3427d1ef280c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482974151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3482974151
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.976224764
Short name T197
Test name
Test status
Simulation time 518270576 ps
CPU time 28.97 seconds
Started Aug 18 06:28:51 PM PDT 24
Finished Aug 18 06:29:20 PM PDT 24
Peak memory 200636 kb
Host smart-1dc91467-c999-4011-8ffc-a65fd953fdd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=976224764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.976224764
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2267369629
Short name T177
Test name
Test status
Simulation time 18001606859 ps
CPU time 827.56 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:42:28 PM PDT 24
Peak memory 731380 kb
Host smart-4004cb7b-9c2b-4582-a823-29bd34979ee5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267369629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2267369629
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.848298083
Short name T313
Test name
Test status
Simulation time 20571452565 ps
CPU time 254.6 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:33:21 PM PDT 24
Peak memory 200740 kb
Host smart-665e9497-18d1-4e02-91d8-fac89376cb52
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848298083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.848298083
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1273337386
Short name T255
Test name
Test status
Simulation time 4212154075 ps
CPU time 61.07 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 06:29:48 PM PDT 24
Peak memory 200980 kb
Host smart-783454b3-08e1-428e-b5ca-aa28daf16ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273337386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1273337386
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1565258631
Short name T44
Test name
Test status
Simulation time 61590472 ps
CPU time 0.99 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:29:09 PM PDT 24
Peak memory 219804 kb
Host smart-fe5c79e0-f266-4242-b485-009c87050bd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565258631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1565258631
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1125716332
Short name T217
Test name
Test status
Simulation time 47082598 ps
CPU time 2.02 seconds
Started Aug 18 06:28:49 PM PDT 24
Finished Aug 18 06:28:51 PM PDT 24
Peak memory 200660 kb
Host smart-1f61837c-4694-46b2-85ab-7944c413e2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125716332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1125716332
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1973770958
Short name T155
Test name
Test status
Simulation time 1074748173 ps
CPU time 37.92 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:29:15 PM PDT 24
Peak memory 200684 kb
Host smart-6e9bc4f8-1225-44f1-8744-443f696367ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1973770958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1973770958
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3801755087
Short name T331
Test name
Test status
Simulation time 6177421888 ps
CPU time 92.87 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:30:36 PM PDT 24
Peak memory 200596 kb
Host smart-0539ea85-0c89-431f-a5a4-7dc5697df8f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3801755087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3801755087
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2822911840
Short name T337
Test name
Test status
Simulation time 2913730261 ps
CPU time 109.49 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:30:29 PM PDT 24
Peak memory 200700 kb
Host smart-b61b3e69-6573-4c62-b1b8-82fc5a2c3385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2822911840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2822911840
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2457935643
Short name T297
Test name
Test status
Simulation time 36911241947 ps
CPU time 534.99 seconds
Started Aug 18 06:29:03 PM PDT 24
Finished Aug 18 06:37:58 PM PDT 24
Peak memory 200536 kb
Host smart-26ff0c59-6c86-457e-ba3a-f778bbd3667e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2457935643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2457935643
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1301991412
Short name T417
Test name
Test status
Simulation time 426414185588 ps
CPU time 2880.76 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 07:16:45 PM PDT 24
Peak memory 216028 kb
Host smart-dda52717-854e-4bbe-b6a3-72d4de447b83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1301991412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1301991412
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2474322585
Short name T445
Test name
Test status
Simulation time 225094425398 ps
CPU time 2511.85 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 07:10:35 PM PDT 24
Peak memory 216248 kb
Host smart-16ec4b66-bd8c-47f2-9de2-c5650220d949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474322585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2474322585
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1488396299
Short name T371
Test name
Test status
Simulation time 5636941229 ps
CPU time 122.14 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:30:43 PM PDT 24
Peak memory 200768 kb
Host smart-5b124e50-21d2-49a5-bcd9-8a53957d25ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488396299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1488396299
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3122371085
Short name T167
Test name
Test status
Simulation time 15105358 ps
CPU time 0.62 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:29:21 PM PDT 24
Peak memory 196724 kb
Host smart-64ed2199-df3c-468b-a6e3-c61d57f07ffa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122371085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3122371085
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.896758528
Short name T285
Test name
Test status
Simulation time 361131293 ps
CPU time 21.92 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:29:57 PM PDT 24
Peak memory 200732 kb
Host smart-04a64120-2e03-45bc-8eec-56b8a5a219de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=896758528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.896758528
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.847150748
Short name T454
Test name
Test status
Simulation time 7060816892 ps
CPU time 63.26 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:30:35 PM PDT 24
Peak memory 200756 kb
Host smart-71a840bd-10d7-4697-acc7-d45bc2aa20a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847150748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.847150748
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2013099594
Short name T494
Test name
Test status
Simulation time 2653412224 ps
CPU time 210.64 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 06:32:49 PM PDT 24
Peak memory 477776 kb
Host smart-347d68b9-d919-4b5e-9ce6-de05ed80fbd8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013099594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2013099594
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3084216292
Short name T256
Test name
Test status
Simulation time 2674533443 ps
CPU time 74.33 seconds
Started Aug 18 06:29:12 PM PDT 24
Finished Aug 18 06:30:27 PM PDT 24
Peak memory 200736 kb
Host smart-e2a1e1db-851b-4db2-b938-282583b86aec
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084216292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3084216292
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1767099987
Short name T394
Test name
Test status
Simulation time 10127385478 ps
CPU time 96.23 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 208980 kb
Host smart-e0c4be5d-38af-49b2-9152-4c152c487e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767099987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1767099987
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2882173403
Short name T128
Test name
Test status
Simulation time 6685622382 ps
CPU time 10.13 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:29:44 PM PDT 24
Peak memory 200752 kb
Host smart-c503ec8c-fc20-42e1-acb3-cfd7bbf77655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882173403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2882173403
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.478489313
Short name T505
Test name
Test status
Simulation time 97017981147 ps
CPU time 2422.87 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 07:09:51 PM PDT 24
Peak memory 779700 kb
Host smart-1ad3b713-fdc3-4002-a2bd-05b7baa25ed9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478489313 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.478489313
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2486058611
Short name T346
Test name
Test status
Simulation time 26799855516 ps
CPU time 83.65 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:30:39 PM PDT 24
Peak memory 200812 kb
Host smart-a1f12823-14bb-40b9-b49a-bb8d1d813aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486058611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2486058611
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1929770399
Short name T489
Test name
Test status
Simulation time 42129742 ps
CPU time 0.55 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:29:14 PM PDT 24
Peak memory 196756 kb
Host smart-036bb8f5-5a05-4a1e-97a9-95538a99d63f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929770399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1929770399
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3087141718
Short name T18
Test name
Test status
Simulation time 1163955642 ps
CPU time 66.7 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:30:22 PM PDT 24
Peak memory 200696 kb
Host smart-92f1ccfb-56cc-4be0-bd16-ca1e2ca977af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3087141718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3087141718
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3819687043
Short name T314
Test name
Test status
Simulation time 3200816162 ps
CPU time 27.29 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:48 PM PDT 24
Peak memory 200672 kb
Host smart-c9bb6f27-5abb-4ed0-845c-12d5e1d206fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819687043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3819687043
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3640501184
Short name T275
Test name
Test status
Simulation time 12614743629 ps
CPU time 1210.12 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:49:38 PM PDT 24
Peak memory 769520 kb
Host smart-4a529dc9-0c96-4b17-8b31-967cf52e87f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640501184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3640501184
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4046984940
Short name T212
Test name
Test status
Simulation time 2011931737 ps
CPU time 37.48 seconds
Started Aug 18 06:29:34 PM PDT 24
Finished Aug 18 06:30:12 PM PDT 24
Peak memory 200608 kb
Host smart-a5abd7cd-1464-4c95-9f91-9bef56dd3a92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046984940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4046984940
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.387586074
Short name T237
Test name
Test status
Simulation time 3089674252 ps
CPU time 38.71 seconds
Started Aug 18 06:29:15 PM PDT 24
Finished Aug 18 06:29:54 PM PDT 24
Peak memory 200708 kb
Host smart-dfc9ade6-3cc5-4220-affb-f4a5af19e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387586074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.387586074
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2746526375
Short name T354
Test name
Test status
Simulation time 242520056 ps
CPU time 10.51 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 200688 kb
Host smart-36178978-0096-481c-b6bd-293dbceecaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746526375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2746526375
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.189426396
Short name T359
Test name
Test status
Simulation time 508655691705 ps
CPU time 3158.24 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 07:22:12 PM PDT 24
Peak memory 747376 kb
Host smart-f31a925c-5536-4289-b651-64b572043e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189426396 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.189426396
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2589737857
Short name T171
Test name
Test status
Simulation time 2537308430 ps
CPU time 32.52 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:29:59 PM PDT 24
Peak memory 200748 kb
Host smart-18471146-f6b9-4acd-85c3-fd6c8edd1057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589737857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2589737857
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1830611954
Short name T520
Test name
Test status
Simulation time 59457061 ps
CPU time 0.62 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:29:20 PM PDT 24
Peak memory 196736 kb
Host smart-305a0369-2e0d-4333-9013-9acda6d0c68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830611954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1830611954
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2497736545
Short name T479
Test name
Test status
Simulation time 10074597134 ps
CPU time 106.67 seconds
Started Aug 18 06:29:40 PM PDT 24
Finished Aug 18 06:31:27 PM PDT 24
Peak memory 200940 kb
Host smart-115f0802-d9c3-4bcf-9594-af04844bf96f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497736545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2497736545
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3436856752
Short name T151
Test name
Test status
Simulation time 946092467 ps
CPU time 15.95 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200704 kb
Host smart-5aec4ca7-ad36-4668-bb89-526be07741a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436856752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3436856752
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.531479941
Short name T372
Test name
Test status
Simulation time 419552870 ps
CPU time 50.31 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:30:17 PM PDT 24
Peak memory 318116 kb
Host smart-fccc1598-5b50-4fc7-8ebf-a4934f29d7bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=531479941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.531479941
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3634084927
Short name T515
Test name
Test status
Simulation time 434469745 ps
CPU time 3.42 seconds
Started Aug 18 06:29:34 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 200540 kb
Host smart-722e803b-565d-4c0f-b914-35fcd881a018
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634084927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3634084927
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3476023028
Short name T328
Test name
Test status
Simulation time 73126549074 ps
CPU time 135.82 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:31:44 PM PDT 24
Peak memory 200768 kb
Host smart-8a0bcc48-45da-4979-bd88-922581b35489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476023028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3476023028
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3204133256
Short name T431
Test name
Test status
Simulation time 2877102056 ps
CPU time 5.52 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:29:37 PM PDT 24
Peak memory 200704 kb
Host smart-18fb43eb-9211-4761-950a-a00aee45decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204133256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3204133256
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1936545436
Short name T13
Test name
Test status
Simulation time 33256622231 ps
CPU time 217.51 seconds
Started Aug 18 06:29:13 PM PDT 24
Finished Aug 18 06:32:51 PM PDT 24
Peak memory 200768 kb
Host smart-5ce65283-41a2-4805-a718-8efef19e8b20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936545436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1936545436
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.4039719879
Short name T508
Test name
Test status
Simulation time 2961040690 ps
CPU time 76.02 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:35 PM PDT 24
Peak memory 200748 kb
Host smart-9d06498b-66b3-4f73-a799-3d465df3feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039719879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.4039719879
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2511609106
Short name T152
Test name
Test status
Simulation time 32117135 ps
CPU time 0.62 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:26 PM PDT 24
Peak memory 196748 kb
Host smart-6929ad3e-b244-4515-9827-945e74e1fe84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511609106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2511609106
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4204225084
Short name T19
Test name
Test status
Simulation time 347895972 ps
CPU time 20.17 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:29:47 PM PDT 24
Peak memory 200688 kb
Host smart-e67ffa1c-9360-4af6-9740-952a4ccadcd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4204225084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4204225084
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1416367955
Short name T160
Test name
Test status
Simulation time 19711961 ps
CPU time 0.71 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 197292 kb
Host smart-c2b2ccae-feac-4787-b3dc-cbf2f6a4412c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416367955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1416367955
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4106440311
Short name T474
Test name
Test status
Simulation time 1999691592 ps
CPU time 119.24 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:31:31 PM PDT 24
Peak memory 355428 kb
Host smart-66892b1a-c839-41f2-b2fd-8db2f867c1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4106440311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4106440311
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1450482505
Short name T511
Test name
Test status
Simulation time 11532213371 ps
CPU time 42 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:30:02 PM PDT 24
Peak memory 200656 kb
Host smart-d2de454b-e352-4afe-87e9-460a0ce64f9d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450482505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1450482505
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3360310656
Short name T24
Test name
Test status
Simulation time 1650251473 ps
CPU time 39.53 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:30:03 PM PDT 24
Peak memory 200700 kb
Host smart-dce5430a-7faf-4fe7-b2c2-83bfa38f214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360310656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3360310656
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2725895471
Short name T243
Test name
Test status
Simulation time 124622758 ps
CPU time 2.43 seconds
Started Aug 18 06:29:18 PM PDT 24
Finished Aug 18 06:29:20 PM PDT 24
Peak memory 200664 kb
Host smart-9007a9ce-2d8d-41b7-8551-eb12df35ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725895471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2725895471
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3253379773
Short name T278
Test name
Test status
Simulation time 16986363345 ps
CPU time 873.12 seconds
Started Aug 18 06:29:16 PM PDT 24
Finished Aug 18 06:43:50 PM PDT 24
Peak memory 200804 kb
Host smart-c5690eea-8dd2-45c3-87ed-f541d08f804a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253379773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3253379773
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3050707520
Short name T402
Test name
Test status
Simulation time 251446346 ps
CPU time 13.98 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:29:40 PM PDT 24
Peak memory 200628 kb
Host smart-7a7d44c9-1d28-4277-a805-86e03fdee09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050707520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3050707520
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2364935413
Short name T51
Test name
Test status
Simulation time 12439434 ps
CPU time 0.58 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:29:33 PM PDT 24
Peak memory 195708 kb
Host smart-809d10ba-70b3-48c5-807c-bbbe7bd96f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364935413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2364935413
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1397805018
Short name T4
Test name
Test status
Simulation time 12519960853 ps
CPU time 75.65 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:30:48 PM PDT 24
Peak memory 200792 kb
Host smart-92f8391e-3d5e-4e02-9da4-9d92f847f4e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1397805018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1397805018
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.774046845
Short name T523
Test name
Test status
Simulation time 209275007 ps
CPU time 11.02 seconds
Started Aug 18 06:29:41 PM PDT 24
Finished Aug 18 06:29:52 PM PDT 24
Peak memory 200724 kb
Host smart-1bbb2d7a-f01a-439a-b697-71a5c0a080c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774046845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.774046845
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3549359462
Short name T229
Test name
Test status
Simulation time 994280620 ps
CPU time 47.61 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:30:16 PM PDT 24
Peak memory 322868 kb
Host smart-2e373100-748d-49da-9cc4-aea436fe6b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549359462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3549359462
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.2088564618
Short name T423
Test name
Test status
Simulation time 4863219368 ps
CPU time 75.13 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:30:39 PM PDT 24
Peak memory 200704 kb
Host smart-c6c5ed17-bdff-4442-8ca8-9be16b8a7379
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088564618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.2088564618
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1707445564
Short name T381
Test name
Test status
Simulation time 4573652539 ps
CPU time 62.95 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:30:28 PM PDT 24
Peak memory 200820 kb
Host smart-570ec177-d7e3-4a9c-a6e6-12dde39c770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707445564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1707445564
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.981675315
Short name T408
Test name
Test status
Simulation time 1311723165 ps
CPU time 12.1 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200660 kb
Host smart-71b9058c-194e-458d-a23b-22aaac84105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981675315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.981675315
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2277498565
Short name T72
Test name
Test status
Simulation time 86620231016 ps
CPU time 574.28 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:39:04 PM PDT 24
Peak memory 200784 kb
Host smart-1121ce8b-2b83-447a-8f07-47c59ac55e3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277498565 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2277498565
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1782483137
Short name T262
Test name
Test status
Simulation time 126484613216 ps
CPU time 153.45 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:32:01 PM PDT 24
Peak memory 200732 kb
Host smart-42a1d551-09c3-47c5-ac97-6b03015e594a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782483137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1782483137
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1811565288
Short name T302
Test name
Test status
Simulation time 49871834 ps
CPU time 0.59 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:29:32 PM PDT 24
Peak memory 197436 kb
Host smart-390ea2af-ad55-4808-9abb-425718cdeb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811565288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1811565288
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.459053491
Short name T286
Test name
Test status
Simulation time 807641656 ps
CPU time 43.32 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:30:12 PM PDT 24
Peak memory 200648 kb
Host smart-9f43cace-aacc-428d-9402-ffb3ea46dd21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459053491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.459053491
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2411759087
Short name T460
Test name
Test status
Simulation time 1964232177 ps
CPU time 51.55 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:30:17 PM PDT 24
Peak memory 200668 kb
Host smart-9d357567-df5c-4cf7-b272-4a2582f91ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411759087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2411759087
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1001379706
Short name T527
Test name
Test status
Simulation time 18686512200 ps
CPU time 2186.4 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 07:05:52 PM PDT 24
Peak memory 786948 kb
Host smart-a7542394-2443-4add-803c-5c883e3a6bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1001379706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1001379706
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3717848429
Short name T183
Test name
Test status
Simulation time 48931481746 ps
CPU time 153.86 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:32:12 PM PDT 24
Peak memory 200736 kb
Host smart-364ae46b-a88f-4f03-bd9f-83130982931f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717848429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3717848429
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1404394239
Short name T367
Test name
Test status
Simulation time 2961965760 ps
CPU time 156.35 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:32:06 PM PDT 24
Peak memory 199292 kb
Host smart-62bf9e72-2733-4010-b34c-e07449c0eb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404394239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1404394239
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2910132217
Short name T319
Test name
Test status
Simulation time 491443284 ps
CPU time 8.68 seconds
Started Aug 18 06:29:21 PM PDT 24
Finished Aug 18 06:29:30 PM PDT 24
Peak memory 200748 kb
Host smart-8f45a3a3-409d-47a9-b6ec-bcb8e7d48ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910132217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2910132217
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2692849513
Short name T75
Test name
Test status
Simulation time 254684288678 ps
CPU time 2557.25 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 07:12:05 PM PDT 24
Peak memory 766472 kb
Host smart-24524d51-b8da-4581-8aa7-e89e3b53fa79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692849513 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2692849513
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2404396142
Short name T309
Test name
Test status
Simulation time 18607440213 ps
CPU time 108.67 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:31:09 PM PDT 24
Peak memory 200776 kb
Host smart-bc8843fc-89c1-4b29-8ea8-6dc286c4f7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404396142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2404396142
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.965903934
Short name T427
Test name
Test status
Simulation time 14206628 ps
CPU time 0.57 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:29:25 PM PDT 24
Peak memory 197432 kb
Host smart-f88bba5c-866d-4c63-b934-1a2196c6d66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965903934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.965903934
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.435683417
Short name T221
Test name
Test status
Simulation time 3212127317 ps
CPU time 45.35 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:30:23 PM PDT 24
Peak memory 200748 kb
Host smart-83b90269-5dee-4ffd-ab9a-3ed989ce724e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=435683417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.435683417
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2705422327
Short name T245
Test name
Test status
Simulation time 9209941820 ps
CPU time 62.14 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:30:29 PM PDT 24
Peak memory 209024 kb
Host smart-3ece0ffb-fcf5-4c77-82f7-4acc08118ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705422327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2705422327
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.778562579
Short name T265
Test name
Test status
Simulation time 3302981876 ps
CPU time 588.09 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:39:16 PM PDT 24
Peak memory 657724 kb
Host smart-9e7a367a-981e-4677-9dfe-6a3189628cd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778562579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.778562579
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3251636493
Short name T1
Test name
Test status
Simulation time 10407782713 ps
CPU time 128.62 seconds
Started Aug 18 06:29:16 PM PDT 24
Finished Aug 18 06:31:25 PM PDT 24
Peak memory 200740 kb
Host smart-e4786c12-cc9c-4d7a-a255-5e0f1df471b8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251636493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3251636493
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2694659411
Short name T82
Test name
Test status
Simulation time 14477061782 ps
CPU time 89.81 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:30:59 PM PDT 24
Peak memory 200756 kb
Host smart-2ad85e9a-7069-417c-94dc-41051abb5c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694659411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2694659411
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1683739295
Short name T389
Test name
Test status
Simulation time 1565713616 ps
CPU time 8.95 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:29:44 PM PDT 24
Peak memory 200696 kb
Host smart-673b1e62-48e0-4733-8283-0fcf6a114d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683739295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1683739295
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1501861964
Short name T235
Test name
Test status
Simulation time 58142973468 ps
CPU time 930.21 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:45:04 PM PDT 24
Peak memory 217144 kb
Host smart-af09423a-03a6-4d31-b93e-f34268f2efa4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501861964 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1501861964
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3680566531
Short name T487
Test name
Test status
Simulation time 4077643549 ps
CPU time 45.02 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 200756 kb
Host smart-66a95d78-a346-4397-9fff-8582e5250687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680566531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3680566531
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4209145949
Short name T150
Test name
Test status
Simulation time 39494501 ps
CPU time 0.58 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:29:31 PM PDT 24
Peak memory 197440 kb
Host smart-a34bc624-6e28-47f6-ac94-302f4004866a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209145949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4209145949
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.1389703628
Short name T149
Test name
Test status
Simulation time 4266033256 ps
CPU time 44.33 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:30:10 PM PDT 24
Peak memory 200688 kb
Host smart-254a7ce6-70d8-4a4c-b9fe-226cf04018e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1389703628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.1389703628
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2827979761
Short name T478
Test name
Test status
Simulation time 2546088608 ps
CPU time 35.31 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:30:03 PM PDT 24
Peak memory 200752 kb
Host smart-cd6564fd-0d0c-401d-9047-b22bcaf390f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827979761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2827979761
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3595053724
Short name T131
Test name
Test status
Simulation time 19888524306 ps
CPU time 988.34 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:45:53 PM PDT 24
Peak memory 735032 kb
Host smart-c8a3d2f9-7e44-46ba-ada8-d424740079eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595053724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3595053724
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3305872243
Short name T25
Test name
Test status
Simulation time 16842970025 ps
CPU time 31.24 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:30:03 PM PDT 24
Peak memory 200708 kb
Host smart-6aa3db30-e862-47d7-afb0-b202ca2b0f4a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305872243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3305872243
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.756721036
Short name T228
Test name
Test status
Simulation time 7934305145 ps
CPU time 120.17 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:31:23 PM PDT 24
Peak memory 208932 kb
Host smart-0fd10efa-c51e-4f39-a6ee-2857b4a6475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756721036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.756721036
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1955021174
Short name T481
Test name
Test status
Simulation time 467852280 ps
CPU time 10.38 seconds
Started Aug 18 06:29:22 PM PDT 24
Finished Aug 18 06:29:33 PM PDT 24
Peak memory 200624 kb
Host smart-4b636c47-8676-4922-bcf9-0aca94ffa4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955021174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1955021174
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2542978697
Short name T73
Test name
Test status
Simulation time 489201674024 ps
CPU time 1808.94 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:59:38 PM PDT 24
Peak memory 727024 kb
Host smart-e677bbf6-3cea-4e3a-b313-2512e6f708a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542978697 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2542978697
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.1087458870
Short name T230
Test name
Test status
Simulation time 28388191930 ps
CPU time 99.86 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 200688 kb
Host smart-42a0b1a9-ed0f-4e6c-808e-9d036db6434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087458870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.1087458870
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1388083855
Short name T365
Test name
Test status
Simulation time 29279442 ps
CPU time 0.6 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:29:28 PM PDT 24
Peak memory 195732 kb
Host smart-3276c1b8-8f6a-45eb-bb16-78d34f381756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388083855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1388083855
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4002624783
Short name T488
Test name
Test status
Simulation time 4198175747 ps
CPU time 72.32 seconds
Started Aug 18 06:29:22 PM PDT 24
Finished Aug 18 06:30:34 PM PDT 24
Peak memory 200748 kb
Host smart-4f6b0139-8801-4896-a266-2fb59c84bb88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002624783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4002624783
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1007590035
Short name T483
Test name
Test status
Simulation time 2025520822 ps
CPU time 26.99 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:29:55 PM PDT 24
Peak memory 200692 kb
Host smart-35651645-d197-457a-88d6-b486ba15ae1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007590035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1007590035
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1313697515
Short name T259
Test name
Test status
Simulation time 1651193330 ps
CPU time 266.17 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:33:53 PM PDT 24
Peak memory 448856 kb
Host smart-3b85708f-996e-4d41-a3b7-ae2510b8976c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313697515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1313697515
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2267794335
Short name T522
Test name
Test status
Simulation time 16612654572 ps
CPU time 74.43 seconds
Started Aug 18 06:29:19 PM PDT 24
Finished Aug 18 06:30:33 PM PDT 24
Peak memory 200696 kb
Host smart-ac3c214d-a8ec-477d-979a-817c09eb19c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267794335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2267794335
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1964534836
Short name T480
Test name
Test status
Simulation time 50840849009 ps
CPU time 67.05 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:30:34 PM PDT 24
Peak memory 217152 kb
Host smart-81863e2c-b8ff-4ace-9ff2-fe4e7b7c2af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964534836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1964534836
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2083563999
Short name T289
Test name
Test status
Simulation time 40476122 ps
CPU time 2.26 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:29:32 PM PDT 24
Peak memory 200580 kb
Host smart-608412c4-af4e-4037-815d-23ec8af17cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083563999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2083563999
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1061917987
Short name T20
Test name
Test status
Simulation time 58245431679 ps
CPU time 1551.95 seconds
Started Aug 18 06:29:22 PM PDT 24
Finished Aug 18 06:55:15 PM PDT 24
Peak memory 755384 kb
Host smart-2f66a186-18cd-4ab8-a3ec-0b957821ce65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061917987 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1061917987
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.4145768178
Short name T200
Test name
Test status
Simulation time 3994621752 ps
CPU time 94.62 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:31:04 PM PDT 24
Peak memory 200764 kb
Host smart-9268a490-fcee-4627-8a08-63351fe51c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145768178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.4145768178
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.671998469
Short name T420
Test name
Test status
Simulation time 177367456 ps
CPU time 0.58 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:29:28 PM PDT 24
Peak memory 196756 kb
Host smart-aa6269c1-3991-4c31-8858-59a1a88a866a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671998469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.671998469
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3734715409
Short name T324
Test name
Test status
Simulation time 820774426 ps
CPU time 25.77 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:29:49 PM PDT 24
Peak memory 200740 kb
Host smart-81d92ec2-32f9-4d2e-821d-a419a7225f49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734715409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3734715409
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2856439514
Short name T138
Test name
Test status
Simulation time 2008056427 ps
CPU time 52.11 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:30:15 PM PDT 24
Peak memory 200712 kb
Host smart-c03cbe15-485f-46ca-980e-3e05b23c24c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856439514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2856439514
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1830648736
Short name T204
Test name
Test status
Simulation time 7346793921 ps
CPU time 371.32 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:35:36 PM PDT 24
Peak memory 653416 kb
Host smart-661cd977-c918-42fa-8a28-5a988fffebec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830648736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1830648736
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.416828667
Short name T484
Test name
Test status
Simulation time 16647569481 ps
CPU time 52.52 seconds
Started Aug 18 06:29:20 PM PDT 24
Finished Aug 18 06:30:13 PM PDT 24
Peak memory 200856 kb
Host smart-6f652a9d-ed2f-4deb-a33e-fc55c8ffa2fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416828667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.416828667
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1166202256
Short name T491
Test name
Test status
Simulation time 11285768286 ps
CPU time 50.48 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:30:15 PM PDT 24
Peak memory 200700 kb
Host smart-752fe6a9-9300-4548-8e3f-0a2a8465889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166202256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1166202256
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.456347632
Short name T379
Test name
Test status
Simulation time 6915121341 ps
CPU time 6.11 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:29:33 PM PDT 24
Peak memory 200760 kb
Host smart-4b10f992-808b-4545-ab98-a8de891cf5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456347632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.456347632
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2173374011
Short name T430
Test name
Test status
Simulation time 68291957450 ps
CPU time 2466.86 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 07:10:46 PM PDT 24
Peak memory 741040 kb
Host smart-5ce96ac7-a654-4cb6-9f42-f05dc2dddc08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173374011 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2173374011
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3834876409
Short name T373
Test name
Test status
Simulation time 2423525055 ps
CPU time 16.48 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:29:48 PM PDT 24
Peak memory 200728 kb
Host smart-c471dfe1-283b-45fc-adaf-b9275b6f0d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834876409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3834876409
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4219029283
Short name T490
Test name
Test status
Simulation time 26922212 ps
CPU time 0.6 seconds
Started Aug 18 06:29:04 PM PDT 24
Finished Aug 18 06:29:05 PM PDT 24
Peak memory 196740 kb
Host smart-df575898-402c-4236-a998-5f8ad3f580dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219029283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4219029283
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4137417405
Short name T66
Test name
Test status
Simulation time 129156667 ps
CPU time 3.73 seconds
Started Aug 18 06:29:04 PM PDT 24
Finished Aug 18 06:29:08 PM PDT 24
Peak memory 200560 kb
Host smart-917bc917-8184-42ea-970c-9e54b424e630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4137417405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4137417405
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1552734607
Short name T426
Test name
Test status
Simulation time 2007254985 ps
CPU time 34.35 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:29:09 PM PDT 24
Peak memory 200676 kb
Host smart-fe469882-19f1-4266-aa31-20245111237b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552734607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1552734607
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.380198016
Short name T203
Test name
Test status
Simulation time 13856064248 ps
CPU time 381.74 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:34:59 PM PDT 24
Peak memory 608080 kb
Host smart-7d4a29ed-cbb0-4dae-8051-05ebd71dc2c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=380198016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.380198016
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.580691843
Short name T143
Test name
Test status
Simulation time 40360903613 ps
CPU time 124.56 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:30:39 PM PDT 24
Peak memory 200692 kb
Host smart-d50ed08f-2ae5-4ec0-b2bd-fcd14481f95d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580691843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.580691843
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.248806288
Short name T247
Test name
Test status
Simulation time 9770513675 ps
CPU time 97.09 seconds
Started Aug 18 06:29:01 PM PDT 24
Finished Aug 18 06:30:38 PM PDT 24
Peak memory 200756 kb
Host smart-fd46e063-04b4-49ee-b783-6da7a040c3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248806288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.248806288
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.822415366
Short name T45
Test name
Test status
Simulation time 322188604 ps
CPU time 1 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:28:37 PM PDT 24
Peak memory 220028 kb
Host smart-0a531f52-5570-4dd7-b08b-e1209187f7d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822415366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.822415366
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2038825460
Short name T193
Test name
Test status
Simulation time 2662784595 ps
CPU time 16.49 seconds
Started Aug 18 06:29:06 PM PDT 24
Finished Aug 18 06:29:22 PM PDT 24
Peak memory 200596 kb
Host smart-57478d10-06f7-4b28-a0d0-bd1d9efc0f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038825460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2038825460
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3752060457
Short name T115
Test name
Test status
Simulation time 170204584322 ps
CPU time 1100.11 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 06:46:56 PM PDT 24
Peak memory 694868 kb
Host smart-4265b681-fff5-415a-aa18-a7716ec153df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752060457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3752060457
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.2166352234
Short name T9
Test name
Test status
Simulation time 16737359573 ps
CPU time 248.33 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:32:45 PM PDT 24
Peak memory 216468 kb
Host smart-818218b2-14cb-46f2-99f0-7df299a6a5d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166352234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.2166352234
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.339904250
Short name T154
Test name
Test status
Simulation time 12138141335 ps
CPU time 50.57 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:29:27 PM PDT 24
Peak memory 200668 kb
Host smart-c208c2e6-0a4d-40c3-8e4d-26bb022fca4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=339904250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.339904250
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1010229356
Short name T398
Test name
Test status
Simulation time 32387825058 ps
CPU time 113 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:30:31 PM PDT 24
Peak memory 200744 kb
Host smart-6684677b-faca-416b-b035-850118ec4dac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1010229356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1010229356
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3069962684
Short name T48
Test name
Test status
Simulation time 4202845116 ps
CPU time 72.28 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:29:51 PM PDT 24
Peak memory 200800 kb
Host smart-a2a6cd7d-6d45-40ac-9bf1-1d2a796fea61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3069962684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3069962684
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1716909588
Short name T224
Test name
Test status
Simulation time 10497359459 ps
CPU time 582.18 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:38:18 PM PDT 24
Peak memory 200764 kb
Host smart-9b236f99-405b-4680-bc4d-784cb4e0fde3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1716909588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1716909588
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.893538563
Short name T327
Test name
Test status
Simulation time 81623354614 ps
CPU time 2579.54 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 07:11:42 PM PDT 24
Peak memory 216272 kb
Host smart-6383e006-f06d-4e43-a2ea-db2d69a11cb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=893538563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.893538563
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3193138051
Short name T316
Test name
Test status
Simulation time 139675837889 ps
CPU time 2579.37 seconds
Started Aug 18 06:28:34 PM PDT 24
Finished Aug 18 07:11:36 PM PDT 24
Peak memory 216076 kb
Host smart-e266314a-8833-4c39-a573-d1b1567fd11d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3193138051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3193138051
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1182566795
Short name T195
Test name
Test status
Simulation time 10580921142 ps
CPU time 34.09 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:29:12 PM PDT 24
Peak memory 200788 kb
Host smart-6efc700a-76f1-45b3-8c6c-3c605207be36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182566795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1182566795
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2095686072
Short name T242
Test name
Test status
Simulation time 24994741 ps
CPU time 0.59 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:29:29 PM PDT 24
Peak memory 196380 kb
Host smart-39078133-918e-4e5e-8182-cffd4fd8413f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095686072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2095686072
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1892433691
Short name T199
Test name
Test status
Simulation time 2653891245 ps
CPU time 39.23 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:30:14 PM PDT 24
Peak memory 200772 kb
Host smart-8958bd2f-ebcc-498b-a1eb-436da132e2d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892433691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1892433691
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1316359927
Short name T440
Test name
Test status
Simulation time 1013966531 ps
CPU time 57.67 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:30:27 PM PDT 24
Peak memory 200620 kb
Host smart-cf683c22-816a-4340-901d-0fe2d7a5443f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316359927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1316359927
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.15512682
Short name T409
Test name
Test status
Simulation time 3103939721 ps
CPU time 562.71 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:38:47 PM PDT 24
Peak memory 663280 kb
Host smart-1b58784b-a768-48e8-9882-c902075f14df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15512682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.15512682
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2353480439
Short name T276
Test name
Test status
Simulation time 7367953998 ps
CPU time 202.96 seconds
Started Aug 18 06:29:37 PM PDT 24
Finished Aug 18 06:33:00 PM PDT 24
Peak memory 200720 kb
Host smart-acb37241-dc51-44a9-8211-b138e5ba72dd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353480439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2353480439
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2884344756
Short name T293
Test name
Test status
Simulation time 1769352123 ps
CPU time 98.24 seconds
Started Aug 18 06:29:34 PM PDT 24
Finished Aug 18 06:31:12 PM PDT 24
Peak memory 200724 kb
Host smart-c61d530f-1c43-4279-af70-adfce211deb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884344756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2884344756
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.4213832972
Short name T180
Test name
Test status
Simulation time 920525740 ps
CPU time 11.54 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:36 PM PDT 24
Peak memory 200740 kb
Host smart-97064e2c-6a10-4ad9-b9a7-59542a13c002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213832972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.4213832972
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3602835808
Short name T344
Test name
Test status
Simulation time 26374018106 ps
CPU time 1713.42 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:58:02 PM PDT 24
Peak memory 731064 kb
Host smart-dee0eb82-1d98-4d8d-9a69-b737bf15b476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602835808 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3602835808
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2487924218
Short name T88
Test name
Test status
Simulation time 10945675908 ps
CPU time 123.14 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:31:36 PM PDT 24
Peak memory 200736 kb
Host smart-be973cf9-51e2-4227-b169-0b9205ed9354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487924218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2487924218
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.371663391
Short name T311
Test name
Test status
Simulation time 14761526 ps
CPU time 0.65 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:29:23 PM PDT 24
Peak memory 197416 kb
Host smart-064d4968-8003-4121-9bee-7bb27a232928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371663391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.371663391
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.283361481
Short name T320
Test name
Test status
Simulation time 905063332 ps
CPU time 50.57 seconds
Started Aug 18 06:29:36 PM PDT 24
Finished Aug 18 06:30:27 PM PDT 24
Peak memory 200704 kb
Host smart-46e7c0d6-279b-4d27-b041-4b49e49b4687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283361481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.283361481
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.4210812455
Short name T181
Test name
Test status
Simulation time 4030743140 ps
CPU time 160.13 seconds
Started Aug 18 06:29:23 PM PDT 24
Finished Aug 18 06:32:04 PM PDT 24
Peak memory 577296 kb
Host smart-861123d9-1b4e-4f92-b7e3-924eb7df220f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4210812455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.4210812455
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2673722135
Short name T127
Test name
Test status
Simulation time 451856981 ps
CPU time 23.85 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:29:49 PM PDT 24
Peak memory 200564 kb
Host smart-0931008f-256b-42f4-bcd1-b81d7f17fba2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673722135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2673722135
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3556422760
Short name T351
Test name
Test status
Simulation time 2337330135 ps
CPU time 19.68 seconds
Started Aug 18 06:29:34 PM PDT 24
Finished Aug 18 06:29:54 PM PDT 24
Peak memory 200768 kb
Host smart-109d9428-866c-4901-ad11-f1cb66d6e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556422760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3556422760
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1108816293
Short name T358
Test name
Test status
Simulation time 3013031110 ps
CPU time 4.67 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 200804 kb
Host smart-ff032123-7021-466c-ad0b-a04c727427f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108816293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1108816293
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.3144820516
Short name T277
Test name
Test status
Simulation time 8018469752 ps
CPU time 108.81 seconds
Started Aug 18 06:29:27 PM PDT 24
Finished Aug 18 06:31:16 PM PDT 24
Peak memory 200816 kb
Host smart-6cc497d1-32d0-471e-a6fa-eab836221031
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144820516 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.3144820516
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3307502239
Short name T392
Test name
Test status
Simulation time 5394679836 ps
CPU time 88.47 seconds
Started Aug 18 06:29:25 PM PDT 24
Finished Aug 18 06:30:53 PM PDT 24
Peak memory 200688 kb
Host smart-25b17c2f-e373-4fa4-a29b-2d49d3da11b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307502239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3307502239
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4079718941
Short name T153
Test name
Test status
Simulation time 40570186 ps
CPU time 0.59 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:29:33 PM PDT 24
Peak memory 195748 kb
Host smart-c85ebf38-5ff6-454b-80b5-fe7a8a12b392
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079718941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4079718941
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1178824873
Short name T226
Test name
Test status
Simulation time 2080655576 ps
CPU time 59.76 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:30:30 PM PDT 24
Peak memory 200696 kb
Host smart-7ff493b1-e10b-41d5-aefd-ab80f7785ced
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178824873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1178824873
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3832757531
Short name T345
Test name
Test status
Simulation time 6873926639 ps
CPU time 34.02 seconds
Started Aug 18 06:29:31 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 200816 kb
Host smart-e4e8fd72-7fae-4c5b-84fd-fed9ceaec439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832757531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3832757531
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3561294596
Short name T364
Test name
Test status
Simulation time 3911500781 ps
CPU time 707.58 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:41:18 PM PDT 24
Peak memory 723196 kb
Host smart-2275f889-4e03-4458-b662-a358764b3bb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561294596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3561294596
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2842576795
Short name T175
Test name
Test status
Simulation time 6033975951 ps
CPU time 55.41 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:30:28 PM PDT 24
Peak memory 200816 kb
Host smart-a5485c0a-2b9a-416a-8838-b722da1a7624
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842576795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2842576795
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2419150361
Short name T439
Test name
Test status
Simulation time 35579018394 ps
CPU time 119.64 seconds
Started Aug 18 06:29:24 PM PDT 24
Finished Aug 18 06:31:24 PM PDT 24
Peak memory 200768 kb
Host smart-ec0504aa-3053-4292-8c5d-b91afa5e7384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419150361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2419150361
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2322583783
Short name T386
Test name
Test status
Simulation time 2337946044 ps
CPU time 9.98 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 200772 kb
Host smart-d5018306-56c1-4001-a048-4bf5b4e0fd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322583783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2322583783
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1660657227
Short name T249
Test name
Test status
Simulation time 94075535236 ps
CPU time 3137.65 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 07:21:48 PM PDT 24
Peak memory 680108 kb
Host smart-1db437d6-ad24-44c6-aa06-5fb5341edae8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660657227 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1660657227
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2167405440
Short name T342
Test name
Test status
Simulation time 10818142067 ps
CPU time 124.11 seconds
Started Aug 18 06:29:28 PM PDT 24
Finished Aug 18 06:31:32 PM PDT 24
Peak memory 200776 kb
Host smart-b899d7df-1033-418d-a692-3b2e32d59c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167405440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2167405440
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3529932503
Short name T210
Test name
Test status
Simulation time 12259700 ps
CPU time 0.59 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 196760 kb
Host smart-e8178978-608a-42d1-9896-47804639931e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529932503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3529932503
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3082246370
Short name T374
Test name
Test status
Simulation time 1418467783 ps
CPU time 78.94 seconds
Started Aug 18 06:29:26 PM PDT 24
Finished Aug 18 06:30:45 PM PDT 24
Peak memory 200724 kb
Host smart-c9e81e0a-97b7-44d7-b088-5af254cd9dd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3082246370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3082246370
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3041575495
Short name T137
Test name
Test status
Simulation time 1202470203 ps
CPU time 31.82 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:30:01 PM PDT 24
Peak memory 200692 kb
Host smart-2fcd08fd-2994-46d2-bba3-0f45adfd47c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041575495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3041575495
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3221209964
Short name T192
Test name
Test status
Simulation time 20631819289 ps
CPU time 976.62 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:45:50 PM PDT 24
Peak memory 751328 kb
Host smart-88556dc1-b6b6-467f-b0e0-c18685da7a4b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3221209964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3221209964
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.4189265148
Short name T23
Test name
Test status
Simulation time 18394279164 ps
CPU time 135.74 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:31:51 PM PDT 24
Peak memory 200756 kb
Host smart-b16ab960-2c17-4d84-bbd6-3f16c9186b1f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189265148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.4189265148
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1847163517
Short name T284
Test name
Test status
Simulation time 1072916926 ps
CPU time 62.1 seconds
Started Aug 18 06:29:29 PM PDT 24
Finished Aug 18 06:30:31 PM PDT 24
Peak memory 200620 kb
Host smart-183b4f33-7874-482e-b192-525f60f4fa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847163517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1847163517
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2210664331
Short name T335
Test name
Test status
Simulation time 1449073147 ps
CPU time 12.51 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 06:29:42 PM PDT 24
Peak memory 200636 kb
Host smart-ec052cbb-7264-401d-ba14-fecc53cf6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210664331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2210664331
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.404736855
Short name T296
Test name
Test status
Simulation time 805869556 ps
CPU time 4.5 seconds
Started Aug 18 06:29:39 PM PDT 24
Finished Aug 18 06:29:44 PM PDT 24
Peak memory 200680 kb
Host smart-f9fa7745-a32e-4501-9f92-a1f413aa2e50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404736855 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.404736855
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.856602319
Short name T438
Test name
Test status
Simulation time 2466585636 ps
CPU time 54.26 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:30:28 PM PDT 24
Peak memory 200716 kb
Host smart-029433a3-90a9-4b34-8331-cf58b8d98289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856602319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.856602319
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.418016236
Short name T173
Test name
Test status
Simulation time 35269694 ps
CPU time 0.58 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:29:36 PM PDT 24
Peak memory 196764 kb
Host smart-0aeb92dc-eee2-4734-a9ce-ed98e7ab8f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418016236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.418016236
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.332473111
Short name T507
Test name
Test status
Simulation time 3469472254 ps
CPU time 43.17 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:30:15 PM PDT 24
Peak memory 200744 kb
Host smart-5a34e7ba-6828-45d7-8eb5-f61066efb026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332473111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.332473111
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.273544262
Short name T469
Test name
Test status
Simulation time 218692888 ps
CPU time 3.27 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:29:35 PM PDT 24
Peak memory 200628 kb
Host smart-2d60b88e-810b-45cd-b202-e7db996c4538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273544262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.273544262
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1668975390
Short name T343
Test name
Test status
Simulation time 2208953950 ps
CPU time 427.19 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:36:43 PM PDT 24
Peak memory 689048 kb
Host smart-b10e0c7b-b180-4e81-b27a-7f1d6ff61ff3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1668975390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1668975390
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2016753610
Short name T71
Test name
Test status
Simulation time 3936692872 ps
CPU time 223.42 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:33:21 PM PDT 24
Peak memory 200800 kb
Host smart-41abd643-6e55-481f-9e5f-29108c0cced2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016753610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2016753610
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.301962309
Short name T292
Test name
Test status
Simulation time 30835269899 ps
CPU time 99.31 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:31:14 PM PDT 24
Peak memory 200712 kb
Host smart-bb009dcd-7f9f-4ec8-94e7-8fe5f6e7bc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301962309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.301962309
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4029355912
Short name T451
Test name
Test status
Simulation time 4073047137 ps
CPU time 7.04 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:29:40 PM PDT 24
Peak memory 200708 kb
Host smart-08389dfe-4d6a-4940-b730-7317b9bf2d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029355912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4029355912
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.4045147760
Short name T323
Test name
Test status
Simulation time 134403685503 ps
CPU time 2248.91 seconds
Started Aug 18 06:29:30 PM PDT 24
Finished Aug 18 07:07:00 PM PDT 24
Peak memory 758516 kb
Host smart-feb89894-0bad-4242-aa13-339d2f3ec00a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045147760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.4045147760
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2957144903
Short name T234
Test name
Test status
Simulation time 1095109998 ps
CPU time 4.8 seconds
Started Aug 18 06:29:36 PM PDT 24
Finished Aug 18 06:29:41 PM PDT 24
Peak memory 200620 kb
Host smart-54fc6c34-62fe-425f-b570-656007689748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957144903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2957144903
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.217672681
Short name T288
Test name
Test status
Simulation time 15060450 ps
CPU time 0.62 seconds
Started Aug 18 06:29:37 PM PDT 24
Finished Aug 18 06:29:38 PM PDT 24
Peak memory 196756 kb
Host smart-82f96671-53c1-47b6-b911-27c3b1dc9ed6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217672681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.217672681
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3980920895
Short name T157
Test name
Test status
Simulation time 891382764 ps
CPU time 12.33 seconds
Started Aug 18 06:29:37 PM PDT 24
Finished Aug 18 06:29:49 PM PDT 24
Peak memory 200620 kb
Host smart-451c8bfe-a362-4459-bba7-44efc6be74a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3980920895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3980920895
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.789658159
Short name T340
Test name
Test status
Simulation time 2874579829 ps
CPU time 41.11 seconds
Started Aug 18 06:29:36 PM PDT 24
Finished Aug 18 06:30:17 PM PDT 24
Peak memory 200756 kb
Host smart-f7fa2419-1551-41f7-920b-2ed6a70f330c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789658159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.789658159
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3509778673
Short name T418
Test name
Test status
Simulation time 28123453987 ps
CPU time 1563.11 seconds
Started Aug 18 06:29:36 PM PDT 24
Finished Aug 18 06:55:40 PM PDT 24
Peak memory 790424 kb
Host smart-3ddf6645-9741-4726-a2d0-c1213acef1cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509778673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3509778673
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2743129073
Short name T163
Test name
Test status
Simulation time 51313919230 ps
CPU time 186.29 seconds
Started Aug 18 06:29:33 PM PDT 24
Finished Aug 18 06:32:39 PM PDT 24
Peak memory 200752 kb
Host smart-5abc607c-cc97-4b40-82fd-35904f1c4415
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743129073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2743129073
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1382545463
Short name T290
Test name
Test status
Simulation time 1331168772 ps
CPU time 78.55 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:30:53 PM PDT 24
Peak memory 200692 kb
Host smart-a6c9de1c-7fae-4418-9e9e-484be190e262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382545463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1382545463
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.352168493
Short name T246
Test name
Test status
Simulation time 232716824 ps
CPU time 3.88 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 200688 kb
Host smart-4657d938-331c-4453-b840-5ea0a99b2530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352168493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.352168493
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.408079483
Short name T475
Test name
Test status
Simulation time 35040251716 ps
CPU time 491.16 seconds
Started Aug 18 06:29:35 PM PDT 24
Finished Aug 18 06:37:46 PM PDT 24
Peak memory 199272 kb
Host smart-d63058f5-8064-4190-9711-5f189f99a860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408079483 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.408079483
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2871656978
Short name T405
Test name
Test status
Simulation time 13483990855 ps
CPU time 118.9 seconds
Started Aug 18 06:29:32 PM PDT 24
Finished Aug 18 06:31:31 PM PDT 24
Peak memory 200784 kb
Host smart-66c24aab-2588-4211-9886-ffe4c03c1a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871656978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2871656978
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3366866129
Short name T47
Test name
Test status
Simulation time 46650703 ps
CPU time 0.61 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 196760 kb
Host smart-7519182a-f6af-4b3b-adf0-03f71fe0058c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366866129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3366866129
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4236566310
Short name T356
Test name
Test status
Simulation time 305701556 ps
CPU time 16.88 seconds
Started Aug 18 06:29:40 PM PDT 24
Finished Aug 18 06:29:57 PM PDT 24
Peak memory 200660 kb
Host smart-3b4c1a3b-3e5a-4acb-8163-0d0d6c9f1766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4236566310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4236566310
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3450847153
Short name T411
Test name
Test status
Simulation time 3083108550 ps
CPU time 20.69 seconds
Started Aug 18 06:29:43 PM PDT 24
Finished Aug 18 06:30:04 PM PDT 24
Peak memory 200740 kb
Host smart-150dc5b4-d2db-437f-a9db-64af40d8ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450847153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3450847153
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1192984878
Short name T455
Test name
Test status
Simulation time 17761989391 ps
CPU time 1166.25 seconds
Started Aug 18 06:29:43 PM PDT 24
Finished Aug 18 06:49:10 PM PDT 24
Peak memory 790028 kb
Host smart-5269a32e-4688-453b-bfd6-cac7374630f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192984878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1192984878
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3212578560
Short name T2
Test name
Test status
Simulation time 6175859691 ps
CPU time 165.05 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:32:23 PM PDT 24
Peak memory 200620 kb
Host smart-babc0315-3e99-483e-80b4-78a811532b2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212578560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3212578560
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2393441081
Short name T444
Test name
Test status
Simulation time 8831242660 ps
CPU time 105.89 seconds
Started Aug 18 06:29:39 PM PDT 24
Finished Aug 18 06:31:25 PM PDT 24
Peak memory 200708 kb
Host smart-432b5034-9a8d-4ad1-bd53-3e6521571303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393441081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2393441081
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3872626441
Short name T15
Test name
Test status
Simulation time 132099337 ps
CPU time 6.08 seconds
Started Aug 18 06:29:41 PM PDT 24
Finished Aug 18 06:29:47 PM PDT 24
Peak memory 200668 kb
Host smart-73bd6080-5d8a-48ab-b86a-e859150ab77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872626441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3872626441
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3986426435
Short name T283
Test name
Test status
Simulation time 1371790638 ps
CPU time 18.32 seconds
Started Aug 18 06:29:42 PM PDT 24
Finished Aug 18 06:30:01 PM PDT 24
Peak memory 200708 kb
Host smart-a184584a-33e9-4156-b2d5-aa9e19012bf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986426435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3986426435
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.4246317359
Short name T338
Test name
Test status
Simulation time 2029642121 ps
CPU time 50.77 seconds
Started Aug 18 06:29:39 PM PDT 24
Finished Aug 18 06:30:30 PM PDT 24
Peak memory 200716 kb
Host smart-9715da94-5975-41e2-b27b-ae1e097b8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246317359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.4246317359
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1096397429
Short name T399
Test name
Test status
Simulation time 63579229 ps
CPU time 0.62 seconds
Started Aug 18 06:29:45 PM PDT 24
Finished Aug 18 06:29:45 PM PDT 24
Peak memory 195324 kb
Host smart-24222e9e-0a9d-4f2f-8f88-f1ac0729940e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096397429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1096397429
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2988013387
Short name T26
Test name
Test status
Simulation time 503594706 ps
CPU time 27.57 seconds
Started Aug 18 06:29:38 PM PDT 24
Finished Aug 18 06:30:06 PM PDT 24
Peak memory 200652 kb
Host smart-75748db9-0160-4119-928e-d66e12168931
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2988013387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2988013387
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1771478127
Short name T257
Test name
Test status
Simulation time 7108762171 ps
CPU time 51.06 seconds
Started Aug 18 06:29:44 PM PDT 24
Finished Aug 18 06:30:35 PM PDT 24
Peak memory 200676 kb
Host smart-82c8e8ce-385f-4ad1-9cc2-eb81a7566ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771478127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1771478127
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4127380365
Short name T458
Test name
Test status
Simulation time 5017310738 ps
CPU time 546.81 seconds
Started Aug 18 06:29:39 PM PDT 24
Finished Aug 18 06:38:46 PM PDT 24
Peak memory 690108 kb
Host smart-b0b65d8e-6a15-4a02-b834-22c35742d94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4127380365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4127380365
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4272731630
Short name T465
Test name
Test status
Simulation time 2332969717 ps
CPU time 32.11 seconds
Started Aug 18 06:29:46 PM PDT 24
Finished Aug 18 06:30:18 PM PDT 24
Peak memory 200636 kb
Host smart-ef5fd43c-465b-42b7-b306-5dda5bcd467c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272731630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4272731630
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2357450770
Short name T300
Test name
Test status
Simulation time 7288075140 ps
CPU time 131.91 seconds
Started Aug 18 06:29:40 PM PDT 24
Finished Aug 18 06:31:52 PM PDT 24
Peak memory 208896 kb
Host smart-08598c2d-e110-44c0-8c7d-839cdedc8bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357450770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2357450770
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4285685594
Short name T191
Test name
Test status
Simulation time 280534450 ps
CPU time 13.2 seconds
Started Aug 18 06:29:47 PM PDT 24
Finished Aug 18 06:30:00 PM PDT 24
Peak memory 200712 kb
Host smart-60ad3c12-c806-4587-ba69-02c031e500f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285685594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4285685594
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3698664
Short name T231
Test name
Test status
Simulation time 164647522262 ps
CPU time 999.84 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:46:44 PM PDT 24
Peak memory 664452 kb
Host smart-bec9c262-c57b-4950-a5b9-cdb746728c91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698664 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3698664
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1693894080
Short name T468
Test name
Test status
Simulation time 896897196 ps
CPU time 44.32 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:30:49 PM PDT 24
Peak memory 200620 kb
Host smart-3bbb0eb0-da7a-42f3-89a1-70ca3553384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693894080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1693894080
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3192824848
Short name T240
Test name
Test status
Simulation time 32226183 ps
CPU time 0.58 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 196396 kb
Host smart-b7df1793-d634-45dc-ab67-02aad686971b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192824848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3192824848
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2650759757
Short name T471
Test name
Test status
Simulation time 3459214632 ps
CPU time 53.98 seconds
Started Aug 18 06:29:47 PM PDT 24
Finished Aug 18 06:30:41 PM PDT 24
Peak memory 200724 kb
Host smart-4baba20b-cd3b-4ed6-9cce-44d82cf0690b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2650759757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2650759757
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1278867388
Short name T412
Test name
Test status
Simulation time 88900237 ps
CPU time 2.72 seconds
Started Aug 18 06:29:47 PM PDT 24
Finished Aug 18 06:29:50 PM PDT 24
Peak memory 200632 kb
Host smart-fec0cf72-993a-4c59-bf94-78bf80da6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278867388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1278867388
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2553564905
Short name T496
Test name
Test status
Simulation time 4097913184 ps
CPU time 775.75 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:43:00 PM PDT 24
Peak memory 708764 kb
Host smart-f33e398e-192a-4657-beb9-5fb3413e4778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553564905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2553564905
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1610262712
Short name T462
Test name
Test status
Simulation time 45107061849 ps
CPU time 215.01 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:33:40 PM PDT 24
Peak memory 200772 kb
Host smart-4ad3a354-5514-485b-b6eb-abfa4b0302df
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610262712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1610262712
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.284024787
Short name T274
Test name
Test status
Simulation time 3312867628 ps
CPU time 49.38 seconds
Started Aug 18 06:29:47 PM PDT 24
Finished Aug 18 06:30:37 PM PDT 24
Peak memory 200684 kb
Host smart-c2f6dd32-f6ab-464b-99d2-ea65d923bbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284024787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.284024787
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.106380107
Short name T397
Test name
Test status
Simulation time 1316686923 ps
CPU time 14.81 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:30:19 PM PDT 24
Peak memory 200704 kb
Host smart-05c4069e-e1f1-4d4e-8fa0-bbd9c30cf12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106380107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.106380107
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.651043030
Short name T6
Test name
Test status
Simulation time 75877800498 ps
CPU time 1447.2 seconds
Started Aug 18 06:29:45 PM PDT 24
Finished Aug 18 06:53:53 PM PDT 24
Peak memory 200832 kb
Host smart-36d28b37-3336-4752-af64-8e48a8cad0d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651043030 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.651043030
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1917356380
Short name T370
Test name
Test status
Simulation time 21516609939 ps
CPU time 92.72 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:31:37 PM PDT 24
Peak memory 200784 kb
Host smart-4f5f81cb-2809-4269-b727-d08f18ae6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917356380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1917356380
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.783328720
Short name T211
Test name
Test status
Simulation time 15550755 ps
CPU time 0.64 seconds
Started Aug 18 06:30:05 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 196740 kb
Host smart-3b74edcd-f645-4f6e-8627-885115bea69d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783328720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.783328720
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2996679732
Short name T506
Test name
Test status
Simulation time 1569023423 ps
CPU time 83.94 seconds
Started Aug 18 06:29:47 PM PDT 24
Finished Aug 18 06:31:11 PM PDT 24
Peak memory 200648 kb
Host smart-12b35d70-23b9-4600-9d0a-0e083eb30742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2996679732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2996679732
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.287145718
Short name T306
Test name
Test status
Simulation time 2897695909 ps
CPU time 54.06 seconds
Started Aug 18 06:29:46 PM PDT 24
Finished Aug 18 06:30:40 PM PDT 24
Peak memory 200800 kb
Host smart-3031535e-bfd1-41b0-8f68-142110e44d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287145718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.287145718
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.16768566
Short name T161
Test name
Test status
Simulation time 24380777 ps
CPU time 0.71 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 06:30:05 PM PDT 24
Peak memory 198864 kb
Host smart-89d77563-9619-412f-85b6-30db861a7704
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16768566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.16768566
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1919240040
Short name T378
Test name
Test status
Simulation time 14270265633 ps
CPU time 178.35 seconds
Started Aug 18 06:29:48 PM PDT 24
Finished Aug 18 06:32:47 PM PDT 24
Peak memory 200732 kb
Host smart-b160bdaa-d6ec-412f-8f73-e0882ecb991b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919240040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1919240040
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2129019516
Short name T446
Test name
Test status
Simulation time 1842923361 ps
CPU time 99.21 seconds
Started Aug 18 06:29:48 PM PDT 24
Finished Aug 18 06:31:27 PM PDT 24
Peak memory 200756 kb
Host smart-6f54feda-f35e-4c20-9aef-8bf7a6345bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129019516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2129019516
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1804969393
Short name T146
Test name
Test status
Simulation time 389132840 ps
CPU time 6.17 seconds
Started Aug 18 06:29:45 PM PDT 24
Finished Aug 18 06:29:51 PM PDT 24
Peak memory 200760 kb
Host smart-d669d5fe-a423-4509-80a6-e3ceaab7b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804969393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1804969393
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1545865121
Short name T139
Test name
Test status
Simulation time 13006580494 ps
CPU time 1831.61 seconds
Started Aug 18 06:30:04 PM PDT 24
Finished Aug 18 07:00:37 PM PDT 24
Peak memory 751908 kb
Host smart-b91efd89-c74c-442f-8cca-01344a73c271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545865121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1545865121
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.797927434
Short name T241
Test name
Test status
Simulation time 8111888314 ps
CPU time 22.78 seconds
Started Aug 18 06:29:45 PM PDT 24
Finished Aug 18 06:30:08 PM PDT 24
Peak memory 200752 kb
Host smart-1d22ee51-4d98-42cb-95a7-0548e6895fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797927434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.797927434
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.141496760
Short name T360
Test name
Test status
Simulation time 15073091 ps
CPU time 0.6 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:28:42 PM PDT 24
Peak memory 195580 kb
Host smart-e6e71b87-be48-4876-bddf-eddd6f03f4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141496760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.141496760
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.772882149
Short name T391
Test name
Test status
Simulation time 5003736877 ps
CPU time 62.86 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:29:39 PM PDT 24
Peak memory 208976 kb
Host smart-cf919296-acf4-4df2-8307-6737f051544f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772882149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.772882149
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1454069901
Short name T434
Test name
Test status
Simulation time 11970519212 ps
CPU time 37.28 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:29:20 PM PDT 24
Peak memory 208920 kb
Host smart-6c771518-c7ff-445d-a72d-4f68a2260a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454069901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1454069901
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.4104139736
Short name T164
Test name
Test status
Simulation time 51305688506 ps
CPU time 737.89 seconds
Started Aug 18 06:28:38 PM PDT 24
Finished Aug 18 06:40:56 PM PDT 24
Peak memory 690352 kb
Host smart-5abdcae4-9092-453b-8261-8f2d33eadc92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4104139736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.4104139736
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2355216405
Short name T272
Test name
Test status
Simulation time 2976254945 ps
CPU time 167.3 seconds
Started Aug 18 06:28:40 PM PDT 24
Finished Aug 18 06:31:27 PM PDT 24
Peak memory 200804 kb
Host smart-d9afd9f8-23e0-4622-be7e-8c364b855955
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355216405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2355216405
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.684901210
Short name T362
Test name
Test status
Simulation time 394396551 ps
CPU time 16.4 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:28:57 PM PDT 24
Peak memory 200644 kb
Host smart-0740adc7-64eb-489b-a962-f342a30d28b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684901210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.684901210
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.515575972
Short name T273
Test name
Test status
Simulation time 53476886 ps
CPU time 2.74 seconds
Started Aug 18 06:28:30 PM PDT 24
Finished Aug 18 06:28:33 PM PDT 24
Peak memory 200568 kb
Host smart-b276aa1a-7f29-4a2c-b851-bbe2bf041104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515575972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.515575972
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2160855441
Short name T168
Test name
Test status
Simulation time 2909132260 ps
CPU time 50.64 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:29:32 PM PDT 24
Peak memory 200716 kb
Host smart-5d13722b-7ba8-4001-9919-be5382b62204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160855441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2160855441
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3010739115
Short name T37
Test name
Test status
Simulation time 27722777 ps
CPU time 0.58 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:28:43 PM PDT 24
Peak memory 196728 kb
Host smart-22b96f28-9b7d-4b61-a987-ba02ead57b9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010739115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3010739115
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.309027034
Short name T526
Test name
Test status
Simulation time 4308161968 ps
CPU time 96.92 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:30:20 PM PDT 24
Peak memory 200776 kb
Host smart-1028da91-05bb-42f2-87e2-e135337d77c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309027034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.309027034
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3197881321
Short name T53
Test name
Test status
Simulation time 2775058238 ps
CPU time 47.6 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:29:25 PM PDT 24
Peak memory 200696 kb
Host smart-7f43bec6-76bc-491f-9cf0-4fb7f5a830dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197881321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3197881321
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3388494846
Short name T159
Test name
Test status
Simulation time 4566167356 ps
CPU time 962.95 seconds
Started Aug 18 06:29:02 PM PDT 24
Finished Aug 18 06:45:05 PM PDT 24
Peak memory 762296 kb
Host smart-80737844-9e8b-4cf5-96f0-373d3e7e31e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388494846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3388494846
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1519535682
Short name T407
Test name
Test status
Simulation time 2183167736 ps
CPU time 122.24 seconds
Started Aug 18 06:28:29 PM PDT 24
Finished Aug 18 06:30:32 PM PDT 24
Peak memory 200708 kb
Host smart-b71aff05-9238-40d3-bda6-28733dc55c02
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519535682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1519535682
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2043201361
Short name T166
Test name
Test status
Simulation time 121087009905 ps
CPU time 136.42 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:30:54 PM PDT 24
Peak memory 200768 kb
Host smart-7e405df0-5675-447d-99ce-97b9790c86db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043201361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2043201361
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.762469109
Short name T466
Test name
Test status
Simulation time 844500534 ps
CPU time 14.57 seconds
Started Aug 18 06:28:45 PM PDT 24
Finished Aug 18 06:28:59 PM PDT 24
Peak memory 200676 kb
Host smart-dccb2cff-7cef-42e1-b9c6-084685e14a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762469109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.762469109
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3554525960
Short name T64
Test name
Test status
Simulation time 1404336412152 ps
CPU time 3679.07 seconds
Started Aug 18 06:28:35 PM PDT 24
Finished Aug 18 07:29:56 PM PDT 24
Peak memory 790004 kb
Host smart-39cf4d83-476e-4e98-888f-01db33a7491c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554525960 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3554525960
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3988415085
Short name T112
Test name
Test status
Simulation time 1634609331 ps
CPU time 68.25 seconds
Started Aug 18 06:28:37 PM PDT 24
Finished Aug 18 06:29:45 PM PDT 24
Peak memory 200648 kb
Host smart-9d8ffade-5f55-49e8-b096-ef297650c3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988415085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3988415085
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2496951799
Short name T457
Test name
Test status
Simulation time 52428690 ps
CPU time 0.59 seconds
Started Aug 18 06:29:01 PM PDT 24
Finished Aug 18 06:29:02 PM PDT 24
Peak memory 196656 kb
Host smart-5b1665b1-3d95-4a50-811b-daef713fef29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496951799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2496951799
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.424099349
Short name T223
Test name
Test status
Simulation time 1001593690 ps
CPU time 13.91 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:28:55 PM PDT 24
Peak memory 200612 kb
Host smart-70710ebc-3e72-4e3a-8958-9b260f83d1dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=424099349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.424099349
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.720433475
Short name T341
Test name
Test status
Simulation time 14076570022 ps
CPU time 44.84 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:29:28 PM PDT 24
Peak memory 200692 kb
Host smart-957c42e1-3533-4fe1-9416-dbbef8f3863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720433475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.720433475
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.632137191
Short name T369
Test name
Test status
Simulation time 666738444 ps
CPU time 114.59 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:30:31 PM PDT 24
Peak memory 469044 kb
Host smart-97628a01-a9c9-497b-b197-af934b329185
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632137191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.632137191
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.174962728
Short name T70
Test name
Test status
Simulation time 3768160352 ps
CPU time 34.24 seconds
Started Aug 18 06:29:01 PM PDT 24
Finished Aug 18 06:29:36 PM PDT 24
Peak memory 200704 kb
Host smart-95a05647-3a97-42a7-b612-1c164eca3b5c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174962728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.174962728
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1264901467
Short name T144
Test name
Test status
Simulation time 11581910727 ps
CPU time 213.15 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:32:33 PM PDT 24
Peak memory 200760 kb
Host smart-040745c4-2f68-4cc4-ad70-47e10355b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264901467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1264901467
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1097160035
Short name T436
Test name
Test status
Simulation time 1847775504 ps
CPU time 8.67 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 06:28:56 PM PDT 24
Peak memory 200716 kb
Host smart-64bea447-5b16-4a44-bb90-87c762db63fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097160035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1097160035
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.693070622
Short name T78
Test name
Test status
Simulation time 187926253292 ps
CPU time 596.34 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:38:39 PM PDT 24
Peak memory 200904 kb
Host smart-fa85ca64-32cc-421b-84e0-efd0aefebf59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693070622 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.693070622
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2423210364
Short name T32
Test name
Test status
Simulation time 3137833497 ps
CPU time 35.35 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:29:16 PM PDT 24
Peak memory 200784 kb
Host smart-2bb13912-7498-47ab-a88d-0dd64ffad721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423210364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2423210364
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1268410694
Short name T385
Test name
Test status
Simulation time 96925573 ps
CPU time 0.59 seconds
Started Aug 18 06:28:46 PM PDT 24
Finished Aug 18 06:28:46 PM PDT 24
Peak memory 194984 kb
Host smart-43479804-efa5-43d7-9d2c-54d7b35287b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268410694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1268410694
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2609367134
Short name T5
Test name
Test status
Simulation time 8616072877 ps
CPU time 89.76 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:30:11 PM PDT 24
Peak memory 200884 kb
Host smart-fc297676-a38a-45d1-9b28-49ffe57490eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609367134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2609367134
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1576770936
Short name T253
Test name
Test status
Simulation time 3819210873 ps
CPU time 37.54 seconds
Started Aug 18 06:28:36 PM PDT 24
Finished Aug 18 06:29:14 PM PDT 24
Peak memory 200756 kb
Host smart-14d47acd-6a52-48b1-baae-0963845b0a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576770936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1576770936
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3861619334
Short name T404
Test name
Test status
Simulation time 7357111143 ps
CPU time 611.91 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:38:53 PM PDT 24
Peak memory 720232 kb
Host smart-69c1f459-f136-4ad7-a617-d686c793ee3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3861619334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3861619334
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1388221168
Short name T207
Test name
Test status
Simulation time 7355227268 ps
CPU time 105 seconds
Started Aug 18 06:28:48 PM PDT 24
Finished Aug 18 06:30:33 PM PDT 24
Peak memory 200700 kb
Host smart-233a7636-8a7c-4df4-9b87-f256d13ef186
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388221168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1388221168
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3663511132
Short name T321
Test name
Test status
Simulation time 3551251353 ps
CPU time 192.92 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:31:56 PM PDT 24
Peak memory 200824 kb
Host smart-f99e2259-acb4-4075-b5d2-48a39b740a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663511132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3663511132
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.386448139
Short name T353
Test name
Test status
Simulation time 24114150 ps
CPU time 1.14 seconds
Started Aug 18 06:28:51 PM PDT 24
Finished Aug 18 06:28:53 PM PDT 24
Peak memory 200696 kb
Host smart-db342197-27c3-4d16-9f4e-3156a1969b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386448139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.386448139
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1381707856
Short name T87
Test name
Test status
Simulation time 10793234819 ps
CPU time 287.69 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:33:31 PM PDT 24
Peak memory 200748 kb
Host smart-77cf0992-dbda-42db-bd06-1705e489a74d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381707856 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1381707856
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1334205619
Short name T449
Test name
Test status
Simulation time 4342277904 ps
CPU time 63.03 seconds
Started Aug 18 06:28:41 PM PDT 24
Finished Aug 18 06:29:44 PM PDT 24
Peak memory 200688 kb
Host smart-d85f4a89-27dc-4623-a469-94eb457dedac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334205619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1334205619
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1166880238
Short name T377
Test name
Test status
Simulation time 12646672 ps
CPU time 0.59 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:28:42 PM PDT 24
Peak memory 196384 kb
Host smart-a8d85ae7-68d6-4214-b1ac-2c65055193d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166880238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1166880238
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2463507686
Short name T413
Test name
Test status
Simulation time 916410222 ps
CPU time 12.64 seconds
Started Aug 18 06:28:57 PM PDT 24
Finished Aug 18 06:29:09 PM PDT 24
Peak memory 200640 kb
Host smart-13a286ee-d3d7-451d-a545-5587abe29124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463507686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2463507686
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3249078531
Short name T366
Test name
Test status
Simulation time 1055812518 ps
CPU time 40.01 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:29:23 PM PDT 24
Peak memory 200628 kb
Host smart-36b2986d-9b7a-479c-ad6a-05b514937529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249078531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3249078531
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.262621284
Short name T424
Test name
Test status
Simulation time 5735213404 ps
CPU time 909.43 seconds
Started Aug 18 06:28:49 PM PDT 24
Finished Aug 18 06:43:59 PM PDT 24
Peak memory 759792 kb
Host smart-fdc77fab-c4b6-426d-8775-307665b96131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262621284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.262621284
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.743000146
Short name T485
Test name
Test status
Simulation time 5137419678 ps
CPU time 67.95 seconds
Started Aug 18 06:29:00 PM PDT 24
Finished Aug 18 06:30:08 PM PDT 24
Peak memory 200724 kb
Host smart-5eb3449e-44ec-4e3e-b05b-ed72ebb4619b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743000146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.743000146
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.178595222
Short name T355
Test name
Test status
Simulation time 36947713334 ps
CPU time 163.7 seconds
Started Aug 18 06:29:08 PM PDT 24
Finished Aug 18 06:31:52 PM PDT 24
Peak memory 200776 kb
Host smart-b31628c7-7c15-4d3b-b625-9983aca021f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178595222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.178595222
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2124465515
Short name T129
Test name
Test status
Simulation time 2585467995 ps
CPU time 11.41 seconds
Started Aug 18 06:28:43 PM PDT 24
Finished Aug 18 06:28:55 PM PDT 24
Peak memory 200780 kb
Host smart-417f55ac-4d6f-4f58-99d0-bbe76a130051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124465515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2124465515
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.463353231
Short name T400
Test name
Test status
Simulation time 406793083870 ps
CPU time 2766.28 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 07:14:55 PM PDT 24
Peak memory 772464 kb
Host smart-31fdd34c-3c3d-42fd-b138-7ee826f9646e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463353231 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.463353231
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.934426572
Short name T60
Test name
Test status
Simulation time 10431405899 ps
CPU time 570.99 seconds
Started Aug 18 06:28:47 PM PDT 24
Finished Aug 18 06:38:18 PM PDT 24
Peak memory 691488 kb
Host smart-a6c2d460-81c8-4ce4-9f87-908ca31e5a8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=934426572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.934426572
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.645351497
Short name T248
Test name
Test status
Simulation time 5492931611 ps
CPU time 77.24 seconds
Started Aug 18 06:28:42 PM PDT 24
Finished Aug 18 06:30:00 PM PDT 24
Peak memory 200724 kb
Host smart-cf6624a2-a8c7-46ca-87d5-4ac829acc8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645351497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.645351497
Directory /workspace/9.hmac_wipe_secret/latest
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