Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16947147	1			T1	696		T4	2624		T5	1827
all_values[1]	16947147	1			T1	696		T4	2624		T5	1827
all_values[2]	16947147	1			T1	696		T4	2624		T5	1827

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253099

1

T1

343

T4

47

T6

73

auto[1]

50588342

1

T1

1745

T4

7825

T5

5481

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43443533

1

T1

1539

T4

7195

T5

4821

auto[1]

7397908

1

T1

549

T4

677

T5

660

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	72991	1			T26	38		T11	572		T15	1
all_values[0]	auto[0]	auto[1]	313	1			T11	3		T75	2		T19	1
all_values[0]	auto[1]	auto[0]	16854990	1			T1	695		T4	2587		T5	1804
all_values[0]	auto[1]	auto[1]	18853	1			T1	1		T4	37		T5	23
all_values[1]	auto[0]	auto[0]	82386	1			T4	47		T6	73		T8	496
all_values[1]	auto[0]	auto[1]	194	1			T27	3		T75	2		T19	3
all_values[1]	auto[1]	auto[0]	16864254	1			T1	696		T4	2577		T5	1827
all_values[1]	auto[1]	auto[1]	313	1			T26	4		T27	3		T60	6
all_values[2]	auto[0]	auto[0]	60119	1			T1	1		T12	15		T29	1
all_values[2]	auto[0]	auto[1]	37096	1			T1	342		T12	32		T29	1
all_values[2]	auto[1]	auto[0]	9508793	1			T1	147		T4	1984		T5	1190
all_values[2]	auto[1]	auto[1]	7341139	1			T1	206		T4	640		T5	637