Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117567

1

T4

40

T5

34

T6

532

auto[1]

114208

1

T1

2

T4

52

T5

30

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	86609	1			T1	1		T4	2		T6	500
len_1026_2046	6396	1			T4	3		T5	1		T6	12
len_514_1022	3400	1			T4	1		T6	8		T12	6
len_2_510	4073	1			T4	10		T5	3		T6	3
len_2056	154	1			T4	1		T5	3		T12	4
len_2048	476	1			T4	6		T26	2		T27	1
len_2040	143	1			T4	3		T5	6		T12	2
len_1032	164	1			T4	2		T5	1		T12	6
len_1024	1736	1			T4	4		T5	4		T7	1
len_1016	165	1			T4	1		T5	3		T160	4
len_520	201	1			T4	3		T12	1		T17	1
len_512	373	1			T4	3		T5	2		T12	3
len_504	1428	1			T4	1		T5	1		T12	5
len_8	1122	1			T75	4		T46	6		T19	7
len_0	9447	1			T4	6		T5	8		T6	37

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

130

1

T4

2

T7

2

T8

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	45118	1			T4	2		T6	246		T9	4
auto[0]	len_1026_2046	2375	1			T6	11		T7	2		T12	1
auto[0]	len_514_1022	2123	1			T6	6		T12	4		T29	1
auto[0]	len_2_510	2726	1			T4	2		T5	2		T6	3
auto[0]	len_2056	89	1			T4	1		T5	2		T12	2
auto[0]	len_2048	223	1			T4	1		T26	2		T60	3
auto[0]	len_2040	83	1			T4	3		T5	3		T12	1
auto[0]	len_1032	96	1			T4	1		T5	1		T12	4
auto[0]	len_1024	211	1			T4	1		T5	3		T7	1
auto[0]	len_1016	78	1			T160	3		T98	1		T36	2
auto[0]	len_520	111	1			T4	3		T17	1		T161	2
auto[0]	len_512	196	1			T4	2		T5	2		T12	2
auto[0]	len_504	1354	1			T5	1		T12	5		T160	1
auto[0]	len_8	91	1			T162	1		T163	1		T164	1
auto[0]	len_0	3909	1			T4	4		T5	3		T12	6
auto[1]	len_2050_plus	41491	1			T1	1		T6	254		T9	3
auto[1]	len_1026_2046	4021	1			T4	3		T5	1		T6	1
auto[1]	len_514_1022	1277	1			T4	1		T6	2		T12	2
auto[1]	len_2_510	1347	1			T4	8		T5	1		T25	2
auto[1]	len_2056	65	1			T5	1		T12	2		T43	2
auto[1]	len_2048	253	1			T4	5		T27	1		T165	1
auto[1]	len_2040	60	1			T5	3		T12	1		T17	1
auto[1]	len_1032	68	1			T4	1		T12	2		T143	2
auto[1]	len_1024	1525	1			T4	3		T5	1		T30	69
auto[1]	len_1016	87	1			T4	1		T5	3		T160	1
auto[1]	len_520	90	1			T12	1		T160	2		T98	2
auto[1]	len_512	177	1			T4	1		T12	1		T26	1
auto[1]	len_504	74	1			T4	1		T166	1		T17	2
auto[1]	len_8	1031	1			T75	4		T46	6		T19	7
auto[1]	len_0	5538	1			T4	2		T5	5		T6	37

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

79

1

T4

2

T7

2

T8

2

auto[1]

len_upper

51

1

T99

2

T111

1

T39

1