Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4431316

1

T4

617

T5

414

T6

997

auto[1]

2578167

1

T1

3

T4

417

T5

478

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2597000

1

T1

3

T4

727

T5

395

auto[1]

4412483

1

T4

307

T5

497

T6

1078

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3173284

1

T1

1

T4

444

T5

355

auto[1]

3836199

1

T1

2

T4

590

T5

537

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4367027

1

T4

588

T5

613

T6

1637

auto[1]

2642456

1

T1

3

T4

446

T5

279

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6185510	1			T1	3		T4	873		T5	878
fifo_depth[1]	125120	1			T4	22		T5	9		T6	37
fifo_depth[2]	102458	1			T4	21		T5	4		T6	80
fifo_depth[3]	84134	1			T4	17		T5	1		T6	27
fifo_depth[4]	75640	1			T4	27		T6	64		T30	172
fifo_depth[5]	59540	1			T4	14		T6	25		T9	1
fifo_depth[6]	47396	1			T4	15		T6	33		T30	61
fifo_depth[7]	31337	1			T4	13		T6	13		T8	1

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

823973

1

T4

161

T5

14

T6

318

auto[1]

6185510

1

T1

3

T4

873

T5

878

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6994972

1

T1

3

T4

1034

T5

892

auto[1]

14511

1

T25

73

T26

231

T27

98

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

40007

1

T4

29

T7

1

T12

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31984

1

T4

6

T5

1

T26

333

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

34664

1

T6

70

T26

2432

T11

15

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35791

1

T6

51

T9

20

T25

1934

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

212850

1

T5

1

T6

25

T10

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

33530

1

T6

37

T7

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45628

1

T6

34

T9

20

T10

85

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31990

1

T6

59

T12

1

T10

82

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46301

1

T4

29

T5

1

T9

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

52249

1

T4

7

T25

904

T142

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39056

1

T4

13

T12

2

T59

152

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

40193

1

T4

23

T5

2

T25

1052

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

50946

1

T4

7

T5

3

T30

977

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

32517

1

T6

13

T9

20

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41190

1

T4

24

T5

6

T6

29

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

55077

1

T4

23

T12

2

T10

117

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

147347

1

T4

136

T5

60

T12

91

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

134133

1

T4

133

T5

46

T6

52

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

148210

1

T5

60

T6

178

T8

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

148476

1

T1

1

T4

73

T5

13

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1665340

1

T5

86

T6

67

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

163015

1

T4

2

T5

30

T6

80

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

148490

1

T4

12

T5

30

T6

107

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

151829

1

T4

53

T5

28

T6

150

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

428250

1

T4

136

T5

53

T6

605

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

442378

1

T4

29

T5

30

T7

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

423021

1

T4

75

T5

39

T6

91

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

404940

1

T1

2

T4

38

T5

90

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

505269

1

T4

92

T5

103

T6

85

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

445200

1

T4

11

T6

33

T9

346

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

390458

1

T4

35

T5

171

T6

346

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

439154

1

T4

48

T5

39

T6

13

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

185584

1

T4

165

T5

60

T7

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

165046

1

T4

139

T5

47

T6

52

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

182484

1

T5

60

T6

248

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

182614

1

T1

1

T4

73

T5

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1877714

1

T5

87

T6

92

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

195997

1

T4

2

T5

30

T6

117

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

192714

1

T4

12

T5

30

T6

141

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

182682

1

T4

53

T5

28

T6

209

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

474099

1

T4

165

T5

54

T6

605

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

493303

1

T4

36

T5

30

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

461828

1

T4

88

T5

39

T6

91

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

444559

1

T1

2

T4

61

T5

92

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

555412

1

T4

99

T5

106

T6

85

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

476807

1

T4

11

T6

46

T9

366

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

430753

1

T4

59

T5

177

T6

375

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

493376

1

T4

71

T5

39

T6

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1770

1

T25

64

T26

112

T14

34

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1071

1

T60

153

T14

1

T169

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

390

1

T26

1

T60

4

T169

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1653

1

T25

2

T14

7

T169

237

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

476

1

T39

24

T51

40

T170

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

548

1

T39

39

T169

6

T76

43

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1404

1

T26

68

T60

106

T14

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1137

1

T27

20

T60

8

T14

166

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

452

1

T14

34

T51

24

T171

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1324

1

T27

54

T51

158

T172

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

249

1

T60

1

T173

94

T170

25

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

574

1

T25

7

T39

3

T174

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

803

1

T14

78

T51

29

T174

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

910

1

T169

3

T173

82

T174

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

895

1

T27

24

T39

11

T51

219

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

855

1

T26

50

T60

6

T14

131

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

147347

1

T4

136

T5

60

T12

91

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

134133

1

T4

133

T5

46

T6

52

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

148210

1

T5

60

T6

178

T8

3

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

148476

1

T1

1

T4

73

T5

13

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1665340

1

T5

86

T6

67

T7

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

163015

1

T4

2

T5

30

T6

80

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

148490

1

T4

12

T5

30

T6

107

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

151829

1

T4

53

T5

28

T6

150

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

428250

1

T4

136

T5

53

T6

605

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

442378

1

T4

29

T5

30

T7

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

423021

1

T4

75

T5

39

T6

91

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

404940

1

T1

2

T4

38

T5

90

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

505269

1

T4

92

T5

103

T6

85

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

445200

1

T4

11

T6

33

T9

346

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

390458

1

T4

35

T5

171

T6

346

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

439154

1

T4

48

T5

39

T6

13

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

2913

1

T4

6

T12

1

T10

32

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

2663

1

T4

2

T5

1

T31

5

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3382

1

T6

9

T26

25

T11

11

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3242

1

T6

3

T9

11

T25

58

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

53242

1

T5

1

T6

2

T10

5

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3238

1

T6

1

T10

12

T31

15

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3067

1

T6

2

T9

10

T10

12

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3134

1

T6

12

T12

1

T10

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6586

1

T4

3

T5

1

T9

3

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6585

1

T25

19

T27

3

T11

5

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5944

1

T4

3

T12

1

T59

28

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

5947

1

T4

4

T5

1

T10

10

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7967

1

T5

1

T30

215

T62

194

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

5341

1

T6

4

T9

14

T12

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

5155

1

T4

2

T5

4

T6

4

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6714

1

T4

2

T12

2

T10

15

fifo_depth[2]

auto[0]

auto[0]

auto[0]

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