Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	16947147	1			T1	696		T4	2624		T5	1827
all_pins[1]	16947147	1			T1	696		T4	2624		T5	1827
all_pins[2]	16947147	1			T1	696		T4	2624		T5	1827

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	43480250	1			T1	1881		T4	7188		T5	4819
values[0x1]	7361191	1			T1	207		T4	684		T5	662
transitions[0x0=>0x1]	7361018	1			T1	207		T4	684		T5	662
transitions[0x1=>0x0]	7361035	1			T1	207		T4	684		T5	662

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	16927441	1			T1	695		T4	2580		T5	1802
all_pins[0]	values[0x1]	19706	1			T1	1		T4	44		T5	25
all_pins[0]	transitions[0x0=>0x1]	19627	1			T1	1		T4	44		T5	25
all_pins[0]	transitions[0x1=>0x0]	7341077	1			T1	206		T4	640		T5	637
all_pins[1]	values[0x0]	16946801	1			T1	696		T4	2624		T5	1827
all_pins[1]	values[0x1]	346	1			T26	4		T27	3		T60	6
all_pins[1]	transitions[0x0=>0x1]	298	1			T26	4		T27	3		T60	6
all_pins[1]	transitions[0x1=>0x0]	19658	1			T1	1		T4	44		T5	25
all_pins[2]	values[0x0]	9606008	1			T1	490		T4	1984		T5	1190
all_pins[2]	values[0x1]	7341139	1			T1	206		T4	640		T5	637
all_pins[2]	transitions[0x0=>0x1]	7341093	1			T1	206		T4	640		T5	637
all_pins[2]	transitions[0x1=>0x0]	300	1			T26	4		T27	3		T60	6