Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 854 1 T75 4 T19 10 T76 4
all_values[1] 854 1 T75 4 T19 10 T76 4
all_values[2] 854 1 T75 4 T19 10 T76 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1284 1 T75 9 T19 17 T76 4
auto[1] 1278 1 T75 3 T19 13 T76 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 853 1 T75 2 T19 13 T76 6
auto[1] 1709 1 T75 10 T19 17 T76 6


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1426 1 T75 6 T19 20 T76 9
auto[1] 1136 1 T75 6 T19 10 T76 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 145 1 T19 2 T77 1 T88 1
all_values[0] auto[0] auto[0] auto[1] 78 1 T75 1 T19 1 T18 1
all_values[0] auto[0] auto[1] auto[0] 161 1 T19 4 T76 1 T151 4
all_values[0] auto[0] auto[1] auto[1] 93 1 T75 1 T76 2 T18 1
all_values[0] auto[1] auto[0] auto[1] 174 1 T75 2 T18 1 T77 4
all_values[0] auto[1] auto[1] auto[1] 203 1 T19 3 T76 1 T18 1
all_values[1] auto[0] auto[0] auto[0] 128 1 T75 1 T19 1 T18 1
all_values[1] auto[0] auto[0] auto[1] 122 1 T75 1 T19 3 T76 1
all_values[1] auto[0] auto[1] auto[0] 126 1 T19 2 T76 2 T18 1
all_values[1] auto[0] auto[1] auto[1] 102 1 T18 1 T77 2 T151 1
all_values[1] auto[1] auto[0] auto[1] 194 1 T75 2 T19 2 T76 1
all_values[1] auto[1] auto[1] auto[1] 182 1 T19 2 T18 1 T77 3
all_values[2] auto[0] auto[0] auto[0] 153 1 T75 1 T19 3 T76 2
all_values[2] auto[0] auto[0] auto[1] 85 1 T19 2 T18 1 T77 2
all_values[2] auto[0] auto[1] auto[0] 140 1 T19 1 T76 1 T18 1
all_values[2] auto[0] auto[1] auto[1] 93 1 T75 1 T19 1 T77 2
all_values[2] auto[1] auto[0] auto[1] 205 1 T75 1 T19 3 T18 1
all_values[2] auto[1] auto[1] auto[1] 178 1 T75 1 T76 1 T77 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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