Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3860	1			T4	6		T5	8		T6	3
sha2_none	3946	1			T1	1		T4	12		T5	12
sha2_512	7266	1			T4	16		T5	10		T6	3
sha2_384	6981	1			T1	2		T4	10		T5	8
sha2_256	5864	1			T4	10		T5	5		T6	6

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17862

1

T4

34

T5

20

T6

10

auto[1]

10386

1

T1

3

T4

20

T5

24

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10455

1

T1

3

T4

35

T5

20

auto[1]

17793

1

T4

19

T5

24

T6

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14584

1

T1

2

T4

35

T5

24

disabled

13664

1

T1

1

T4

19

T5

20

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4267	1			T1	1		T4	10		T5	8
key_none	7602	1			T1	1		T4	8		T5	2
key_1024	4154	1			T1	1		T4	7		T5	13
key_512	3535	1			T4	8		T5	7		T6	3
key_384	3234	1			T4	5		T5	4		T9	2
key_256	2706	1			T4	10		T5	4		T6	2
key_128	2688	1			T4	6		T5	5		T6	4

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17919

1

T4

27

T5

29

T6

15

auto[1]

10329

1

T1

3

T4

27

T5

15

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28090

1

T1

3

T4

54

T5

44

disabled

158

1

T65

5

T66

5

T44

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1492

1

T4

8

T5

3

T6

3

enabled

auto[0]

auto[0]

auto[1]

1506

1

T4

5

T5

1

T7

1

enabled

auto[0]

auto[1]

auto[0]

1560

1

T4

5

T5

3

T6

1

enabled

auto[0]

auto[1]

auto[1]

1509

1

T1

2

T4

3

T5

4

enabled

auto[1]

auto[0]

auto[0]

4157

1

T4

6

T5

3

T6

2

enabled

auto[1]

auto[0]

auto[1]

1415

1

T4

2

T6

1

T9

1

enabled

auto[1]

auto[1]

auto[0]

1476

1

T4

2

T5

8

T6

3

enabled

auto[1]

auto[1]

auto[1]

1469

1

T4

4

T5

2

T6

1

disabled

auto[0]

auto[0]

auto[0]

1164

1

T4

5

T5

4

T7

1

disabled

auto[0]

auto[0]

auto[1]

1066

1

T4

6

T5

1

T6

2

disabled

auto[0]

auto[1]

auto[0]

1066

1

T5

3

T6

3

T8

3

disabled

auto[0]

auto[1]

auto[1]

1092

1

T1

1

T4

3

T5

1

disabled

auto[1]

auto[0]

auto[0]

5922

1

T5

3

T6

1

T7

2

disabled

auto[1]

auto[0]

auto[1]

1140

1

T4

2

T5

5

T6

1

disabled

auto[1]

auto[1]

auto[0]

1082

1

T4

1

T5

2

T6

2

disabled

auto[1]

auto[1]

auto[1]

1132

1

T4

2

T5

1

T6

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14528

1

T1

2

T4

35

T5

24

enabled

disabled

56

1

T65

4

T66

1

T44

1

disabled

disabled

102

1

T65

1

T66

4

T44

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13562

1

T1

1

T4

19

T5

20

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	984	1			T4	1		T5	1		T6	1
key_invalid	sha2_none	810	1			T4	4		T5	4		T6	3
key_invalid	sha2_512	798	1			T4	3		T5	2		T9	1
key_invalid	sha2_384	779	1			T1	1		T4	1		T6	2
key_invalid	sha2_256	820	1			T4	1		T5	1		T6	1
key_none	sha2_invalid	503	1			T4	2		T12	2		T25	2
key_none	sha2_none	544	1			T4	1		T6	2		T8	2
key_none	sha2_512	2495	1			T4	2		T5	1		T6	1
key_none	sha2_384	2505	1			T1	1		T4	1		T6	1
key_none	sha2_256	1510	1			T4	2		T6	2		T7	1
key_1024	sha2_invalid	474	1			T5	4		T7	1		T12	3
key_1024	sha2_none	506	1			T1	1		T4	2		T5	2
key_1024	sha2_512	1702	1			T4	2		T5	1		T7	1
key_1024	sha2_384	887	1			T4	2		T5	5		T6	2
key_512	sha2_invalid	470	1			T4	1		T5	2		T6	1
key_512	sha2_none	513	1			T4	2		T25	1		T10	1
key_512	sha2_512	597	1			T4	3		T5	2		T6	1
key_512	sha2_384	1137	1			T4	1		T5	2		T7	2
key_512	sha2_256	787	1			T4	1		T5	1		T6	1
key_384	sha2_invalid	467	1			T7	2		T26	1		T31	1
key_384	sha2_none	506	1			T4	1		T5	1		T9	1
key_384	sha2_512	580	1			T4	2		T5	2		T10	2
key_384	sha2_384	593	1			T4	1		T7	2		T10	1
key_384	sha2_256	1045	1			T4	1		T5	1		T30	90
key_256	sha2_invalid	472	1			T6	1		T26	2		T11	1
key_256	sha2_none	522	1			T4	1		T5	2		T12	1
key_256	sha2_512	523	1			T4	2		T6	1		T9	1
key_256	sha2_384	524	1			T4	4		T5	1		T7	2
key_256	sha2_256	626	1			T4	3		T5	1		T12	4
key_128	sha2_invalid	473	1			T4	2		T5	1		T9	1
key_128	sha2_none	530	1			T4	1		T5	2		T6	1
key_128	sha2_512	560	1			T4	2		T5	2		T7	2
key_128	sha2_384	545	1			T6	1		T7	1		T12	3
key_128	sha2_256	541	1			T4	1		T6	2		T9	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

528

1

T4

1

T5

1

T12

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	984	1			T4	1		T5	1		T6	1
key_invalid	sha2_none	810	1			T4	4		T5	4		T6	3
key_invalid	sha2_512	798	1			T4	3		T5	2		T9	1
key_invalid	sha2_384	779	1			T1	1		T4	1		T6	2
key_invalid	sha2_256	820	1			T4	1		T5	1		T6	1
key_none	sha2_invalid	503	1			T4	2		T12	2		T25	2
key_none	sha2_none	544	1			T4	1		T6	2		T8	2
key_none	sha2_512	2495	1			T4	2		T5	1		T6	1
key_none	sha2_384	2505	1			T1	1		T4	1		T6	1
key_none	sha2_256	1510	1			T4	2		T6	2		T7	1
key_1024	sha2_invalid	474	1			T5	4		T7	1		T12	3
key_1024	sha2_none	506	1			T1	1		T4	2		T5	2
key_1024	sha2_512	1702	1			T4	2		T5	1		T7	1
key_1024	sha2_384	887	1			T4	2		T5	5		T6	2
key_1024	sha2_256	528	1			T4	1		T5	1		T12	2
key_512	sha2_invalid	470	1			T4	1		T5	2		T6	1
key_512	sha2_none	513	1			T4	2		T25	1		T10	1
key_512	sha2_512	597	1			T4	3		T5	2		T6	1
key_512	sha2_384	1137	1			T4	1		T5	2		T7	2
key_512	sha2_256	787	1			T4	1		T5	1		T6	1
key_384	sha2_invalid	467	1			T7	2		T26	1		T31	1
key_384	sha2_none	506	1			T4	1		T5	1		T9	1
key_384	sha2_512	580	1			T4	2		T5	2		T10	2
key_384	sha2_384	593	1			T4	1		T7	2		T10	1
key_384	sha2_256	1045	1			T4	1		T5	1		T30	90
key_256	sha2_invalid	472	1			T6	1		T26	2		T11	1
key_256	sha2_none	522	1			T4	1		T5	2		T12	1
key_256	sha2_512	523	1			T4	2		T6	1		T9	1
key_256	sha2_384	524	1			T4	4		T5	1		T7	2
key_256	sha2_256	626	1			T4	3		T5	1		T12	4
key_128	sha2_invalid	473	1			T4	2		T5	1		T9	1
key_128	sha2_none	530	1			T4	1		T5	2		T6	1
key_128	sha2_512	560	1			T4	2		T5	2		T7	2
key_128	sha2_384	545	1			T6	1		T7	1		T12	3
key_128	sha2_256	541	1			T4	1		T6	2		T9	1