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72 always_ff @(posedge clk_i or negedge rst_ni) begin
73 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
74 1/1 err_q <= '0;
Tests: T1 T2 T3
75 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
76 1/1 err_q <= 1'b1;
Tests: T3 T23 T69
77 end
MISSING_ELSE
78 end
79
80 // integrity error output is permanent and should be used for alert generation
81 // register errors are transactional
82 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
83
84 // outgoing integrity generation
85 tlul_pkg::tl_d2h_t tl_o_pre;
86 tlul_rsp_intg_gen #(
87 .EnableRspIntgGen(1),
88 .EnableDataIntgGen(1)
89 ) u_rsp_intg_gen (
90 .tl_i(tl_o_pre),
91 .tl_o(tl_o)
92 );
93
94 tlul_pkg::tl_h2d_t tl_socket_h2d [2];
95 tlul_pkg::tl_d2h_t tl_socket_d2h [2];
96
97 logic [0:0] reg_steer;
98
99 // socket_1n connection
100 1/1 assign tl_reg_h2d = tl_socket_h2d[1];
Tests: T1 T2 T3
101 1/1 assign tl_socket_d2h[1] = tl_reg_d2h;
Tests: T1 T2 T3
102
103 1/1 assign tl_win_o = tl_socket_h2d[0];
Tests: T1 T2 T3
104 1/1 assign tl_socket_d2h[0] = tl_win_i;
Tests: T1 T2 T3
105
106 // Create Socket_1n
107 tlul_socket_1n #(
108 .N (2),
109 .HReqPass (1'b1),
110 .HRspPass (1'b1),
111 .DReqPass ({2{1'b1}}),
112 .DRspPass ({2{1'b1}}),
113 .HReqDepth (4'h0),
114 .HRspDepth (4'h0),
115 .DReqDepth ({2{4'h0}}),
116 .DRspDepth ({2{4'h0}}),
117 .ExplicitErrs (1'b0)
118 ) u_socket (
119 .clk_i (clk_i),
120 .rst_ni (rst_ni),
121 .tl_h_i (tl_i),
122 .tl_h_o (tl_o_pre),
123 .tl_d_o (tl_socket_h2d),
124 .tl_d_i (tl_socket_d2h),
125 .dev_select_i (reg_steer)
126 );
127
128 // Create steering logic
129 always_comb begin
130 1/1 reg_steer =
Tests: T1 T2 T3
131 tl_i.a_address[AW-1:0] inside {[4096:8191]} ? 1'd0 :
132 // Default set to register
133 1'd1;
134
135 // Override this in case of an integrity error
136 1/1 if (intg_err) begin
Tests: T1 T2 T3
137 1/1 reg_steer = 1'd1;
Tests: T72 T73 T74
138 end
MISSING_ELSE
139 end
140
141 tlul_adapter_reg #(
142 .RegAw(AW),
143 .RegDw(DW),
144 .EnableDataIntgGen(0)
145 ) u_reg_if (
146 .clk_i (clk_i),
147 .rst_ni (rst_ni),
148
149 .tl_i (tl_reg_h2d),
150 .tl_o (tl_reg_d2h),
151
152 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
153 .intg_error_o(),
154
155 .we_o (reg_we),
156 .re_o (reg_re),
157 .addr_o (reg_addr),
158 .wdata_o (reg_wdata),
159 .be_o (reg_be),
160 .busy_i (reg_busy),
161 .rdata_i (reg_rdata),
162 .error_i (reg_error)
163 );
164
165 // cdc oversampling signals
166
167 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
168 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T3 T24
169
170 // Define SW related signals
171 // Format: <reg>_<field>_{wd|we|qs}
172 // or <reg>_{wd|we|qs} if field == 1 or 0
173 logic intr_state_we;
174 logic intr_state_hmac_done_qs;
175 logic intr_state_hmac_done_wd;
176 logic intr_state_fifo_empty_qs;
177 logic intr_state_hmac_err_qs;
178 logic intr_state_hmac_err_wd;
179 logic intr_enable_we;
180 logic intr_enable_hmac_done_qs;
181 logic intr_enable_hmac_done_wd;
182 logic intr_enable_fifo_empty_qs;
183 logic intr_enable_fifo_empty_wd;
184 logic intr_enable_hmac_err_qs;
185 logic intr_enable_hmac_err_wd;
186 logic intr_test_we;
187 logic intr_test_hmac_done_wd;
188 logic intr_test_fifo_empty_wd;
189 logic intr_test_hmac_err_wd;
190 logic alert_test_we;
191 logic alert_test_wd;
192 logic cfg_re;
193 logic cfg_we;
194 logic cfg_hmac_en_qs;
195 logic cfg_hmac_en_wd;
196 logic cfg_sha_en_qs;
197 logic cfg_sha_en_wd;
198 logic cfg_endian_swap_qs;
199 logic cfg_endian_swap_wd;
200 logic cfg_digest_swap_qs;
201 logic cfg_digest_swap_wd;
202 logic cfg_key_swap_qs;
203 logic cfg_key_swap_wd;
204 logic [3:0] cfg_digest_size_qs;
205 logic [3:0] cfg_digest_size_wd;
206 logic [5:0] cfg_key_length_qs;
207 logic [5:0] cfg_key_length_wd;
208 logic cmd_we;
209 logic cmd_hash_start_wd;
210 logic cmd_hash_process_wd;
211 logic cmd_hash_stop_wd;
212 logic cmd_hash_continue_wd;
213 logic status_re;
214 logic status_hmac_idle_qs;
215 logic status_fifo_empty_qs;
216 logic status_fifo_full_qs;
217 logic [5:0] status_fifo_depth_qs;
218 logic [31:0] err_code_qs;
219 logic wipe_secret_we;
220 logic [31:0] wipe_secret_wd;
221 logic key_0_we;
222 logic [31:0] key_0_wd;
223 logic key_1_we;
224 logic [31:0] key_1_wd;
225 logic key_2_we;
226 logic [31:0] key_2_wd;
227 logic key_3_we;
228 logic [31:0] key_3_wd;
229 logic key_4_we;
230 logic [31:0] key_4_wd;
231 logic key_5_we;
232 logic [31:0] key_5_wd;
233 logic key_6_we;
234 logic [31:0] key_6_wd;
235 logic key_7_we;
236 logic [31:0] key_7_wd;
237 logic key_8_we;
238 logic [31:0] key_8_wd;
239 logic key_9_we;
240 logic [31:0] key_9_wd;
241 logic key_10_we;
242 logic [31:0] key_10_wd;
243 logic key_11_we;
244 logic [31:0] key_11_wd;
245 logic key_12_we;
246 logic [31:0] key_12_wd;
247 logic key_13_we;
248 logic [31:0] key_13_wd;
249 logic key_14_we;
250 logic [31:0] key_14_wd;
251 logic key_15_we;
252 logic [31:0] key_15_wd;
253 logic key_16_we;
254 logic [31:0] key_16_wd;
255 logic key_17_we;
256 logic [31:0] key_17_wd;
257 logic key_18_we;
258 logic [31:0] key_18_wd;
259 logic key_19_we;
260 logic [31:0] key_19_wd;
261 logic key_20_we;
262 logic [31:0] key_20_wd;
263 logic key_21_we;
264 logic [31:0] key_21_wd;
265 logic key_22_we;
266 logic [31:0] key_22_wd;
267 logic key_23_we;
268 logic [31:0] key_23_wd;
269 logic key_24_we;
270 logic [31:0] key_24_wd;
271 logic key_25_we;
272 logic [31:0] key_25_wd;
273 logic key_26_we;
274 logic [31:0] key_26_wd;
275 logic key_27_we;
276 logic [31:0] key_27_wd;
277 logic key_28_we;
278 logic [31:0] key_28_wd;
279 logic key_29_we;
280 logic [31:0] key_29_wd;
281 logic key_30_we;
282 logic [31:0] key_30_wd;
283 logic key_31_we;
284 logic [31:0] key_31_wd;
285 logic digest_0_re;
286 logic digest_0_we;
287 logic [31:0] digest_0_qs;
288 logic [31:0] digest_0_wd;
289 logic digest_1_re;
290 logic digest_1_we;
291 logic [31:0] digest_1_qs;
292 logic [31:0] digest_1_wd;
293 logic digest_2_re;
294 logic digest_2_we;
295 logic [31:0] digest_2_qs;
296 logic [31:0] digest_2_wd;
297 logic digest_3_re;
298 logic digest_3_we;
299 logic [31:0] digest_3_qs;
300 logic [31:0] digest_3_wd;
301 logic digest_4_re;
302 logic digest_4_we;
303 logic [31:0] digest_4_qs;
304 logic [31:0] digest_4_wd;
305 logic digest_5_re;
306 logic digest_5_we;
307 logic [31:0] digest_5_qs;
308 logic [31:0] digest_5_wd;
309 logic digest_6_re;
310 logic digest_6_we;
311 logic [31:0] digest_6_qs;
312 logic [31:0] digest_6_wd;
313 logic digest_7_re;
314 logic digest_7_we;
315 logic [31:0] digest_7_qs;
316 logic [31:0] digest_7_wd;
317 logic digest_8_re;
318 logic digest_8_we;
319 logic [31:0] digest_8_qs;
320 logic [31:0] digest_8_wd;
321 logic digest_9_re;
322 logic digest_9_we;
323 logic [31:0] digest_9_qs;
324 logic [31:0] digest_9_wd;
325 logic digest_10_re;
326 logic digest_10_we;
327 logic [31:0] digest_10_qs;
328 logic [31:0] digest_10_wd;
329 logic digest_11_re;
330 logic digest_11_we;
331 logic [31:0] digest_11_qs;
332 logic [31:0] digest_11_wd;
333 logic digest_12_re;
334 logic digest_12_we;
335 logic [31:0] digest_12_qs;
336 logic [31:0] digest_12_wd;
337 logic digest_13_re;
338 logic digest_13_we;
339 logic [31:0] digest_13_qs;
340 logic [31:0] digest_13_wd;
341 logic digest_14_re;
342 logic digest_14_we;
343 logic [31:0] digest_14_qs;
344 logic [31:0] digest_14_wd;
345 logic digest_15_re;
346 logic digest_15_we;
347 logic [31:0] digest_15_qs;
348 logic [31:0] digest_15_wd;
349 logic msg_length_lower_re;
350 logic msg_length_lower_we;
351 logic [31:0] msg_length_lower_qs;
352 logic [31:0] msg_length_lower_wd;
353 logic msg_length_upper_re;
354 logic msg_length_upper_we;
355 logic [31:0] msg_length_upper_qs;
356 logic [31:0] msg_length_upper_wd;
357
358 // Register instances
359 // R[intr_state]: V(False)
360 // F[hmac_done]: 0:0
361 prim_subreg #(
362 .DW (1),
363 .SwAccess(prim_subreg_pkg::SwAccessW1C),
364 .RESVAL (1'h0),
365 .Mubi (1'b0)
366 ) u_intr_state_hmac_done (
367 .clk_i (clk_i),
368 .rst_ni (rst_ni),
369
370 // from register interface
371 .we (intr_state_we),
372 .wd (intr_state_hmac_done_wd),
373
374 // from internal hardware
375 .de (hw2reg.intr_state.hmac_done.de),
376 .d (hw2reg.intr_state.hmac_done.d),
377
378 // to internal hardware
379 .qe (),
380 .q (reg2hw.intr_state.hmac_done.q),
381 .ds (),
382
383 // to register interface (read)
384 .qs (intr_state_hmac_done_qs)
385 );
386
387 // F[fifo_empty]: 1:1
388 prim_subreg #(
389 .DW (1),
390 .SwAccess(prim_subreg_pkg::SwAccessRO),
391 .RESVAL (1'h0),
392 .Mubi (1'b0)
393 ) u_intr_state_fifo_empty (
394 .clk_i (clk_i),
395 .rst_ni (rst_ni),
396
397 // from register interface
398 .we (1'b0),
399 .wd ('0),
400
401 // from internal hardware
402 .de (hw2reg.intr_state.fifo_empty.de),
403 .d (hw2reg.intr_state.fifo_empty.d),
404
405 // to internal hardware
406 .qe (),
407 .q (reg2hw.intr_state.fifo_empty.q),
408 .ds (),
409
410 // to register interface (read)
411 .qs (intr_state_fifo_empty_qs)
412 );
413
414 // F[hmac_err]: 2:2
415 prim_subreg #(
416 .DW (1),
417 .SwAccess(prim_subreg_pkg::SwAccessW1C),
418 .RESVAL (1'h0),
419 .Mubi (1'b0)
420 ) u_intr_state_hmac_err (
421 .clk_i (clk_i),
422 .rst_ni (rst_ni),
423
424 // from register interface
425 .we (intr_state_we),
426 .wd (intr_state_hmac_err_wd),
427
428 // from internal hardware
429 .de (hw2reg.intr_state.hmac_err.de),
430 .d (hw2reg.intr_state.hmac_err.d),
431
432 // to internal hardware
433 .qe (),
434 .q (reg2hw.intr_state.hmac_err.q),
435 .ds (),
436
437 // to register interface (read)
438 .qs (intr_state_hmac_err_qs)
439 );
440
441
442 // R[intr_enable]: V(False)
443 // F[hmac_done]: 0:0
444 prim_subreg #(
445 .DW (1),
446 .SwAccess(prim_subreg_pkg::SwAccessRW),
447 .RESVAL (1'h0),
448 .Mubi (1'b0)
449 ) u_intr_enable_hmac_done (
450 .clk_i (clk_i),
451 .rst_ni (rst_ni),
452
453 // from register interface
454 .we (intr_enable_we),
455 .wd (intr_enable_hmac_done_wd),
456
457 // from internal hardware
458 .de (1'b0),
459 .d ('0),
460
461 // to internal hardware
462 .qe (),
463 .q (reg2hw.intr_enable.hmac_done.q),
464 .ds (),
465
466 // to register interface (read)
467 .qs (intr_enable_hmac_done_qs)
468 );
469
470 // F[fifo_empty]: 1:1
471 prim_subreg #(
472 .DW (1),
473 .SwAccess(prim_subreg_pkg::SwAccessRW),
474 .RESVAL (1'h0),
475 .Mubi (1'b0)
476 ) u_intr_enable_fifo_empty (
477 .clk_i (clk_i),
478 .rst_ni (rst_ni),
479
480 // from register interface
481 .we (intr_enable_we),
482 .wd (intr_enable_fifo_empty_wd),
483
484 // from internal hardware
485 .de (1'b0),
486 .d ('0),
487
488 // to internal hardware
489 .qe (),
490 .q (reg2hw.intr_enable.fifo_empty.q),
491 .ds (),
492
493 // to register interface (read)
494 .qs (intr_enable_fifo_empty_qs)
495 );
496
497 // F[hmac_err]: 2:2
498 prim_subreg #(
499 .DW (1),
500 .SwAccess(prim_subreg_pkg::SwAccessRW),
501 .RESVAL (1'h0),
502 .Mubi (1'b0)
503 ) u_intr_enable_hmac_err (
504 .clk_i (clk_i),
505 .rst_ni (rst_ni),
506
507 // from register interface
508 .we (intr_enable_we),
509 .wd (intr_enable_hmac_err_wd),
510
511 // from internal hardware
512 .de (1'b0),
513 .d ('0),
514
515 // to internal hardware
516 .qe (),
517 .q (reg2hw.intr_enable.hmac_err.q),
518 .ds (),
519
520 // to register interface (read)
521 .qs (intr_enable_hmac_err_qs)
522 );
523
524
525 // R[intr_test]: V(True)
526 logic intr_test_qe;
527 logic [2:0] intr_test_flds_we;
528 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T15 T75 T17
529 // F[hmac_done]: 0:0
530 prim_subreg_ext #(
531 .DW (1)
532 ) u_intr_test_hmac_done (
533 .re (1'b0),
534 .we (intr_test_we),
535 .wd (intr_test_hmac_done_wd),
536 .d ('0),
537 .qre (),
538 .qe (intr_test_flds_we[0]),
539 .q (reg2hw.intr_test.hmac_done.q),
540 .ds (),
541 .qs ()
542 );
543 1/1 assign reg2hw.intr_test.hmac_done.qe = intr_test_qe;
Tests: T15 T75 T17
544
545 // F[fifo_empty]: 1:1
546 prim_subreg_ext #(
547 .DW (1)
548 ) u_intr_test_fifo_empty (
549 .re (1'b0),
550 .we (intr_test_we),
551 .wd (intr_test_fifo_empty_wd),
552 .d ('0),
553 .qre (),
554 .qe (intr_test_flds_we[1]),
555 .q (reg2hw.intr_test.fifo_empty.q),
556 .ds (),
557 .qs ()
558 );
559 1/1 assign reg2hw.intr_test.fifo_empty.qe = intr_test_qe;
Tests: T15 T75 T17
560
561 // F[hmac_err]: 2:2
562 prim_subreg_ext #(
563 .DW (1)
564 ) u_intr_test_hmac_err (
565 .re (1'b0),
566 .we (intr_test_we),
567 .wd (intr_test_hmac_err_wd),
568 .d ('0),
569 .qre (),
570 .qe (intr_test_flds_we[2]),
571 .q (reg2hw.intr_test.hmac_err.q),
572 .ds (),
573 .qs ()
574 );
575 1/1 assign reg2hw.intr_test.hmac_err.qe = intr_test_qe;
Tests: T15 T75 T17
576
577
578 // R[alert_test]: V(True)
579 logic alert_test_qe;
580 logic [0:0] alert_test_flds_we;
581 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T2 T24 T68
582 prim_subreg_ext #(
583 .DW (1)
584 ) u_alert_test (
585 .re (1'b0),
586 .we (alert_test_we),
587 .wd (alert_test_wd),
588 .d ('0),
589 .qre (),
590 .qe (alert_test_flds_we[0]),
591 .q (reg2hw.alert_test.q),
592 .ds (),
593 .qs ()
594 );
595 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T2 T24 T68
596
597
598 // R[cfg]: V(True)
599 logic cfg_qe;
600 logic [6:0] cfg_flds_we;
601 1/1 assign cfg_qe = &cfg_flds_we;
Tests: T1 T4 T5
602 // F[hmac_en]: 0:0
603 prim_subreg_ext #(
604 .DW (1)
605 ) u_cfg_hmac_en (
606 .re (cfg_re),
607 .we (cfg_we),
608 .wd (cfg_hmac_en_wd),
609 .d (hw2reg.cfg.hmac_en.d),
610 .qre (),
611 .qe (cfg_flds_we[0]),
612 .q (reg2hw.cfg.hmac_en.q),
613 .ds (),
614 .qs (cfg_hmac_en_qs)
615 );
616 1/1 assign reg2hw.cfg.hmac_en.qe = cfg_qe;
Tests: T1 T4 T5
617
618 // F[sha_en]: 1:1
619 prim_subreg_ext #(
620 .DW (1)
621 ) u_cfg_sha_en (
622 .re (cfg_re),
623 .we (cfg_we),
624 .wd (cfg_sha_en_wd),
625 .d (hw2reg.cfg.sha_en.d),
626 .qre (),
627 .qe (cfg_flds_we[1]),
628 .q (reg2hw.cfg.sha_en.q),
629 .ds (),
630 .qs (cfg_sha_en_qs)
631 );
632 1/1 assign reg2hw.cfg.sha_en.qe = cfg_qe;
Tests: T1 T4 T5
633
634 // F[endian_swap]: 2:2
635 prim_subreg_ext #(
636 .DW (1)
637 ) u_cfg_endian_swap (
638 .re (cfg_re),
639 .we (cfg_we),
640 .wd (cfg_endian_swap_wd),
641 .d (hw2reg.cfg.endian_swap.d),
642 .qre (),
643 .qe (cfg_flds_we[2]),
644 .q (reg2hw.cfg.endian_swap.q),
645 .ds (),
646 .qs (cfg_endian_swap_qs)
647 );
648 1/1 assign reg2hw.cfg.endian_swap.qe = cfg_qe;
Tests: T1 T4 T5
649
650 // F[digest_swap]: 3:3
651 prim_subreg_ext #(
652 .DW (1)
653 ) u_cfg_digest_swap (
654 .re (cfg_re),
655 .we (cfg_we),
656 .wd (cfg_digest_swap_wd),
657 .d (hw2reg.cfg.digest_swap.d),
658 .qre (),
659 .qe (cfg_flds_we[3]),
660 .q (reg2hw.cfg.digest_swap.q),
661 .ds (),
662 .qs (cfg_digest_swap_qs)
663 );
664 1/1 assign reg2hw.cfg.digest_swap.qe = cfg_qe;
Tests: T1 T4 T5
665
666 // F[key_swap]: 4:4
667 prim_subreg_ext #(
668 .DW (1)
669 ) u_cfg_key_swap (
670 .re (cfg_re),
671 .we (cfg_we),
672 .wd (cfg_key_swap_wd),
673 .d (hw2reg.cfg.key_swap.d),
674 .qre (),
675 .qe (cfg_flds_we[4]),
676 .q (reg2hw.cfg.key_swap.q),
677 .ds (),
678 .qs (cfg_key_swap_qs)
679 );
680 1/1 assign reg2hw.cfg.key_swap.qe = cfg_qe;
Tests: T1 T4 T5
681
682 // F[digest_size]: 8:5
683 prim_subreg_ext #(
684 .DW (4)
685 ) u_cfg_digest_size (
686 .re (cfg_re),
687 .we (cfg_we),
688 .wd (cfg_digest_size_wd),
689 .d (hw2reg.cfg.digest_size.d),
690 .qre (),
691 .qe (cfg_flds_we[5]),
692 .q (reg2hw.cfg.digest_size.q),
693 .ds (),
694 .qs (cfg_digest_size_qs)
695 );
696 1/1 assign reg2hw.cfg.digest_size.qe = cfg_qe;
Tests: T1 T4 T5
697
698 // F[key_length]: 14:9
699 prim_subreg_ext #(
700 .DW (6)
701 ) u_cfg_key_length (
702 .re (cfg_re),
703 .we (cfg_we),
704 .wd (cfg_key_length_wd),
705 .d (hw2reg.cfg.key_length.d),
706 .qre (),
707 .qe (cfg_flds_we[6]),
708 .q (reg2hw.cfg.key_length.q),
709 .ds (),
710 .qs (cfg_key_length_qs)
711 );
712 1/1 assign reg2hw.cfg.key_length.qe = cfg_qe;
Tests: T1 T4 T5
713
714
715 // R[cmd]: V(True)
716 logic cmd_qe;
717 logic [3:0] cmd_flds_we;
718 1/1 assign cmd_qe = &cmd_flds_we;
Tests: T1 T4 T5
719 // F[hash_start]: 0:0
720 prim_subreg_ext #(
721 .DW (1)
722 ) u_cmd_hash_start (
723 .re (1'b0),
724 .we (cmd_we),
725 .wd (cmd_hash_start_wd),
726 .d ('0),
727 .qre (),
728 .qe (cmd_flds_we[0]),
729 .q (reg2hw.cmd.hash_start.q),
730 .ds (),
731 .qs ()
732 );
733 1/1 assign reg2hw.cmd.hash_start.qe = cmd_qe;
Tests: T1 T4 T5
734
735 // F[hash_process]: 1:1
736 prim_subreg_ext #(
737 .DW (1)
738 ) u_cmd_hash_process (
739 .re (1'b0),
740 .we (cmd_we),
741 .wd (cmd_hash_process_wd),
742 .d ('0),
743 .qre (),
744 .qe (cmd_flds_we[1]),
745 .q (reg2hw.cmd.hash_process.q),
746 .ds (),
747 .qs ()
748 );
749 1/1 assign reg2hw.cmd.hash_process.qe = cmd_qe;
Tests: T1 T4 T5
750
751 // F[hash_stop]: 2:2
752 prim_subreg_ext #(
753 .DW (1)
754 ) u_cmd_hash_stop (
755 .re (1'b0),
756 .we (cmd_we),
757 .wd (cmd_hash_stop_wd),
758 .d ('0),
759 .qre (),
760 .qe (cmd_flds_we[2]),
761 .q (reg2hw.cmd.hash_stop.q),
762 .ds (),
763 .qs ()
764 );
765 1/1 assign reg2hw.cmd.hash_stop.qe = cmd_qe;
Tests: T1 T4 T5
766
767 // F[hash_continue]: 3:3
768 prim_subreg_ext #(
769 .DW (1)
770 ) u_cmd_hash_continue (
771 .re (1'b0),
772 .we (cmd_we),
773 .wd (cmd_hash_continue_wd),
774 .d ('0),
775 .qre (),
776 .qe (cmd_flds_we[3]),
777 .q (reg2hw.cmd.hash_continue.q),
778 .ds (),
779 .qs ()
780 );
781 1/1 assign reg2hw.cmd.hash_continue.qe = cmd_qe;
Tests: T1 T4 T5
782
783
784 // R[status]: V(True)
785 // F[hmac_idle]: 0:0
786 prim_subreg_ext #(
787 .DW (1)
788 ) u_status_hmac_idle (
789 .re (status_re),
790 .we (1'b0),
791 .wd ('0),
792 .d (hw2reg.status.hmac_idle.d),
793 .qre (),
794 .qe (),
795 .q (),
796 .ds (),
797 .qs (status_hmac_idle_qs)
798 );
799
800 // F[fifo_empty]: 1:1
801 prim_subreg_ext #(
802 .DW (1)
803 ) u_status_fifo_empty (
804 .re (status_re),
805 .we (1'b0),
806 .wd ('0),
807 .d (hw2reg.status.fifo_empty.d),
808 .qre (),
809 .qe (),
810 .q (),
811 .ds (),
812 .qs (status_fifo_empty_qs)
813 );
814
815 // F[fifo_full]: 2:2
816 prim_subreg_ext #(
817 .DW (1)
818 ) u_status_fifo_full (
819 .re (status_re),
820 .we (1'b0),
821 .wd ('0),
822 .d (hw2reg.status.fifo_full.d),
823 .qre (),
824 .qe (),
825 .q (),
826 .ds (),
827 .qs (status_fifo_full_qs)
828 );
829
830 // F[fifo_depth]: 9:4
831 prim_subreg_ext #(
832 .DW (6)
833 ) u_status_fifo_depth (
834 .re (status_re),
835 .we (1'b0),
836 .wd ('0),
837 .d (hw2reg.status.fifo_depth.d),
838 .qre (),
839 .qe (),
840 .q (),
841 .ds (),
842 .qs (status_fifo_depth_qs)
843 );
844
845
846 // R[err_code]: V(False)
847 prim_subreg #(
848 .DW (32),
849 .SwAccess(prim_subreg_pkg::SwAccessRO),
850 .RESVAL (32'h0),
851 .Mubi (1'b0)
852 ) u_err_code (
853 .clk_i (clk_i),
854 .rst_ni (rst_ni),
855
856 // from register interface
857 .we (1'b0),
858 .wd ('0),
859
860 // from internal hardware
861 .de (hw2reg.err_code.de),
862 .d (hw2reg.err_code.d),
863
864 // to internal hardware
865 .qe (),
866 .q (),
867 .ds (),
868
869 // to register interface (read)
870 .qs (err_code_qs)
871 );
872
873
874 // R[wipe_secret]: V(True)
875 logic wipe_secret_qe;
876 logic [0:0] wipe_secret_flds_we;
877 1/1 assign wipe_secret_qe = &wipe_secret_flds_we;
Tests: T9 T10 T31
878 prim_subreg_ext #(
879 .DW (32)
880 ) u_wipe_secret (
881 .re (1'b0),
882 .we (wipe_secret_we),
883 .wd (wipe_secret_wd),
884 .d ('0),
885 .qre (),
886 .qe (wipe_secret_flds_we[0]),
887 .q (reg2hw.wipe_secret.q),
888 .ds (),
889 .qs ()
890 );
891 1/1 assign reg2hw.wipe_secret.qe = wipe_secret_qe;
Tests: T9 T10 T31
892
893
894 // Subregister 0 of Multireg key
895 // R[key_0]: V(True)
896 logic key_0_qe;
897 logic [0:0] key_0_flds_we;
898 1/1 assign key_0_qe = &key_0_flds_we;
Tests: T1 T4 T5
899 prim_subreg_ext #(
900 .DW (32)
901 ) u_key_0 (
902 .re (1'b0),
903 .we (key_0_we),
904 .wd (key_0_wd),
905 .d (hw2reg.key[0].d),
906 .qre (),
907 .qe (key_0_flds_we[0]),
908 .q (reg2hw.key[0].q),
909 .ds (),
910 .qs ()
911 );
912 1/1 assign reg2hw.key[0].qe = key_0_qe;
Tests: T1 T4 T5
913
914
915 // Subregister 1 of Multireg key
916 // R[key_1]: V(True)
917 logic key_1_qe;
918 logic [0:0] key_1_flds_we;
919 1/1 assign key_1_qe = &key_1_flds_we;
Tests: T1 T4 T5
920 prim_subreg_ext #(
921 .DW (32)
922 ) u_key_1 (
923 .re (1'b0),
924 .we (key_1_we),
925 .wd (key_1_wd),
926 .d (hw2reg.key[1].d),
927 .qre (),
928 .qe (key_1_flds_we[0]),
929 .q (reg2hw.key[1].q),
930 .ds (),
931 .qs ()
932 );
933 1/1 assign reg2hw.key[1].qe = key_1_qe;
Tests: T1 T4 T5
934
935
936 // Subregister 2 of Multireg key
937 // R[key_2]: V(True)
938 logic key_2_qe;
939 logic [0:0] key_2_flds_we;
940 1/1 assign key_2_qe = &key_2_flds_we;
Tests: T1 T4 T5
941 prim_subreg_ext #(
942 .DW (32)
943 ) u_key_2 (
944 .re (1'b0),
945 .we (key_2_we),
946 .wd (key_2_wd),
947 .d (hw2reg.key[2].d),
948 .qre (),
949 .qe (key_2_flds_we[0]),
950 .q (reg2hw.key[2].q),
951 .ds (),
952 .qs ()
953 );
954 1/1 assign reg2hw.key[2].qe = key_2_qe;
Tests: T1 T4 T5
955
956
957 // Subregister 3 of Multireg key
958 // R[key_3]: V(True)
959 logic key_3_qe;
960 logic [0:0] key_3_flds_we;
961 1/1 assign key_3_qe = &key_3_flds_we;
Tests: T1 T4 T5
962 prim_subreg_ext #(
963 .DW (32)
964 ) u_key_3 (
965 .re (1'b0),
966 .we (key_3_we),
967 .wd (key_3_wd),
968 .d (hw2reg.key[3].d),
969 .qre (),
970 .qe (key_3_flds_we[0]),
971 .q (reg2hw.key[3].q),
972 .ds (),
973 .qs ()
974 );
975 1/1 assign reg2hw.key[3].qe = key_3_qe;
Tests: T1 T4 T5
976
977
978 // Subregister 4 of Multireg key
979 // R[key_4]: V(True)
980 logic key_4_qe;
981 logic [0:0] key_4_flds_we;
982 1/1 assign key_4_qe = &key_4_flds_we;
Tests: T1 T4 T5
983 prim_subreg_ext #(
984 .DW (32)
985 ) u_key_4 (
986 .re (1'b0),
987 .we (key_4_we),
988 .wd (key_4_wd),
989 .d (hw2reg.key[4].d),
990 .qre (),
991 .qe (key_4_flds_we[0]),
992 .q (reg2hw.key[4].q),
993 .ds (),
994 .qs ()
995 );
996 1/1 assign reg2hw.key[4].qe = key_4_qe;
Tests: T1 T4 T5
997
998
999 // Subregister 5 of Multireg key
1000 // R[key_5]: V(True)
1001 logic key_5_qe;
1002 logic [0:0] key_5_flds_we;
1003 1/1 assign key_5_qe = &key_5_flds_we;
Tests: T1 T4 T5
1004 prim_subreg_ext #(
1005 .DW (32)
1006 ) u_key_5 (
1007 .re (1'b0),
1008 .we (key_5_we),
1009 .wd (key_5_wd),
1010 .d (hw2reg.key[5].d),
1011 .qre (),
1012 .qe (key_5_flds_we[0]),
1013 .q (reg2hw.key[5].q),
1014 .ds (),
1015 .qs ()
1016 );
1017 1/1 assign reg2hw.key[5].qe = key_5_qe;
Tests: T1 T4 T5
1018
1019
1020 // Subregister 6 of Multireg key
1021 // R[key_6]: V(True)
1022 logic key_6_qe;
1023 logic [0:0] key_6_flds_we;
1024 1/1 assign key_6_qe = &key_6_flds_we;
Tests: T1 T4 T5
1025 prim_subreg_ext #(
1026 .DW (32)
1027 ) u_key_6 (
1028 .re (1'b0),
1029 .we (key_6_we),
1030 .wd (key_6_wd),
1031 .d (hw2reg.key[6].d),
1032 .qre (),
1033 .qe (key_6_flds_we[0]),
1034 .q (reg2hw.key[6].q),
1035 .ds (),
1036 .qs ()
1037 );
1038 1/1 assign reg2hw.key[6].qe = key_6_qe;
Tests: T1 T4 T5
1039
1040
1041 // Subregister 7 of Multireg key
1042 // R[key_7]: V(True)
1043 logic key_7_qe;
1044 logic [0:0] key_7_flds_we;
1045 1/1 assign key_7_qe = &key_7_flds_we;
Tests: T1 T4 T5
1046 prim_subreg_ext #(
1047 .DW (32)
1048 ) u_key_7 (
1049 .re (1'b0),
1050 .we (key_7_we),
1051 .wd (key_7_wd),
1052 .d (hw2reg.key[7].d),
1053 .qre (),
1054 .qe (key_7_flds_we[0]),
1055 .q (reg2hw.key[7].q),
1056 .ds (),
1057 .qs ()
1058 );
1059 1/1 assign reg2hw.key[7].qe = key_7_qe;
Tests: T1 T4 T5
1060
1061
1062 // Subregister 8 of Multireg key
1063 // R[key_8]: V(True)
1064 logic key_8_qe;
1065 logic [0:0] key_8_flds_we;
1066 1/1 assign key_8_qe = &key_8_flds_we;
Tests: T1 T4 T5
1067 prim_subreg_ext #(
1068 .DW (32)
1069 ) u_key_8 (
1070 .re (1'b0),
1071 .we (key_8_we),
1072 .wd (key_8_wd),
1073 .d (hw2reg.key[8].d),
1074 .qre (),
1075 .qe (key_8_flds_we[0]),
1076 .q (reg2hw.key[8].q),
1077 .ds (),
1078 .qs ()
1079 );
1080 1/1 assign reg2hw.key[8].qe = key_8_qe;
Tests: T1 T4 T5
1081
1082
1083 // Subregister 9 of Multireg key
1084 // R[key_9]: V(True)
1085 logic key_9_qe;
1086 logic [0:0] key_9_flds_we;
1087 1/1 assign key_9_qe = &key_9_flds_we;
Tests: T1 T4 T5
1088 prim_subreg_ext #(
1089 .DW (32)
1090 ) u_key_9 (
1091 .re (1'b0),
1092 .we (key_9_we),
1093 .wd (key_9_wd),
1094 .d (hw2reg.key[9].d),
1095 .qre (),
1096 .qe (key_9_flds_we[0]),
1097 .q (reg2hw.key[9].q),
1098 .ds (),
1099 .qs ()
1100 );
1101 1/1 assign reg2hw.key[9].qe = key_9_qe;
Tests: T1 T4 T5
1102
1103
1104 // Subregister 10 of Multireg key
1105 // R[key_10]: V(True)
1106 logic key_10_qe;
1107 logic [0:0] key_10_flds_we;
1108 1/1 assign key_10_qe = &key_10_flds_we;
Tests: T1 T4 T5
1109 prim_subreg_ext #(
1110 .DW (32)
1111 ) u_key_10 (
1112 .re (1'b0),
1113 .we (key_10_we),
1114 .wd (key_10_wd),
1115 .d (hw2reg.key[10].d),
1116 .qre (),
1117 .qe (key_10_flds_we[0]),
1118 .q (reg2hw.key[10].q),
1119 .ds (),
1120 .qs ()
1121 );
1122 1/1 assign reg2hw.key[10].qe = key_10_qe;
Tests: T1 T4 T5
1123
1124
1125 // Subregister 11 of Multireg key
1126 // R[key_11]: V(True)
1127 logic key_11_qe;
1128 logic [0:0] key_11_flds_we;
1129 1/1 assign key_11_qe = &key_11_flds_we;
Tests: T1 T4 T5
1130 prim_subreg_ext #(
1131 .DW (32)
1132 ) u_key_11 (
1133 .re (1'b0),
1134 .we (key_11_we),
1135 .wd (key_11_wd),
1136 .d (hw2reg.key[11].d),
1137 .qre (),
1138 .qe (key_11_flds_we[0]),
1139 .q (reg2hw.key[11].q),
1140 .ds (),
1141 .qs ()
1142 );
1143 1/1 assign reg2hw.key[11].qe = key_11_qe;
Tests: T1 T4 T5
1144
1145
1146 // Subregister 12 of Multireg key
1147 // R[key_12]: V(True)
1148 logic key_12_qe;
1149 logic [0:0] key_12_flds_we;
1150 1/1 assign key_12_qe = &key_12_flds_we;
Tests: T1 T4 T5
1151 prim_subreg_ext #(
1152 .DW (32)
1153 ) u_key_12 (
1154 .re (1'b0),
1155 .we (key_12_we),
1156 .wd (key_12_wd),
1157 .d (hw2reg.key[12].d),
1158 .qre (),
1159 .qe (key_12_flds_we[0]),
1160 .q (reg2hw.key[12].q),
1161 .ds (),
1162 .qs ()
1163 );
1164 1/1 assign reg2hw.key[12].qe = key_12_qe;
Tests: T1 T4 T5
1165
1166
1167 // Subregister 13 of Multireg key
1168 // R[key_13]: V(True)
1169 logic key_13_qe;
1170 logic [0:0] key_13_flds_we;
1171 1/1 assign key_13_qe = &key_13_flds_we;
Tests: T1 T4 T5
1172 prim_subreg_ext #(
1173 .DW (32)
1174 ) u_key_13 (
1175 .re (1'b0),
1176 .we (key_13_we),
1177 .wd (key_13_wd),
1178 .d (hw2reg.key[13].d),
1179 .qre (),
1180 .qe (key_13_flds_we[0]),
1181 .q (reg2hw.key[13].q),
1182 .ds (),
1183 .qs ()
1184 );
1185 1/1 assign reg2hw.key[13].qe = key_13_qe;
Tests: T1 T4 T5
1186
1187
1188 // Subregister 14 of Multireg key
1189 // R[key_14]: V(True)
1190 logic key_14_qe;
1191 logic [0:0] key_14_flds_we;
1192 1/1 assign key_14_qe = &key_14_flds_we;
Tests: T1 T4 T5
1193 prim_subreg_ext #(
1194 .DW (32)
1195 ) u_key_14 (
1196 .re (1'b0),
1197 .we (key_14_we),
1198 .wd (key_14_wd),
1199 .d (hw2reg.key[14].d),
1200 .qre (),
1201 .qe (key_14_flds_we[0]),
1202 .q (reg2hw.key[14].q),
1203 .ds (),
1204 .qs ()
1205 );
1206 1/1 assign reg2hw.key[14].qe = key_14_qe;
Tests: T1 T4 T5
1207
1208
1209 // Subregister 15 of Multireg key
1210 // R[key_15]: V(True)
1211 logic key_15_qe;
1212 logic [0:0] key_15_flds_we;
1213 1/1 assign key_15_qe = &key_15_flds_we;
Tests: T1 T4 T5
1214 prim_subreg_ext #(
1215 .DW (32)
1216 ) u_key_15 (
1217 .re (1'b0),
1218 .we (key_15_we),
1219 .wd (key_15_wd),
1220 .d (hw2reg.key[15].d),
1221 .qre (),
1222 .qe (key_15_flds_we[0]),
1223 .q (reg2hw.key[15].q),
1224 .ds (),
1225 .qs ()
1226 );
1227 1/1 assign reg2hw.key[15].qe = key_15_qe;
Tests: T1 T4 T5
1228
1229
1230 // Subregister 16 of Multireg key
1231 // R[key_16]: V(True)
1232 logic key_16_qe;
1233 logic [0:0] key_16_flds_we;
1234 1/1 assign key_16_qe = &key_16_flds_we;
Tests: T1 T4 T5
1235 prim_subreg_ext #(
1236 .DW (32)
1237 ) u_key_16 (
1238 .re (1'b0),
1239 .we (key_16_we),
1240 .wd (key_16_wd),
1241 .d (hw2reg.key[16].d),
1242 .qre (),
1243 .qe (key_16_flds_we[0]),
1244 .q (reg2hw.key[16].q),
1245 .ds (),
1246 .qs ()
1247 );
1248 1/1 assign reg2hw.key[16].qe = key_16_qe;
Tests: T1 T4 T5
1249
1250
1251 // Subregister 17 of Multireg key
1252 // R[key_17]: V(True)
1253 logic key_17_qe;
1254 logic [0:0] key_17_flds_we;
1255 1/1 assign key_17_qe = &key_17_flds_we;
Tests: T1 T4 T5
1256 prim_subreg_ext #(
1257 .DW (32)
1258 ) u_key_17 (
1259 .re (1'b0),
1260 .we (key_17_we),
1261 .wd (key_17_wd),
1262 .d (hw2reg.key[17].d),
1263 .qre (),
1264 .qe (key_17_flds_we[0]),
1265 .q (reg2hw.key[17].q),
1266 .ds (),
1267 .qs ()
1268 );
1269 1/1 assign reg2hw.key[17].qe = key_17_qe;
Tests: T1 T4 T5
1270
1271
1272 // Subregister 18 of Multireg key
1273 // R[key_18]: V(True)
1274 logic key_18_qe;
1275 logic [0:0] key_18_flds_we;
1276 1/1 assign key_18_qe = &key_18_flds_we;
Tests: T1 T4 T5
1277 prim_subreg_ext #(
1278 .DW (32)
1279 ) u_key_18 (
1280 .re (1'b0),
1281 .we (key_18_we),
1282 .wd (key_18_wd),
1283 .d (hw2reg.key[18].d),
1284 .qre (),
1285 .qe (key_18_flds_we[0]),
1286 .q (reg2hw.key[18].q),
1287 .ds (),
1288 .qs ()
1289 );
1290 1/1 assign reg2hw.key[18].qe = key_18_qe;
Tests: T1 T4 T5
1291
1292
1293 // Subregister 19 of Multireg key
1294 // R[key_19]: V(True)
1295 logic key_19_qe;
1296 logic [0:0] key_19_flds_we;
1297 1/1 assign key_19_qe = &key_19_flds_we;
Tests: T1 T4 T5
1298 prim_subreg_ext #(
1299 .DW (32)
1300 ) u_key_19 (
1301 .re (1'b0),
1302 .we (key_19_we),
1303 .wd (key_19_wd),
1304 .d (hw2reg.key[19].d),
1305 .qre (),
1306 .qe (key_19_flds_we[0]),
1307 .q (reg2hw.key[19].q),
1308 .ds (),
1309 .qs ()
1310 );
1311 1/1 assign reg2hw.key[19].qe = key_19_qe;
Tests: T1 T4 T5
1312
1313
1314 // Subregister 20 of Multireg key
1315 // R[key_20]: V(True)
1316 logic key_20_qe;
1317 logic [0:0] key_20_flds_we;
1318 1/1 assign key_20_qe = &key_20_flds_we;
Tests: T1 T4 T5
1319 prim_subreg_ext #(
1320 .DW (32)
1321 ) u_key_20 (
1322 .re (1'b0),
1323 .we (key_20_we),
1324 .wd (key_20_wd),
1325 .d (hw2reg.key[20].d),
1326 .qre (),
1327 .qe (key_20_flds_we[0]),
1328 .q (reg2hw.key[20].q),
1329 .ds (),
1330 .qs ()
1331 );
1332 1/1 assign reg2hw.key[20].qe = key_20_qe;
Tests: T1 T4 T5
1333
1334
1335 // Subregister 21 of Multireg key
1336 // R[key_21]: V(True)
1337 logic key_21_qe;
1338 logic [0:0] key_21_flds_we;
1339 1/1 assign key_21_qe = &key_21_flds_we;
Tests: T1 T4 T5
1340 prim_subreg_ext #(
1341 .DW (32)
1342 ) u_key_21 (
1343 .re (1'b0),
1344 .we (key_21_we),
1345 .wd (key_21_wd),
1346 .d (hw2reg.key[21].d),
1347 .qre (),
1348 .qe (key_21_flds_we[0]),
1349 .q (reg2hw.key[21].q),
1350 .ds (),
1351 .qs ()
1352 );
1353 1/1 assign reg2hw.key[21].qe = key_21_qe;
Tests: T1 T4 T5
1354
1355
1356 // Subregister 22 of Multireg key
1357 // R[key_22]: V(True)
1358 logic key_22_qe;
1359 logic [0:0] key_22_flds_we;
1360 1/1 assign key_22_qe = &key_22_flds_we;
Tests: T1 T4 T5
1361 prim_subreg_ext #(
1362 .DW (32)
1363 ) u_key_22 (
1364 .re (1'b0),
1365 .we (key_22_we),
1366 .wd (key_22_wd),
1367 .d (hw2reg.key[22].d),
1368 .qre (),
1369 .qe (key_22_flds_we[0]),
1370 .q (reg2hw.key[22].q),
1371 .ds (),
1372 .qs ()
1373 );
1374 1/1 assign reg2hw.key[22].qe = key_22_qe;
Tests: T1 T4 T5
1375
1376
1377 // Subregister 23 of Multireg key
1378 // R[key_23]: V(True)
1379 logic key_23_qe;
1380 logic [0:0] key_23_flds_we;
1381 1/1 assign key_23_qe = &key_23_flds_we;
Tests: T1 T4 T5
1382 prim_subreg_ext #(
1383 .DW (32)
1384 ) u_key_23 (
1385 .re (1'b0),
1386 .we (key_23_we),
1387 .wd (key_23_wd),
1388 .d (hw2reg.key[23].d),
1389 .qre (),
1390 .qe (key_23_flds_we[0]),
1391 .q (reg2hw.key[23].q),
1392 .ds (),
1393 .qs ()
1394 );
1395 1/1 assign reg2hw.key[23].qe = key_23_qe;
Tests: T1 T4 T5
1396
1397
1398 // Subregister 24 of Multireg key
1399 // R[key_24]: V(True)
1400 logic key_24_qe;
1401 logic [0:0] key_24_flds_we;
1402 1/1 assign key_24_qe = &key_24_flds_we;
Tests: T1 T4 T5
1403 prim_subreg_ext #(
1404 .DW (32)
1405 ) u_key_24 (
1406 .re (1'b0),
1407 .we (key_24_we),
1408 .wd (key_24_wd),
1409 .d (hw2reg.key[24].d),
1410 .qre (),
1411 .qe (key_24_flds_we[0]),
1412 .q (reg2hw.key[24].q),
1413 .ds (),
1414 .qs ()
1415 );
1416 1/1 assign reg2hw.key[24].qe = key_24_qe;
Tests: T1 T4 T5
1417
1418
1419 // Subregister 25 of Multireg key
1420 // R[key_25]: V(True)
1421 logic key_25_qe;
1422 logic [0:0] key_25_flds_we;
1423 1/1 assign key_25_qe = &key_25_flds_we;
Tests: T1 T4 T5
1424 prim_subreg_ext #(
1425 .DW (32)
1426 ) u_key_25 (
1427 .re (1'b0),
1428 .we (key_25_we),
1429 .wd (key_25_wd),
1430 .d (hw2reg.key[25].d),
1431 .qre (),
1432 .qe (key_25_flds_we[0]),
1433 .q (reg2hw.key[25].q),
1434 .ds (),
1435 .qs ()
1436 );
1437 1/1 assign reg2hw.key[25].qe = key_25_qe;
Tests: T1 T4 T5
1438
1439
1440 // Subregister 26 of Multireg key
1441 // R[key_26]: V(True)
1442 logic key_26_qe;
1443 logic [0:0] key_26_flds_we;
1444 1/1 assign key_26_qe = &key_26_flds_we;
Tests: T1 T4 T5
1445 prim_subreg_ext #(
1446 .DW (32)
1447 ) u_key_26 (
1448 .re (1'b0),
1449 .we (key_26_we),
1450 .wd (key_26_wd),
1451 .d (hw2reg.key[26].d),
1452 .qre (),
1453 .qe (key_26_flds_we[0]),
1454 .q (reg2hw.key[26].q),
1455 .ds (),
1456 .qs ()
1457 );
1458 1/1 assign reg2hw.key[26].qe = key_26_qe;
Tests: T1 T4 T5
1459
1460
1461 // Subregister 27 of Multireg key
1462 // R[key_27]: V(True)
1463 logic key_27_qe;
1464 logic [0:0] key_27_flds_we;
1465 1/1 assign key_27_qe = &key_27_flds_we;
Tests: T1 T4 T5
1466 prim_subreg_ext #(
1467 .DW (32)
1468 ) u_key_27 (
1469 .re (1'b0),
1470 .we (key_27_we),
1471 .wd (key_27_wd),
1472 .d (hw2reg.key[27].d),
1473 .qre (),
1474 .qe (key_27_flds_we[0]),
1475 .q (reg2hw.key[27].q),
1476 .ds (),
1477 .qs ()
1478 );
1479 1/1 assign reg2hw.key[27].qe = key_27_qe;
Tests: T1 T4 T5
1480
1481
1482 // Subregister 28 of Multireg key
1483 // R[key_28]: V(True)
1484 logic key_28_qe;
1485 logic [0:0] key_28_flds_we;
1486 1/1 assign key_28_qe = &key_28_flds_we;
Tests: T1 T4 T5
1487 prim_subreg_ext #(
1488 .DW (32)
1489 ) u_key_28 (
1490 .re (1'b0),
1491 .we (key_28_we),
1492 .wd (key_28_wd),
1493 .d (hw2reg.key[28].d),
1494 .qre (),
1495 .qe (key_28_flds_we[0]),
1496 .q (reg2hw.key[28].q),
1497 .ds (),
1498 .qs ()
1499 );
1500 1/1 assign reg2hw.key[28].qe = key_28_qe;
Tests: T1 T4 T5
1501
1502
1503 // Subregister 29 of Multireg key
1504 // R[key_29]: V(True)
1505 logic key_29_qe;
1506 logic [0:0] key_29_flds_we;
1507 1/1 assign key_29_qe = &key_29_flds_we;
Tests: T1 T4 T5
1508 prim_subreg_ext #(
1509 .DW (32)
1510 ) u_key_29 (
1511 .re (1'b0),
1512 .we (key_29_we),
1513 .wd (key_29_wd),
1514 .d (hw2reg.key[29].d),
1515 .qre (),
1516 .qe (key_29_flds_we[0]),
1517 .q (reg2hw.key[29].q),
1518 .ds (),
1519 .qs ()
1520 );
1521 1/1 assign reg2hw.key[29].qe = key_29_qe;
Tests: T1 T4 T5
1522
1523
1524 // Subregister 30 of Multireg key
1525 // R[key_30]: V(True)
1526 logic key_30_qe;
1527 logic [0:0] key_30_flds_we;
1528 1/1 assign key_30_qe = &key_30_flds_we;
Tests: T1 T4 T5
1529 prim_subreg_ext #(
1530 .DW (32)
1531 ) u_key_30 (
1532 .re (1'b0),
1533 .we (key_30_we),
1534 .wd (key_30_wd),
1535 .d (hw2reg.key[30].d),
1536 .qre (),
1537 .qe (key_30_flds_we[0]),
1538 .q (reg2hw.key[30].q),
1539 .ds (),
1540 .qs ()
1541 );
1542 1/1 assign reg2hw.key[30].qe = key_30_qe;
Tests: T1 T4 T5
1543
1544
1545 // Subregister 31 of Multireg key
1546 // R[key_31]: V(True)
1547 logic key_31_qe;
1548 logic [0:0] key_31_flds_we;
1549 1/1 assign key_31_qe = &key_31_flds_we;
Tests: T1 T4 T5
1550 prim_subreg_ext #(
1551 .DW (32)
1552 ) u_key_31 (
1553 .re (1'b0),
1554 .we (key_31_we),
1555 .wd (key_31_wd),
1556 .d (hw2reg.key[31].d),
1557 .qre (),
1558 .qe (key_31_flds_we[0]),
1559 .q (reg2hw.key[31].q),
1560 .ds (),
1561 .qs ()
1562 );
1563 1/1 assign reg2hw.key[31].qe = key_31_qe;
Tests: T1 T4 T5
1564
1565
1566 // Subregister 0 of Multireg digest
1567 // R[digest_0]: V(True)
1568 logic digest_0_qe;
1569 logic [0:0] digest_0_flds_we;
1570 1/1 assign digest_0_qe = &digest_0_flds_we;
Tests: T4 T7 T8
1571 prim_subreg_ext #(
1572 .DW (32)
1573 ) u_digest_0 (
1574 .re (digest_0_re),
1575 .we (digest_0_we),
1576 .wd (digest_0_wd),
1577 .d (hw2reg.digest[0].d),
1578 .qre (),
1579 .qe (digest_0_flds_we[0]),
1580 .q (reg2hw.digest[0].q),
1581 .ds (),
1582 .qs (digest_0_qs)
1583 );
1584 1/1 assign reg2hw.digest[0].qe = digest_0_qe;
Tests: T4 T7 T8
1585
1586
1587 // Subregister 1 of Multireg digest
1588 // R[digest_1]: V(True)
1589 logic digest_1_qe;
1590 logic [0:0] digest_1_flds_we;
1591 1/1 assign digest_1_qe = &digest_1_flds_we;
Tests: T4 T7 T8
1592 prim_subreg_ext #(
1593 .DW (32)
1594 ) u_digest_1 (
1595 .re (digest_1_re),
1596 .we (digest_1_we),
1597 .wd (digest_1_wd),
1598 .d (hw2reg.digest[1].d),
1599 .qre (),
1600 .qe (digest_1_flds_we[0]),
1601 .q (reg2hw.digest[1].q),
1602 .ds (),
1603 .qs (digest_1_qs)
1604 );
1605 1/1 assign reg2hw.digest[1].qe = digest_1_qe;
Tests: T4 T7 T8
1606
1607
1608 // Subregister 2 of Multireg digest
1609 // R[digest_2]: V(True)
1610 logic digest_2_qe;
1611 logic [0:0] digest_2_flds_we;
1612 1/1 assign digest_2_qe = &digest_2_flds_we;
Tests: T4 T7 T8
1613 prim_subreg_ext #(
1614 .DW (32)
1615 ) u_digest_2 (
1616 .re (digest_2_re),
1617 .we (digest_2_we),
1618 .wd (digest_2_wd),
1619 .d (hw2reg.digest[2].d),
1620 .qre (),
1621 .qe (digest_2_flds_we[0]),
1622 .q (reg2hw.digest[2].q),
1623 .ds (),
1624 .qs (digest_2_qs)
1625 );
1626 1/1 assign reg2hw.digest[2].qe = digest_2_qe;
Tests: T4 T7 T8
1627
1628
1629 // Subregister 3 of Multireg digest
1630 // R[digest_3]: V(True)
1631 logic digest_3_qe;
1632 logic [0:0] digest_3_flds_we;
1633 1/1 assign digest_3_qe = &digest_3_flds_we;
Tests: T4 T7 T8
1634 prim_subreg_ext #(
1635 .DW (32)
1636 ) u_digest_3 (
1637 .re (digest_3_re),
1638 .we (digest_3_we),
1639 .wd (digest_3_wd),
1640 .d (hw2reg.digest[3].d),
1641 .qre (),
1642 .qe (digest_3_flds_we[0]),
1643 .q (reg2hw.digest[3].q),
1644 .ds (),
1645 .qs (digest_3_qs)
1646 );
1647 1/1 assign reg2hw.digest[3].qe = digest_3_qe;
Tests: T4 T7 T8
1648
1649
1650 // Subregister 4 of Multireg digest
1651 // R[digest_4]: V(True)
1652 logic digest_4_qe;
1653 logic [0:0] digest_4_flds_we;
1654 1/1 assign digest_4_qe = &digest_4_flds_we;
Tests: T4 T7 T8
1655 prim_subreg_ext #(
1656 .DW (32)
1657 ) u_digest_4 (
1658 .re (digest_4_re),
1659 .we (digest_4_we),
1660 .wd (digest_4_wd),
1661 .d (hw2reg.digest[4].d),
1662 .qre (),
1663 .qe (digest_4_flds_we[0]),
1664 .q (reg2hw.digest[4].q),
1665 .ds (),
1666 .qs (digest_4_qs)
1667 );
1668 1/1 assign reg2hw.digest[4].qe = digest_4_qe;
Tests: T4 T7 T8
1669
1670
1671 // Subregister 5 of Multireg digest
1672 // R[digest_5]: V(True)
1673 logic digest_5_qe;
1674 logic [0:0] digest_5_flds_we;
1675 1/1 assign digest_5_qe = &digest_5_flds_we;
Tests: T4 T7 T8
1676 prim_subreg_ext #(
1677 .DW (32)
1678 ) u_digest_5 (
1679 .re (digest_5_re),
1680 .we (digest_5_we),
1681 .wd (digest_5_wd),
1682 .d (hw2reg.digest[5].d),
1683 .qre (),
1684 .qe (digest_5_flds_we[0]),
1685 .q (reg2hw.digest[5].q),
1686 .ds (),
1687 .qs (digest_5_qs)
1688 );
1689 1/1 assign reg2hw.digest[5].qe = digest_5_qe;
Tests: T4 T7 T8
1690
1691
1692 // Subregister 6 of Multireg digest
1693 // R[digest_6]: V(True)
1694 logic digest_6_qe;
1695 logic [0:0] digest_6_flds_we;
1696 1/1 assign digest_6_qe = &digest_6_flds_we;
Tests: T4 T7 T8
1697 prim_subreg_ext #(
1698 .DW (32)
1699 ) u_digest_6 (
1700 .re (digest_6_re),
1701 .we (digest_6_we),
1702 .wd (digest_6_wd),
1703 .d (hw2reg.digest[6].d),
1704 .qre (),
1705 .qe (digest_6_flds_we[0]),
1706 .q (reg2hw.digest[6].q),
1707 .ds (),
1708 .qs (digest_6_qs)
1709 );
1710 1/1 assign reg2hw.digest[6].qe = digest_6_qe;
Tests: T4 T7 T8
1711
1712
1713 // Subregister 7 of Multireg digest
1714 // R[digest_7]: V(True)
1715 logic digest_7_qe;
1716 logic [0:0] digest_7_flds_we;
1717 1/1 assign digest_7_qe = &digest_7_flds_we;
Tests: T4 T7 T8
1718 prim_subreg_ext #(
1719 .DW (32)
1720 ) u_digest_7 (
1721 .re (digest_7_re),
1722 .we (digest_7_we),
1723 .wd (digest_7_wd),
1724 .d (hw2reg.digest[7].d),
1725 .qre (),
1726 .qe (digest_7_flds_we[0]),
1727 .q (reg2hw.digest[7].q),
1728 .ds (),
1729 .qs (digest_7_qs)
1730 );
1731 1/1 assign reg2hw.digest[7].qe = digest_7_qe;
Tests: T4 T7 T8
1732
1733
1734 // Subregister 8 of Multireg digest
1735 // R[digest_8]: V(True)
1736 logic digest_8_qe;
1737 logic [0:0] digest_8_flds_we;
1738 1/1 assign digest_8_qe = &digest_8_flds_we;
Tests: T4 T7 T8
1739 prim_subreg_ext #(
1740 .DW (32)
1741 ) u_digest_8 (
1742 .re (digest_8_re),
1743 .we (digest_8_we),
1744 .wd (digest_8_wd),
1745 .d (hw2reg.digest[8].d),
1746 .qre (),
1747 .qe (digest_8_flds_we[0]),
1748 .q (reg2hw.digest[8].q),
1749 .ds (),
1750 .qs (digest_8_qs)
1751 );
1752 1/1 assign reg2hw.digest[8].qe = digest_8_qe;
Tests: T4 T7 T8
1753
1754
1755 // Subregister 9 of Multireg digest
1756 // R[digest_9]: V(True)
1757 logic digest_9_qe;
1758 logic [0:0] digest_9_flds_we;
1759 1/1 assign digest_9_qe = &digest_9_flds_we;
Tests: T4 T7 T8
1760 prim_subreg_ext #(
1761 .DW (32)
1762 ) u_digest_9 (
1763 .re (digest_9_re),
1764 .we (digest_9_we),
1765 .wd (digest_9_wd),
1766 .d (hw2reg.digest[9].d),
1767 .qre (),
1768 .qe (digest_9_flds_we[0]),
1769 .q (reg2hw.digest[9].q),
1770 .ds (),
1771 .qs (digest_9_qs)
1772 );
1773 1/1 assign reg2hw.digest[9].qe = digest_9_qe;
Tests: T4 T7 T8
1774
1775
1776 // Subregister 10 of Multireg digest
1777 // R[digest_10]: V(True)
1778 logic digest_10_qe;
1779 logic [0:0] digest_10_flds_we;
1780 1/1 assign digest_10_qe = &digest_10_flds_we;
Tests: T4 T7 T8
1781 prim_subreg_ext #(
1782 .DW (32)
1783 ) u_digest_10 (
1784 .re (digest_10_re),
1785 .we (digest_10_we),
1786 .wd (digest_10_wd),
1787 .d (hw2reg.digest[10].d),
1788 .qre (),
1789 .qe (digest_10_flds_we[0]),
1790 .q (reg2hw.digest[10].q),
1791 .ds (),
1792 .qs (digest_10_qs)
1793 );
1794 1/1 assign reg2hw.digest[10].qe = digest_10_qe;
Tests: T4 T7 T8
1795
1796
1797 // Subregister 11 of Multireg digest
1798 // R[digest_11]: V(True)
1799 logic digest_11_qe;
1800 logic [0:0] digest_11_flds_we;
1801 1/1 assign digest_11_qe = &digest_11_flds_we;
Tests: T4 T7 T8
1802 prim_subreg_ext #(
1803 .DW (32)
1804 ) u_digest_11 (
1805 .re (digest_11_re),
1806 .we (digest_11_we),
1807 .wd (digest_11_wd),
1808 .d (hw2reg.digest[11].d),
1809 .qre (),
1810 .qe (digest_11_flds_we[0]),
1811 .q (reg2hw.digest[11].q),
1812 .ds (),
1813 .qs (digest_11_qs)
1814 );
1815 1/1 assign reg2hw.digest[11].qe = digest_11_qe;
Tests: T4 T7 T8
1816
1817
1818 // Subregister 12 of Multireg digest
1819 // R[digest_12]: V(True)
1820 logic digest_12_qe;
1821 logic [0:0] digest_12_flds_we;
1822 1/1 assign digest_12_qe = &digest_12_flds_we;
Tests: T4 T7 T8
1823 prim_subreg_ext #(
1824 .DW (32)
1825 ) u_digest_12 (
1826 .re (digest_12_re),
1827 .we (digest_12_we),
1828 .wd (digest_12_wd),
1829 .d (hw2reg.digest[12].d),
1830 .qre (),
1831 .qe (digest_12_flds_we[0]),
1832 .q (reg2hw.digest[12].q),
1833 .ds (),
1834 .qs (digest_12_qs)
1835 );
1836 1/1 assign reg2hw.digest[12].qe = digest_12_qe;
Tests: T4 T7 T8
1837
1838
1839 // Subregister 13 of Multireg digest
1840 // R[digest_13]: V(True)
1841 logic digest_13_qe;
1842 logic [0:0] digest_13_flds_we;
1843 1/1 assign digest_13_qe = &digest_13_flds_we;
Tests: T4 T7 T8
1844 prim_subreg_ext #(
1845 .DW (32)
1846 ) u_digest_13 (
1847 .re (digest_13_re),
1848 .we (digest_13_we),
1849 .wd (digest_13_wd),
1850 .d (hw2reg.digest[13].d),
1851 .qre (),
1852 .qe (digest_13_flds_we[0]),
1853 .q (reg2hw.digest[13].q),
1854 .ds (),
1855 .qs (digest_13_qs)
1856 );
1857 1/1 assign reg2hw.digest[13].qe = digest_13_qe;
Tests: T4 T7 T8
1858
1859
1860 // Subregister 14 of Multireg digest
1861 // R[digest_14]: V(True)
1862 logic digest_14_qe;
1863 logic [0:0] digest_14_flds_we;
1864 1/1 assign digest_14_qe = &digest_14_flds_we;
Tests: T4 T7 T8
1865 prim_subreg_ext #(
1866 .DW (32)
1867 ) u_digest_14 (
1868 .re (digest_14_re),
1869 .we (digest_14_we),
1870 .wd (digest_14_wd),
1871 .d (hw2reg.digest[14].d),
1872 .qre (),
1873 .qe (digest_14_flds_we[0]),
1874 .q (reg2hw.digest[14].q),
1875 .ds (),
1876 .qs (digest_14_qs)
1877 );
1878 1/1 assign reg2hw.digest[14].qe = digest_14_qe;
Tests: T4 T7 T8
1879
1880
1881 // Subregister 15 of Multireg digest
1882 // R[digest_15]: V(True)
1883 logic digest_15_qe;
1884 logic [0:0] digest_15_flds_we;
1885 1/1 assign digest_15_qe = &digest_15_flds_we;
Tests: T4 T7 T8
1886 prim_subreg_ext #(
1887 .DW (32)
1888 ) u_digest_15 (
1889 .re (digest_15_re),
1890 .we (digest_15_we),
1891 .wd (digest_15_wd),
1892 .d (hw2reg.digest[15].d),
1893 .qre (),
1894 .qe (digest_15_flds_we[0]),
1895 .q (reg2hw.digest[15].q),
1896 .ds (),
1897 .qs (digest_15_qs)
1898 );
1899 1/1 assign reg2hw.digest[15].qe = digest_15_qe;
Tests: T4 T7 T8
1900
1901
1902 // R[msg_length_lower]: V(True)
1903 logic msg_length_lower_qe;
1904 logic [0:0] msg_length_lower_flds_we;
1905 1/1 assign msg_length_lower_qe = &msg_length_lower_flds_we;
Tests: T4 T7 T8
1906 prim_subreg_ext #(
1907 .DW (32)
1908 ) u_msg_length_lower (
1909 .re (msg_length_lower_re),
1910 .we (msg_length_lower_we),
1911 .wd (msg_length_lower_wd),
1912 .d (hw2reg.msg_length_lower.d),
1913 .qre (),
1914 .qe (msg_length_lower_flds_we[0]),
1915 .q (reg2hw.msg_length_lower.q),
1916 .ds (),
1917 .qs (msg_length_lower_qs)
1918 );
1919 1/1 assign reg2hw.msg_length_lower.qe = msg_length_lower_qe;
Tests: T4 T7 T8
1920
1921
1922 // R[msg_length_upper]: V(True)
1923 logic msg_length_upper_qe;
1924 logic [0:0] msg_length_upper_flds_we;
1925 1/1 assign msg_length_upper_qe = &msg_length_upper_flds_we;
Tests: T4 T7 T8
1926 prim_subreg_ext #(
1927 .DW (32)
1928 ) u_msg_length_upper (
1929 .re (msg_length_upper_re),
1930 .we (msg_length_upper_we),
1931 .wd (msg_length_upper_wd),
1932 .d (hw2reg.msg_length_upper.d),
1933 .qre (),
1934 .qe (msg_length_upper_flds_we[0]),
1935 .q (reg2hw.msg_length_upper.q),
1936 .ds (),
1937 .qs (msg_length_upper_qs)
1938 );
1939 1/1 assign reg2hw.msg_length_upper.qe = msg_length_upper_qe;
Tests: T4 T7 T8
1940
1941
1942
1943 logic [58:0] addr_hit;
1944 always_comb begin
1945 1/1 addr_hit = '0;
Tests: T1 T2 T3
1946 1/1 addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1947 1/1 addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
1948 1/1 addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1949 1/1 addr_hit[ 3] = (reg_addr == HMAC_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1950 1/1 addr_hit[ 4] = (reg_addr == HMAC_CFG_OFFSET);
Tests: T1 T2 T3
1951 1/1 addr_hit[ 5] = (reg_addr == HMAC_CMD_OFFSET);
Tests: T1 T2 T3
1952 1/1 addr_hit[ 6] = (reg_addr == HMAC_STATUS_OFFSET);
Tests: T1 T2 T3
1953 1/1 addr_hit[ 7] = (reg_addr == HMAC_ERR_CODE_OFFSET);
Tests: T1 T2 T3
1954 1/1 addr_hit[ 8] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
Tests: T1 T2 T3
1955 1/1 addr_hit[ 9] = (reg_addr == HMAC_KEY_0_OFFSET);
Tests: T1 T2 T3
1956 1/1 addr_hit[10] = (reg_addr == HMAC_KEY_1_OFFSET);
Tests: T1 T2 T3
1957 1/1 addr_hit[11] = (reg_addr == HMAC_KEY_2_OFFSET);
Tests: T1 T2 T3
1958 1/1 addr_hit[12] = (reg_addr == HMAC_KEY_3_OFFSET);
Tests: T1 T2 T3
1959 1/1 addr_hit[13] = (reg_addr == HMAC_KEY_4_OFFSET);
Tests: T1 T2 T3
1960 1/1 addr_hit[14] = (reg_addr == HMAC_KEY_5_OFFSET);
Tests: T1 T2 T3
1961 1/1 addr_hit[15] = (reg_addr == HMAC_KEY_6_OFFSET);
Tests: T1 T2 T3
1962 1/1 addr_hit[16] = (reg_addr == HMAC_KEY_7_OFFSET);
Tests: T1 T2 T3
1963 1/1 addr_hit[17] = (reg_addr == HMAC_KEY_8_OFFSET);
Tests: T1 T2 T3
1964 1/1 addr_hit[18] = (reg_addr == HMAC_KEY_9_OFFSET);
Tests: T1 T2 T3
1965 1/1 addr_hit[19] = (reg_addr == HMAC_KEY_10_OFFSET);
Tests: T1 T2 T3
1966 1/1 addr_hit[20] = (reg_addr == HMAC_KEY_11_OFFSET);
Tests: T1 T2 T3
1967 1/1 addr_hit[21] = (reg_addr == HMAC_KEY_12_OFFSET);
Tests: T1 T2 T3
1968 1/1 addr_hit[22] = (reg_addr == HMAC_KEY_13_OFFSET);
Tests: T1 T2 T3
1969 1/1 addr_hit[23] = (reg_addr == HMAC_KEY_14_OFFSET);
Tests: T1 T2 T3
1970 1/1 addr_hit[24] = (reg_addr == HMAC_KEY_15_OFFSET);
Tests: T1 T2 T3
1971 1/1 addr_hit[25] = (reg_addr == HMAC_KEY_16_OFFSET);
Tests: T1 T2 T3
1972 1/1 addr_hit[26] = (reg_addr == HMAC_KEY_17_OFFSET);
Tests: T1 T2 T3
1973 1/1 addr_hit[27] = (reg_addr == HMAC_KEY_18_OFFSET);
Tests: T1 T2 T3
1974 1/1 addr_hit[28] = (reg_addr == HMAC_KEY_19_OFFSET);
Tests: T1 T2 T3
1975 1/1 addr_hit[29] = (reg_addr == HMAC_KEY_20_OFFSET);
Tests: T1 T2 T3
1976 1/1 addr_hit[30] = (reg_addr == HMAC_KEY_21_OFFSET);
Tests: T1 T2 T3
1977 1/1 addr_hit[31] = (reg_addr == HMAC_KEY_22_OFFSET);
Tests: T1 T2 T3
1978 1/1 addr_hit[32] = (reg_addr == HMAC_KEY_23_OFFSET);
Tests: T1 T2 T3
1979 1/1 addr_hit[33] = (reg_addr == HMAC_KEY_24_OFFSET);
Tests: T1 T2 T3
1980 1/1 addr_hit[34] = (reg_addr == HMAC_KEY_25_OFFSET);
Tests: T1 T2 T3
1981 1/1 addr_hit[35] = (reg_addr == HMAC_KEY_26_OFFSET);
Tests: T1 T2 T3
1982 1/1 addr_hit[36] = (reg_addr == HMAC_KEY_27_OFFSET);
Tests: T1 T2 T3
1983 1/1 addr_hit[37] = (reg_addr == HMAC_KEY_28_OFFSET);
Tests: T1 T2 T3
1984 1/1 addr_hit[38] = (reg_addr == HMAC_KEY_29_OFFSET);
Tests: T1 T2 T3
1985 1/1 addr_hit[39] = (reg_addr == HMAC_KEY_30_OFFSET);
Tests: T1 T2 T3
1986 1/1 addr_hit[40] = (reg_addr == HMAC_KEY_31_OFFSET);
Tests: T1 T2 T3
1987 1/1 addr_hit[41] = (reg_addr == HMAC_DIGEST_0_OFFSET);
Tests: T1 T2 T3
1988 1/1 addr_hit[42] = (reg_addr == HMAC_DIGEST_1_OFFSET);
Tests: T1 T2 T3
1989 1/1 addr_hit[43] = (reg_addr == HMAC_DIGEST_2_OFFSET);
Tests: T1 T2 T3
1990 1/1 addr_hit[44] = (reg_addr == HMAC_DIGEST_3_OFFSET);
Tests: T1 T2 T3
1991 1/1 addr_hit[45] = (reg_addr == HMAC_DIGEST_4_OFFSET);
Tests: T1 T2 T3
1992 1/1 addr_hit[46] = (reg_addr == HMAC_DIGEST_5_OFFSET);
Tests: T1 T2 T3
1993 1/1 addr_hit[47] = (reg_addr == HMAC_DIGEST_6_OFFSET);
Tests: T1 T2 T3
1994 1/1 addr_hit[48] = (reg_addr == HMAC_DIGEST_7_OFFSET);
Tests: T1 T2 T3
1995 1/1 addr_hit[49] = (reg_addr == HMAC_DIGEST_8_OFFSET);
Tests: T1 T2 T3
1996 1/1 addr_hit[50] = (reg_addr == HMAC_DIGEST_9_OFFSET);
Tests: T1 T2 T3
1997 1/1 addr_hit[51] = (reg_addr == HMAC_DIGEST_10_OFFSET);
Tests: T1 T2 T3
1998 1/1 addr_hit[52] = (reg_addr == HMAC_DIGEST_11_OFFSET);
Tests: T1 T2 T3
1999 1/1 addr_hit[53] = (reg_addr == HMAC_DIGEST_12_OFFSET);
Tests: T1 T2 T3
2000 1/1 addr_hit[54] = (reg_addr == HMAC_DIGEST_13_OFFSET);
Tests: T1 T2 T3
2001 1/1 addr_hit[55] = (reg_addr == HMAC_DIGEST_14_OFFSET);
Tests: T1 T2 T3
2002 1/1 addr_hit[56] = (reg_addr == HMAC_DIGEST_15_OFFSET);
Tests: T1 T2 T3
2003 1/1 addr_hit[57] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
Tests: T1 T2 T3
2004 1/1 addr_hit[58] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
Tests: T1 T2 T3
2005 end
2006
2007 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
2008
2009 // Check sub-word write is permitted
2010 always_comb begin
2011 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
2012 ((addr_hit[ 0] & (|(HMAC_PERMIT[ 0] & ~reg_be))) |
2013 (addr_hit[ 1] & (|(HMAC_PERMIT[ 1] & ~reg_be))) |
2014 (addr_hit[ 2] & (|(HMAC_PERMIT[ 2] & ~reg_be))) |
2015 (addr_hit[ 3] & (|(HMAC_PERMIT[ 3] & ~reg_be))) |
2016 (addr_hit[ 4] & (|(HMAC_PERMIT[ 4] & ~reg_be))) |
2017 (addr_hit[ 5] & (|(HMAC_PERMIT[ 5] & ~reg_be))) |
2018 (addr_hit[ 6] & (|(HMAC_PERMIT[ 6] & ~reg_be))) |
2019 (addr_hit[ 7] & (|(HMAC_PERMIT[ 7] & ~reg_be))) |
2020 (addr_hit[ 8] & (|(HMAC_PERMIT[ 8] & ~reg_be))) |
2021 (addr_hit[ 9] & (|(HMAC_PERMIT[ 9] & ~reg_be))) |
2022 (addr_hit[10] & (|(HMAC_PERMIT[10] & ~reg_be))) |
2023 (addr_hit[11] & (|(HMAC_PERMIT[11] & ~reg_be))) |
2024 (addr_hit[12] & (|(HMAC_PERMIT[12] & ~reg_be))) |
2025 (addr_hit[13] & (|(HMAC_PERMIT[13] & ~reg_be))) |
2026 (addr_hit[14] & (|(HMAC_PERMIT[14] & ~reg_be))) |
2027 (addr_hit[15] & (|(HMAC_PERMIT[15] & ~reg_be))) |
2028 (addr_hit[16] & (|(HMAC_PERMIT[16] & ~reg_be))) |
2029 (addr_hit[17] & (|(HMAC_PERMIT[17] & ~reg_be))) |
2030 (addr_hit[18] & (|(HMAC_PERMIT[18] & ~reg_be))) |
2031 (addr_hit[19] & (|(HMAC_PERMIT[19] & ~reg_be))) |
2032 (addr_hit[20] & (|(HMAC_PERMIT[20] & ~reg_be))) |
2033 (addr_hit[21] & (|(HMAC_PERMIT[21] & ~reg_be))) |
2034 (addr_hit[22] & (|(HMAC_PERMIT[22] & ~reg_be))) |
2035 (addr_hit[23] & (|(HMAC_PERMIT[23] & ~reg_be))) |
2036 (addr_hit[24] & (|(HMAC_PERMIT[24] & ~reg_be))) |
2037 (addr_hit[25] & (|(HMAC_PERMIT[25] & ~reg_be))) |
2038 (addr_hit[26] & (|(HMAC_PERMIT[26] & ~reg_be))) |
2039 (addr_hit[27] & (|(HMAC_PERMIT[27] & ~reg_be))) |
2040 (addr_hit[28] & (|(HMAC_PERMIT[28] & ~reg_be))) |
2041 (addr_hit[29] & (|(HMAC_PERMIT[29] & ~reg_be))) |
2042 (addr_hit[30] & (|(HMAC_PERMIT[30] & ~reg_be))) |
2043 (addr_hit[31] & (|(HMAC_PERMIT[31] & ~reg_be))) |
2044 (addr_hit[32] & (|(HMAC_PERMIT[32] & ~reg_be))) |
2045 (addr_hit[33] & (|(HMAC_PERMIT[33] & ~reg_be))) |
2046 (addr_hit[34] & (|(HMAC_PERMIT[34] & ~reg_be))) |
2047 (addr_hit[35] & (|(HMAC_PERMIT[35] & ~reg_be))) |
2048 (addr_hit[36] & (|(HMAC_PERMIT[36] & ~reg_be))) |
2049 (addr_hit[37] & (|(HMAC_PERMIT[37] & ~reg_be))) |
2050 (addr_hit[38] & (|(HMAC_PERMIT[38] & ~reg_be))) |
2051 (addr_hit[39] & (|(HMAC_PERMIT[39] & ~reg_be))) |
2052 (addr_hit[40] & (|(HMAC_PERMIT[40] & ~reg_be))) |
2053 (addr_hit[41] & (|(HMAC_PERMIT[41] & ~reg_be))) |
2054 (addr_hit[42] & (|(HMAC_PERMIT[42] & ~reg_be))) |
2055 (addr_hit[43] & (|(HMAC_PERMIT[43] & ~reg_be))) |
2056 (addr_hit[44] & (|(HMAC_PERMIT[44] & ~reg_be))) |
2057 (addr_hit[45] & (|(HMAC_PERMIT[45] & ~reg_be))) |
2058 (addr_hit[46] & (|(HMAC_PERMIT[46] & ~reg_be))) |
2059 (addr_hit[47] & (|(HMAC_PERMIT[47] & ~reg_be))) |
2060 (addr_hit[48] & (|(HMAC_PERMIT[48] & ~reg_be))) |
2061 (addr_hit[49] & (|(HMAC_PERMIT[49] & ~reg_be))) |
2062 (addr_hit[50] & (|(HMAC_PERMIT[50] & ~reg_be))) |
2063 (addr_hit[51] & (|(HMAC_PERMIT[51] & ~reg_be))) |
2064 (addr_hit[52] & (|(HMAC_PERMIT[52] & ~reg_be))) |
2065 (addr_hit[53] & (|(HMAC_PERMIT[53] & ~reg_be))) |
2066 (addr_hit[54] & (|(HMAC_PERMIT[54] & ~reg_be))) |
2067 (addr_hit[55] & (|(HMAC_PERMIT[55] & ~reg_be))) |
2068 (addr_hit[56] & (|(HMAC_PERMIT[56] & ~reg_be))) |
2069 (addr_hit[57] & (|(HMAC_PERMIT[57] & ~reg_be))) |
2070 (addr_hit[58] & (|(HMAC_PERMIT[58] & ~reg_be)))));
2071 end
2072
2073 // Generate write-enables
2074 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
2075
2076 1/1 assign intr_state_hmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2077
2078 1/1 assign intr_state_hmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2079 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
2080
2081 1/1 assign intr_enable_hmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2082
2083 1/1 assign intr_enable_fifo_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
2084
2085 1/1 assign intr_enable_hmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2086 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
2087
2088 1/1 assign intr_test_hmac_done_wd = reg_wdata[0];
Tests: T1 T2 T3
2089
2090 1/1 assign intr_test_fifo_empty_wd = reg_wdata[1];
Tests: T1 T2 T3
2091
2092 1/1 assign intr_test_hmac_err_wd = reg_wdata[2];
Tests: T1 T2 T3
2093 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
2094
2095 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
2096 1/1 assign cfg_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
2097 1/1 assign cfg_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
2098
2099 1/1 assign cfg_hmac_en_wd = reg_wdata[0];
Tests: T1 T2 T3
2100
2101 1/1 assign cfg_sha_en_wd = reg_wdata[1];
Tests: T1 T2 T3
2102
2103 1/1 assign cfg_endian_swap_wd = reg_wdata[2];
Tests: T1 T2 T3
2104
2105 1/1 assign cfg_digest_swap_wd = reg_wdata[3];
Tests: T1 T2 T3
2106
2107 1/1 assign cfg_key_swap_wd = reg_wdata[4];
Tests: T1 T2 T3
2108
2109 1/1 assign cfg_digest_size_wd = reg_wdata[8:5];
Tests: T1 T2 T3
2110
2111 1/1 assign cfg_key_length_wd = reg_wdata[14:9];
Tests: T1 T2 T3
2112 1/1 assign cmd_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
2113
2114 1/1 assign cmd_hash_start_wd = reg_wdata[0];
Tests: T1 T2 T3
2115
2116 1/1 assign cmd_hash_process_wd = reg_wdata[1];
Tests: T1 T2 T3
2117
2118 1/1 assign cmd_hash_stop_wd = reg_wdata[2];
Tests: T1 T2 T3
2119
2120 1/1 assign cmd_hash_continue_wd = reg_wdata[3];
Tests: T1 T2 T3
2121 1/1 assign status_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
2122 1/1 assign wipe_secret_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
2123
2124 1/1 assign wipe_secret_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2125 1/1 assign key_0_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
2126
2127 1/1 assign key_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2128 1/1 assign key_1_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
2129
2130 1/1 assign key_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2131 1/1 assign key_2_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
2132
2133 1/1 assign key_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2134 1/1 assign key_3_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
2135
2136 1/1 assign key_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2137 1/1 assign key_4_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
2138
2139 1/1 assign key_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2140 1/1 assign key_5_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
2141
2142 1/1 assign key_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2143 1/1 assign key_6_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
2144
2145 1/1 assign key_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2146 1/1 assign key_7_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
2147
2148 1/1 assign key_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2149 1/1 assign key_8_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
2150
2151 1/1 assign key_8_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2152 1/1 assign key_9_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
2153
2154 1/1 assign key_9_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2155 1/1 assign key_10_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
2156
2157 1/1 assign key_10_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2158 1/1 assign key_11_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
2159
2160 1/1 assign key_11_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2161 1/1 assign key_12_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
2162
2163 1/1 assign key_12_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2164 1/1 assign key_13_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
2165
2166 1/1 assign key_13_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2167 1/1 assign key_14_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
2168
2169 1/1 assign key_14_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2170 1/1 assign key_15_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
2171
2172 1/1 assign key_15_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2173 1/1 assign key_16_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
2174
2175 1/1 assign key_16_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2176 1/1 assign key_17_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
2177
2178 1/1 assign key_17_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2179 1/1 assign key_18_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
2180
2181 1/1 assign key_18_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2182 1/1 assign key_19_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
2183
2184 1/1 assign key_19_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2185 1/1 assign key_20_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
2186
2187 1/1 assign key_20_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2188 1/1 assign key_21_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
2189
2190 1/1 assign key_21_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2191 1/1 assign key_22_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
2192
2193 1/1 assign key_22_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2194 1/1 assign key_23_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
2195
2196 1/1 assign key_23_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2197 1/1 assign key_24_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
2198
2199 1/1 assign key_24_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2200 1/1 assign key_25_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
2201
2202 1/1 assign key_25_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2203 1/1 assign key_26_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
2204
2205 1/1 assign key_26_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2206 1/1 assign key_27_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
2207
2208 1/1 assign key_27_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2209 1/1 assign key_28_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
2210
2211 1/1 assign key_28_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2212 1/1 assign key_29_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
2213
2214 1/1 assign key_29_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2215 1/1 assign key_30_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
2216
2217 1/1 assign key_30_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2218 1/1 assign key_31_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
2219
2220 1/1 assign key_31_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2221 1/1 assign digest_0_re = addr_hit[41] & reg_re & !reg_error;
Tests: T1 T2 T3
2222 1/1 assign digest_0_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
2223
2224 1/1 assign digest_0_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2225 1/1 assign digest_1_re = addr_hit[42] & reg_re & !reg_error;
Tests: T1 T2 T3
2226 1/1 assign digest_1_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
2227
2228 1/1 assign digest_1_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2229 1/1 assign digest_2_re = addr_hit[43] & reg_re & !reg_error;
Tests: T1 T2 T3
2230 1/1 assign digest_2_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T3
2231
2232 1/1 assign digest_2_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2233 1/1 assign digest_3_re = addr_hit[44] & reg_re & !reg_error;
Tests: T1 T2 T3
2234 1/1 assign digest_3_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T3
2235
2236 1/1 assign digest_3_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2237 1/1 assign digest_4_re = addr_hit[45] & reg_re & !reg_error;
Tests: T1 T2 T3
2238 1/1 assign digest_4_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T3
2239
2240 1/1 assign digest_4_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2241 1/1 assign digest_5_re = addr_hit[46] & reg_re & !reg_error;
Tests: T1 T2 T3
2242 1/1 assign digest_5_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T3
2243
2244 1/1 assign digest_5_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2245 1/1 assign digest_6_re = addr_hit[47] & reg_re & !reg_error;
Tests: T1 T2 T3
2246 1/1 assign digest_6_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T3
2247
2248 1/1 assign digest_6_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2249 1/1 assign digest_7_re = addr_hit[48] & reg_re & !reg_error;
Tests: T1 T2 T3
2250 1/1 assign digest_7_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T3
2251
2252 1/1 assign digest_7_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2253 1/1 assign digest_8_re = addr_hit[49] & reg_re & !reg_error;
Tests: T1 T2 T3
2254 1/1 assign digest_8_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T3
2255
2256 1/1 assign digest_8_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2257 1/1 assign digest_9_re = addr_hit[50] & reg_re & !reg_error;
Tests: T1 T2 T3
2258 1/1 assign digest_9_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T3
2259
2260 1/1 assign digest_9_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2261 1/1 assign digest_10_re = addr_hit[51] & reg_re & !reg_error;
Tests: T1 T2 T3
2262 1/1 assign digest_10_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T3
2263
2264 1/1 assign digest_10_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2265 1/1 assign digest_11_re = addr_hit[52] & reg_re & !reg_error;
Tests: T1 T2 T3
2266 1/1 assign digest_11_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T3
2267
2268 1/1 assign digest_11_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2269 1/1 assign digest_12_re = addr_hit[53] & reg_re & !reg_error;
Tests: T1 T2 T3
2270 1/1 assign digest_12_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T3
2271
2272 1/1 assign digest_12_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2273 1/1 assign digest_13_re = addr_hit[54] & reg_re & !reg_error;
Tests: T1 T2 T3
2274 1/1 assign digest_13_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T3
2275
2276 1/1 assign digest_13_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2277 1/1 assign digest_14_re = addr_hit[55] & reg_re & !reg_error;
Tests: T1 T2 T3
2278 1/1 assign digest_14_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T3
2279
2280 1/1 assign digest_14_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2281 1/1 assign digest_15_re = addr_hit[56] & reg_re & !reg_error;
Tests: T1 T2 T3
2282 1/1 assign digest_15_we = addr_hit[56] & reg_we & !reg_error;
Tests: T1 T2 T3
2283
2284 1/1 assign digest_15_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2285 1/1 assign msg_length_lower_re = addr_hit[57] & reg_re & !reg_error;
Tests: T1 T2 T3
2286 1/1 assign msg_length_lower_we = addr_hit[57] & reg_we & !reg_error;
Tests: T1 T2 T3
2287
2288 1/1 assign msg_length_lower_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2289 1/1 assign msg_length_upper_re = addr_hit[58] & reg_re & !reg_error;
Tests: T1 T2 T3
2290 1/1 assign msg_length_upper_we = addr_hit[58] & reg_we & !reg_error;
Tests: T1 T2 T3
2291
2292 1/1 assign msg_length_upper_wd = reg_wdata[31:0];
Tests: T1 T2 T3
2293
2294 // Assign write-enables to checker logic vector.
2295 always_comb begin
2296 1/1 reg_we_check = '0;
Tests: T1 T2 T4
2297 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T4
2298 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T4
2299 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T4
2300 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T4
2301 1/1 reg_we_check[4] = cfg_we;
Tests: T1 T2 T4
2302 1/1 reg_we_check[5] = cmd_we;
Tests: T1 T2 T4
2303 1/1 reg_we_check[6] = 1'b0;
Tests: T1 T2 T4
2304 1/1 reg_we_check[7] = 1'b0;
Tests: T1 T2 T4
2305 1/1 reg_we_check[8] = wipe_secret_we;
Tests: T1 T2 T4
2306 1/1 reg_we_check[9] = key_0_we;
Tests: T1 T2 T4
2307 1/1 reg_we_check[10] = key_1_we;
Tests: T1 T2 T4
2308 1/1 reg_we_check[11] = key_2_we;
Tests: T1 T2 T4
2309 1/1 reg_we_check[12] = key_3_we;
Tests: T1 T2 T4
2310 1/1 reg_we_check[13] = key_4_we;
Tests: T1 T2 T4
2311 1/1 reg_we_check[14] = key_5_we;
Tests: T1 T2 T4
2312 1/1 reg_we_check[15] = key_6_we;
Tests: T1 T2 T4
2313 1/1 reg_we_check[16] = key_7_we;
Tests: T1 T2 T4
2314 1/1 reg_we_check[17] = key_8_we;
Tests: T1 T2 T4
2315 1/1 reg_we_check[18] = key_9_we;
Tests: T1 T2 T4
2316 1/1 reg_we_check[19] = key_10_we;
Tests: T1 T2 T4
2317 1/1 reg_we_check[20] = key_11_we;
Tests: T1 T2 T4
2318 1/1 reg_we_check[21] = key_12_we;
Tests: T1 T2 T4
2319 1/1 reg_we_check[22] = key_13_we;
Tests: T1 T2 T4
2320 1/1 reg_we_check[23] = key_14_we;
Tests: T1 T2 T4
2321 1/1 reg_we_check[24] = key_15_we;
Tests: T1 T2 T4
2322 1/1 reg_we_check[25] = key_16_we;
Tests: T1 T2 T4
2323 1/1 reg_we_check[26] = key_17_we;
Tests: T1 T2 T4
2324 1/1 reg_we_check[27] = key_18_we;
Tests: T1 T2 T4
2325 1/1 reg_we_check[28] = key_19_we;
Tests: T1 T2 T4
2326 1/1 reg_we_check[29] = key_20_we;
Tests: T1 T2 T4
2327 1/1 reg_we_check[30] = key_21_we;
Tests: T1 T2 T4
2328 1/1 reg_we_check[31] = key_22_we;
Tests: T1 T2 T4
2329 1/1 reg_we_check[32] = key_23_we;
Tests: T1 T2 T4
2330 1/1 reg_we_check[33] = key_24_we;
Tests: T1 T2 T4
2331 1/1 reg_we_check[34] = key_25_we;
Tests: T1 T2 T4
2332 1/1 reg_we_check[35] = key_26_we;
Tests: T1 T2 T4
2333 1/1 reg_we_check[36] = key_27_we;
Tests: T1 T2 T4
2334 1/1 reg_we_check[37] = key_28_we;
Tests: T1 T2 T4
2335 1/1 reg_we_check[38] = key_29_we;
Tests: T1 T2 T4
2336 1/1 reg_we_check[39] = key_30_we;
Tests: T1 T2 T4
2337 1/1 reg_we_check[40] = key_31_we;
Tests: T1 T2 T4
2338 1/1 reg_we_check[41] = digest_0_we;
Tests: T1 T2 T4
2339 1/1 reg_we_check[42] = digest_1_we;
Tests: T1 T2 T4
2340 1/1 reg_we_check[43] = digest_2_we;
Tests: T1 T2 T4
2341 1/1 reg_we_check[44] = digest_3_we;
Tests: T1 T2 T4
2342 1/1 reg_we_check[45] = digest_4_we;
Tests: T1 T2 T4
2343 1/1 reg_we_check[46] = digest_5_we;
Tests: T1 T2 T4
2344 1/1 reg_we_check[47] = digest_6_we;
Tests: T1 T2 T4
2345 1/1 reg_we_check[48] = digest_7_we;
Tests: T1 T2 T4
2346 1/1 reg_we_check[49] = digest_8_we;
Tests: T1 T2 T4
2347 1/1 reg_we_check[50] = digest_9_we;
Tests: T1 T2 T4
2348 1/1 reg_we_check[51] = digest_10_we;
Tests: T1 T2 T4
2349 1/1 reg_we_check[52] = digest_11_we;
Tests: T1 T2 T4
2350 1/1 reg_we_check[53] = digest_12_we;
Tests: T1 T2 T4
2351 1/1 reg_we_check[54] = digest_13_we;
Tests: T1 T2 T4
2352 1/1 reg_we_check[55] = digest_14_we;
Tests: T1 T2 T4
2353 1/1 reg_we_check[56] = digest_15_we;
Tests: T1 T2 T4
2354 1/1 reg_we_check[57] = msg_length_lower_we;
Tests: T1 T2 T4
2355 1/1 reg_we_check[58] = msg_length_upper_we;
Tests: T1 T2 T4
2356 end
2357
2358 // Read data return
2359 always_comb begin
2360 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
2361 1/1 unique case (1'b1)
Tests: T1 T2 T3
2362 addr_hit[0]: begin
2363 1/1 reg_rdata_next[0] = intr_state_hmac_done_qs;
Tests: T1 T2 T3
2364 1/1 reg_rdata_next[1] = intr_state_fifo_empty_qs;
Tests: T1 T2 T3
2365 1/1 reg_rdata_next[2] = intr_state_hmac_err_qs;
Tests: T1 T2 T3
2366 end
2367
2368 addr_hit[1]: begin
2369 1/1 reg_rdata_next[0] = intr_enable_hmac_done_qs;
Tests: T1 T2 T3
2370 1/1 reg_rdata_next[1] = intr_enable_fifo_empty_qs;
Tests: T1 T2 T3
2371 1/1 reg_rdata_next[2] = intr_enable_hmac_err_qs;
Tests: T1 T2 T3
2372 end
2373
2374 addr_hit[2]: begin
2375 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2376 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
2377 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
2378 end
2379
2380 addr_hit[3]: begin
2381 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2382 end
2383
2384 addr_hit[4]: begin
2385 1/1 reg_rdata_next[0] = cfg_hmac_en_qs;
Tests: T1 T2 T3
2386 1/1 reg_rdata_next[1] = cfg_sha_en_qs;
Tests: T1 T2 T3
2387 1/1 reg_rdata_next[2] = cfg_endian_swap_qs;
Tests: T1 T2 T3
2388 1/1 reg_rdata_next[3] = cfg_digest_swap_qs;
Tests: T1 T2 T3
2389 1/1 reg_rdata_next[4] = cfg_key_swap_qs;
Tests: T1 T2 T3
2390 1/1 reg_rdata_next[8:5] = cfg_digest_size_qs;
Tests: T1 T2 T3
2391 1/1 reg_rdata_next[14:9] = cfg_key_length_qs;
Tests: T1 T2 T3
2392 end
2393
2394 addr_hit[5]: begin
2395 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
2396 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
2397 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
2398 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
2399 end
2400
2401 addr_hit[6]: begin
2402 1/1 reg_rdata_next[0] = status_hmac_idle_qs;
Tests: T1 T2 T3
2403 1/1 reg_rdata_next[1] = status_fifo_empty_qs;
Tests: T1 T2 T3
2404 1/1 reg_rdata_next[2] = status_fifo_full_qs;
Tests: T1 T2 T3
2405 1/1 reg_rdata_next[9:4] = status_fifo_depth_qs;
Tests: T1 T2 T3
2406 end
2407
2408 addr_hit[7]: begin
2409 1/1 reg_rdata_next[31:0] = err_code_qs;
Tests: T1 T2 T3
2410 end
2411
2412 addr_hit[8]: begin
2413 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2414 end
2415
2416 addr_hit[9]: begin
2417 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2418 end
2419
2420 addr_hit[10]: begin
2421 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2422 end
2423
2424 addr_hit[11]: begin
2425 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2426 end
2427
2428 addr_hit[12]: begin
2429 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2430 end
2431
2432 addr_hit[13]: begin
2433 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2434 end
2435
2436 addr_hit[14]: begin
2437 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2438 end
2439
2440 addr_hit[15]: begin
2441 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2442 end
2443
2444 addr_hit[16]: begin
2445 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2446 end
2447
2448 addr_hit[17]: begin
2449 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2450 end
2451
2452 addr_hit[18]: begin
2453 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2454 end
2455
2456 addr_hit[19]: begin
2457 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2458 end
2459
2460 addr_hit[20]: begin
2461 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2462 end
2463
2464 addr_hit[21]: begin
2465 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2466 end
2467
2468 addr_hit[22]: begin
2469 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2470 end
2471
2472 addr_hit[23]: begin
2473 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2474 end
2475
2476 addr_hit[24]: begin
2477 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2478 end
2479
2480 addr_hit[25]: begin
2481 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2482 end
2483
2484 addr_hit[26]: begin
2485 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2486 end
2487
2488 addr_hit[27]: begin
2489 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2490 end
2491
2492 addr_hit[28]: begin
2493 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2494 end
2495
2496 addr_hit[29]: begin
2497 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2498 end
2499
2500 addr_hit[30]: begin
2501 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2502 end
2503
2504 addr_hit[31]: begin
2505 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2506 end
2507
2508 addr_hit[32]: begin
2509 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2510 end
2511
2512 addr_hit[33]: begin
2513 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2514 end
2515
2516 addr_hit[34]: begin
2517 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2518 end
2519
2520 addr_hit[35]: begin
2521 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2522 end
2523
2524 addr_hit[36]: begin
2525 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2526 end
2527
2528 addr_hit[37]: begin
2529 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2530 end
2531
2532 addr_hit[38]: begin
2533 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2534 end
2535
2536 addr_hit[39]: begin
2537 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2538 end
2539
2540 addr_hit[40]: begin
2541 1/1 reg_rdata_next[31:0] = '0;
Tests: T1 T2 T3
2542 end
2543
2544 addr_hit[41]: begin
2545 1/1 reg_rdata_next[31:0] = digest_0_qs;
Tests: T1 T2 T3
2546 end
2547
2548 addr_hit[42]: begin
2549 1/1 reg_rdata_next[31:0] = digest_1_qs;
Tests: T1 T2 T3
2550 end
2551
2552 addr_hit[43]: begin
2553 1/1 reg_rdata_next[31:0] = digest_2_qs;
Tests: T1 T2 T3
2554 end
2555
2556 addr_hit[44]: begin
2557 1/1 reg_rdata_next[31:0] = digest_3_qs;
Tests: T1 T2 T3
2558 end
2559
2560 addr_hit[45]: begin
2561 1/1 reg_rdata_next[31:0] = digest_4_qs;
Tests: T1 T2 T3
2562 end
2563
2564 addr_hit[46]: begin
2565 1/1 reg_rdata_next[31:0] = digest_5_qs;
Tests: T1 T2 T3
2566 end
2567
2568 addr_hit[47]: begin
2569 1/1 reg_rdata_next[31:0] = digest_6_qs;
Tests: T1 T2 T3
2570 end
2571
2572 addr_hit[48]: begin
2573 1/1 reg_rdata_next[31:0] = digest_7_qs;
Tests: T1 T2 T3
2574 end
2575
2576 addr_hit[49]: begin
2577 1/1 reg_rdata_next[31:0] = digest_8_qs;
Tests: T1 T2 T3
2578 end
2579
2580 addr_hit[50]: begin
2581 1/1 reg_rdata_next[31:0] = digest_9_qs;
Tests: T1 T2 T3
2582 end
2583
2584 addr_hit[51]: begin
2585 1/1 reg_rdata_next[31:0] = digest_10_qs;
Tests: T1 T2 T3
2586 end
2587
2588 addr_hit[52]: begin
2589 1/1 reg_rdata_next[31:0] = digest_11_qs;
Tests: T1 T2 T3
2590 end
2591
2592 addr_hit[53]: begin
2593 1/1 reg_rdata_next[31:0] = digest_12_qs;
Tests: T1 T2 T3
2594 end
2595
2596 addr_hit[54]: begin
2597 1/1 reg_rdata_next[31:0] = digest_13_qs;
Tests: T1 T2 T3
2598 end
2599
2600 addr_hit[55]: begin
2601 1/1 reg_rdata_next[31:0] = digest_14_qs;
Tests: T1 T2 T3
2602 end
2603
2604 addr_hit[56]: begin
2605 1/1 reg_rdata_next[31:0] = digest_15_qs;
Tests: T1 T2 T3
2606 end
2607
2608 addr_hit[57]: begin
2609 1/1 reg_rdata_next[31:0] = msg_length_lower_qs;
Tests: T1 T2 T3
2610 end
2611
2612 addr_hit[58]: begin
2613 1/1 reg_rdata_next[31:0] = msg_length_upper_qs;
Tests: T1 T2 T3
2614 end
2615
2616 default: begin
2617 reg_rdata_next = '1;
2618 end
2619 endcase
2620 end
2621
2622 // shadow busy
2623 logic shadow_busy;
2624 assign shadow_busy = 1'b0;
2625
2626 // register busy
2627 unreachable assign reg_busy = shadow_busy;
2628
2629 // Unused signal tieoff
2630
2631 // wdata / byte enable are not always fully used
2632 // add a blanket unused statement to handle lint waivers
2633 logic unused_wdata;
2634 logic unused_be;
2635 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
2636 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3