Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17266231	1			T1	1126		T2	551		T3	3062
all_values[1]	17266231	1			T1	1126		T2	551		T3	3062
all_values[2]	17266231	1			T1	1126		T2	551		T3	3062

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

254413

1

T1

112

T3

3062

T18

2832

auto[1]

51544280

1

T1

3266

T2

1653

T3

6124

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44257397

1

T1

2808

T2

1355

T3

6898

auto[1]

7541296

1

T1

570

T2

298

T3

2288

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	76438	1			T18	1856		T7	4		T9	80
all_values[0]	auto[0]	auto[1]	331	1			T7	3		T9	2		T125	2
all_values[0]	auto[1]	auto[0]	17170624	1			T1	1116		T2	543		T3	3062
all_values[0]	auto[1]	auto[1]	18838	1			T1	10		T2	8		T4	30
all_values[1]	auto[0]	auto[0]	92690	1			T7	6		T131	18		T10	1
all_values[1]	auto[0]	auto[1]	173	1			T7	2		T26	2		T51	2
all_values[1]	auto[1]	auto[0]	17173092	1			T1	1126		T2	551		T3	3062
all_values[1]	auto[1]	auto[1]	276	1			T7	3		T11	2		T26	4
all_values[2]	auto[0]	auto[0]	47732	1			T1	47		T3	774		T18	257
all_values[2]	auto[0]	auto[1]	37049	1			T1	65		T3	2288		T18	719
all_values[2]	auto[1]	auto[0]	9696821	1			T1	519		T2	261		T4	1523
all_values[2]	auto[1]	auto[1]	7484629	1			T1	495		T2	290		T4	449