Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102116

1

T1

18

T2

190

T4

36

auto[1]

109178

1

T1

4

T2

212

T4

24

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	77006	1			T2	126		T5	2		T6	11
len_1026_2046	5891	1			T1	1		T2	4		T4	5
len_514_1022	4164	1			T1	1		T2	2		T18	5
len_2_510	3827	1			T1	4		T7	26		T131	1
len_2056	144	1			T4	3		T7	1		T145	4
len_2048	257	1			T4	4		T7	8		T8	1
len_2040	162	1			T1	1		T4	3		T7	1
len_1032	189	1			T7	2		T131	6		T63	2
len_1024	1813	1			T19	78		T30	90		T7	3
len_1016	189	1			T4	4		T7	1		T145	1
len_520	154	1			T4	3		T7	3		T145	3
len_512	314	1			T1	1		T4	2		T7	1
len_504	165	1			T4	6		T7	2		T63	2
len_8	980	1			T9	1		T62	6		T10	1
len_0	10391	1			T1	3		T2	69		T18	4

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

100

1

T8

3

T20

3

T75

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	38859	1			T2	69		T5	2		T6	7
auto[0]	len_1026_2046	2769	1			T1	1		T2	4		T4	2
auto[0]	len_514_1022	2083	1			T1	1		T2	1		T18	2
auto[0]	len_2_510	1648	1			T1	4		T7	10		T20	1
auto[0]	len_2056	86	1			T4	3		T7	1		T145	2
auto[0]	len_2048	135	1			T4	2		T7	3		T8	1
auto[0]	len_2040	81	1			T4	3		T63	1		T146	2
auto[0]	len_1032	112	1			T7	2		T131	3		T63	2
auto[0]	len_1024	270	1			T7	2		T10	1		T26	2
auto[0]	len_1016	107	1			T4	2		T145	1		T147	1
auto[0]	len_520	90	1			T4	1		T7	3		T145	2
auto[0]	len_512	191	1			T1	1		T4	2		T7	1
auto[0]	len_504	83	1			T4	3		T145	3		T148	1
auto[0]	len_8	25	1			T149	1		T150	2		T151	1
auto[0]	len_0	4518	1			T1	2		T2	21		T18	2
auto[1]	len_2050_plus	38147	1			T2	57		T6	4		T18	5
auto[1]	len_1026_2046	3122	1			T4	3		T7	10		T20	6
auto[1]	len_514_1022	2081	1			T2	1		T18	3		T7	5
auto[1]	len_2_510	2179	1			T7	16		T131	1		T20	1
auto[1]	len_2056	58	1			T145	2		T152	1		T153	2
auto[1]	len_2048	122	1			T4	2		T7	5		T77	1
auto[1]	len_2040	81	1			T1	1		T7	1		T63	1
auto[1]	len_1032	77	1			T131	3		T154	2		T152	1
auto[1]	len_1024	1543	1			T19	78		T30	90		T7	1
auto[1]	len_1016	82	1			T4	2		T7	1		T147	1
auto[1]	len_520	64	1			T4	2		T145	1		T155	1
auto[1]	len_512	123	1			T20	1		T25	2		T156	1
auto[1]	len_504	82	1			T4	3		T7	2		T63	2
auto[1]	len_8	955	1			T9	1		T62	6		T10	1
auto[1]	len_0	5873	1			T1	1		T2	48		T18	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

56

1

T8

3

T20

2

T75

2

auto[1]

len_upper

44

1

T20

1

T50

2

T157

2