Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4299521

1

T1

260

T2

350

T3

1574

auto[1]

2673334

1

T1

300

T2

551

T4

391

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2616936

1

T1

216

T2

376

T3

1574

auto[1]

4355919

1

T1

344

T2

525

T4

344

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3238449

1

T1

394

T2

451

T4

618

auto[1]

3734406

1

T1

166

T2

450

T3

1574

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4330729

1

T1

495

T2

602

T3

1574

auto[1]

2642126

1

T1

65

T2

299

T4

449

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6363847	1			T1	555		T2	834		T3	1574
fifo_depth[1]	108759	1			T1	4		T2	24		T4	9
fifo_depth[2]	76456	1			T1	1		T2	15		T4	11
fifo_depth[3]	59582	1			T2	12		T4	6		T5	32
fifo_depth[4]	55243	1			T2	9		T4	1		T5	38
fifo_depth[5]	44747	1			T2	4		T5	22		T6	1
fifo_depth[6]	36348	1			T2	2		T5	17		T19	67
fifo_depth[7]	23865	1			T5	15		T6	1		T19	24

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609008

1

T1

5

T2

67

T4

27

auto[1]

6363847

1

T1

555

T2

834

T3

1574

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6960424

1

T1

560

T2

901

T3

1574

auto[1]

12431

1

T26

606

T27

139

T28

198

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

27654

1

T1

1

T4

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

26487

1

T4

1

T22

72

T7

36

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

37436

1

T4

4

T5

90

T7

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29543

1

T4

2

T6

1

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

86305

1

T1

1

T2

18

T5

112

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

28077

1

T7

37

T8

1

T131

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30829

1

T2

27

T6

1

T18

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25482

1

T2

15

T8

1

T21

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41441

1

T4

3

T7

32

T21

23

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

38517

1

T4

6

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

47504

1

T4

5

T18

8

T7

13

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35464

1

T18

9

T7

45

T9

281

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40192

1

T18

21

T19

1011

T30

214

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

45045

1

T4

1

T7

6

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

29718

1

T1

3

T2

7

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

39314

1

T4

2

T7

29

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

170851

1

T1

29

T2

42

T4

51

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

186915

1

T1

5

T2

86

T4

127

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

172695

1

T1

120

T4

137

T5

178

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

177677

1

T1

11

T4

116

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1742063

1

T1

126

T2

96

T4

103

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

162393

1

T1

46

T4

8

T18

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

167447

1

T1

55

T2

109

T4

68

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

166595

1

T2

58

T6

1

T18

190

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

392465

1

T1

48

T2

108

T3

1574

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

393285

1

T1

2

T4

100

T18

1071

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

427682

1

T4

14

T6

3

T18

485

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

411320

1

T2

140

T4

1

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

496103

1

T1

1

T4

57

T6

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

421728

1

T1

1

T4

63

T7

197

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

420344

1

T1

111

T2

195

T4

18

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

454284

1

T4

22

T7

69

T31

2

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

198126

1

T1

30

T2

42

T4

52

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

213120

1

T1

5

T2

86

T4

128

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

208909

1

T1

120

T4

141

T5

268

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

206006

1

T1

11

T4

118

T6

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1826538

1

T1

127

T2

114

T4

103

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

188092

1

T1

46

T4

8

T18

24

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

196555

1

T1

55

T2

136

T4

68

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

191277

1

T2

73

T6

1

T18

190

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

433072

1

T1

48

T2

108

T3

1574

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

431665

1

T1

2

T4

106

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

474473

1

T4

19

T6

3

T18

493

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

446731

1

T2

140

T4

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

536245

1

T1

1

T4

57

T6

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

466380

1

T1

1

T4

64

T7

203

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

449768

1

T1

114

T2

202

T4

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

493467

1

T4

24

T7

98

T31

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

379

1

T160

1

T32

3

T161

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

282

1

T28

28

T160

2

T54

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1222

1

T26

42

T28

98

T54

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1214

1

T26

116

T28

72

T162

216

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1830

1

T26

7

T163

2

T164

29

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

2378

1

T160

280

T165

23

T164

53

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1721

1

T26

10

T160

50

T161

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

800

1

T26

58

T27

82

T162

23

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

834

1

T26

22

T160

4

T52

444

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

137

1

T26

37

T164

4

T166

57

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

713

1

T26

248

T27

42

T54

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

53

1

T27

15

T167

22

T168

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

50

1

T162

5

T167

2

T164

11

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

393

1

T26

8

T54

327

T165

12

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

294

1

T26

58

T161

20

T164

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

131

1

T160

78

T52

2

T161

9

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

170851

1

T1

29

T2

42

T4

51

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

186915

1

T1

5

T2

86

T4

127

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

172695

1

T1

120

T4

137

T5

178

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

177677

1

T1

11

T4

116

T6

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1742063

1

T1

126

T2

96

T4

103

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

162393

1

T1

46

T4

8

T18

24

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

167447

1

T1

55

T2

109

T4

68

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

166595

1

T2

58

T6

1

T18

190

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

392465

1

T1

48

T2

108

T3

1574

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

393285

1

T1

2

T4

100

T18

1071

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

427682

1

T4

14

T6

3

T18

485

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

411320

1

T2

140

T4

1

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

496103

1

T1

1

T4

57

T6

2

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

421728

1

T1

1

T4

63

T7

197

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

420344

1

T1

111

T2

195

T4

18

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

454284

1

T4

22

T7

69

T31

2

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3548

1

T1

1

T4

1

T21

20

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3551

1

T22

2

T7

5

T31

4

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

4006

1

T4

2

T5

19

T7

1

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3359

1

T4

1

T21

9

T10

13

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

33678

1

T1

1

T2

5

T5

12

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3130

1

T7

1

T58

7

T75

18

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3637

1

T2

9

T18

6

T7

11

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3348

1

T2

7

T21

22

T20

13

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6511

1

T4

1

T7

2

T21

17

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5745

1

T4

1

T7

1

T21

7

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

5726

1

T4

1

T18

6

T7

4

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6463

1

T18

6

T7

3

T9

53

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7636

1

T18

15

T19

222

T30

109

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

7210

1

T4

1

T7

4

T9

71

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

4564

1

T1

2

T2

3

T131

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6647

1

T4

1

T20

1

T10

2

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2857

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17

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28

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167

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6