Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17266231	1			T1	1126		T2	551		T3	3062
all_pins[1]	17266231	1			T1	1126		T2	551		T3	3062
all_pins[2]	17266231	1			T1	1126		T2	551		T3	3062

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44294159	1			T1	2873		T2	1354		T3	9186
values[0x1]	7504534	1			T1	505		T2	299		T4	480
transitions[0x0=>0x1]	7504391	1			T1	505		T2	299		T4	480
transitions[0x1=>0x0]	7504406	1			T1	505		T2	299		T4	480

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17246628	1			T1	1116		T2	542		T3	3062
all_pins[0]	values[0x1]	19603	1			T1	10		T2	9		T4	31
all_pins[0]	transitions[0x0=>0x1]	19552	1			T1	10		T2	9		T4	31
all_pins[0]	transitions[0x1=>0x0]	7484593	1			T1	495		T2	290		T4	449
all_pins[1]	values[0x0]	17265929	1			T1	1126		T2	551		T3	3062
all_pins[1]	values[0x1]	302	1			T7	3		T11	2		T26	6
all_pins[1]	transitions[0x0=>0x1]	253	1			T7	3		T11	1		T26	6
all_pins[1]	transitions[0x1=>0x0]	19554	1			T1	10		T2	9		T4	31
all_pins[2]	values[0x0]	9781602	1			T1	631		T2	261		T3	3062
all_pins[2]	values[0x1]	7484629	1			T1	495		T2	290		T4	449
all_pins[2]	transitions[0x0=>0x1]	7484586	1			T1	495		T2	290		T4	449
all_pins[2]	transitions[0x1=>0x0]	259	1			T7	2		T11	2		T26	6