Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	827	1			T7	14		T11	4		T51	14
all_values[1]	827	1			T7	14		T11	4		T51	14
all_values[2]	827	1			T7	14		T11	4		T51	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1257

1

T7

21

T11

5

T51

21

auto[1]

1224

1

T7

21

T11

7

T51

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844

1

T7

13

T11

3

T51

18

auto[1]

1637

1

T7

29

T11

9

T51

24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1401

1

T7

24

T11

6

T51

29

auto[1]

1080

1

T7

18

T11

6

T51

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

150

1

T7

2

T51

3

T15

2

all_values[0]

auto[0]

auto[0]

auto[1]

88

1

T7

1

T11

1

T51

3

all_values[0]

auto[0]

auto[1]

auto[0]

150

1

T7

2

T51

5

T12

1

all_values[0]

auto[0]

auto[1]

auto[1]

77

1

T7

2

T11

1

T12

1

all_values[0]

auto[1]

auto[0]

auto[1]

191

1

T7

3

T11

1

T51

3

all_values[0]

auto[1]

auto[1]

auto[1]

171

1

T7

4

T11

1

T12

2

all_values[1]

auto[0]

auto[0]

auto[0]

123

1

T7

2

T132

6

T133

2

all_values[1]

auto[0]

auto[0]

auto[1]

114

1

T7

2

T51

3

T12

1

all_values[1]

auto[0]

auto[1]

auto[0]

137

1

T7

3

T11

1

T51

4

all_values[1]

auto[0]

auto[1]

auto[1]

101

1

T7

2

T11

1

T51

2

all_values[1]

auto[1]

auto[0]

auto[1]

167

1

T7

2

T51

2

T12

2

all_values[1]

auto[1]

auto[1]

auto[1]

185

1

T7

3

T11

2

T51

3

all_values[2]

auto[0]

auto[0]

auto[0]

144

1

T7

1

T11

2

T51

3

all_values[2]

auto[0]

auto[0]

auto[1]

95

1

T7

3

T51

2

T132

6

all_values[2]

auto[0]

auto[1]

auto[0]

140

1

T7

3

T51

3

T15

2

all_values[2]

auto[0]

auto[1]

auto[1]

82

1

T7

1

T51

1

T132

3

all_values[2]

auto[1]

auto[0]

auto[1]

185

1

T7

5

T11

1

T51

2

all_values[2]

auto[1]

auto[1]

auto[1]

181

1

T7

1

T11

1

T51

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal