Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	3891	1			T1	5		T2	4		T4	9
sha2_none	3884	1			T1	9		T2	1		T4	3
sha2_512	7326	1			T1	5		T2	2		T3	1
sha2_384	7015	1			T1	4		T2	2		T4	9
sha2_256	5926	1			T1	3		T2	3		T4	5

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17890

1

T1

14

T2

6

T3

1

auto[1]

10507

1

T1

12

T2

6

T4

20

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10481

1

T1

12

T2

6

T3

1

auto[1]

17916

1

T1

14

T2

6

T4

14

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

14554

1

T1

10

T2

5

T3

1

disabled

13843

1

T1

16

T2

7

T4

23

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4271	1			T1	4		T2	1		T4	7
key_none	7527	1			T1	6		T3	1		T4	3
key_1024	4130	1			T1	2		T2	3		T4	5
key_512	3616	1			T1	6		T4	3		T6	1
key_384	3240	1			T1	2		T2	1		T4	5
key_256	2834	1			T1	2		T2	4		T4	6
key_128	2692	1			T1	4		T2	2		T4	8

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18069

1

T1

20

T2

8

T3

1

auto[1]

10328

1

T1

6

T2

4

T4

18

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

28195

1

T1

26

T2

12

T3

1

disabled

202

1

T7

2

T31

2

T58

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1525

1

T1

2

T2

1

T3

1

enabled

auto[0]

auto[0]

auto[1]

1461

1

T1

2

T4

3

T6

1

enabled

auto[0]

auto[1]

auto[0]

1476

1

T4

2

T6

3

T18

2

enabled

auto[0]

auto[1]

auto[1]

1467

1

T2

1

T4

1

T6

1

enabled

auto[1]

auto[0]

auto[0]

4169

1

T1

1

T4

2

T6

2

enabled

auto[1]

auto[0]

auto[1]

1455

1

T1

1

T4

2

T7

5

enabled

auto[1]

auto[1]

auto[0]

1551

1

T1

4

T2

3

T4

2

enabled

auto[1]

auto[1]

auto[1]

1450

1

T4

1

T7

6

T31

1

disabled

auto[0]

auto[0]

auto[0]

1136

1

T1

2

T2

2

T4

2

disabled

auto[0]

auto[0]

auto[1]

1143

1

T1

1

T2

2

T4

4

disabled

auto[0]

auto[1]

auto[0]

1134

1

T1

4

T4

4

T5

1

disabled

auto[0]

auto[1]

auto[1]

1139

1

T1

1

T4

6

T6

2

disabled

auto[1]

auto[0]

auto[0]

5918

1

T1

4

T2

1

T4

2

disabled

auto[1]

auto[0]

auto[1]

1083

1

T1

1

T4

1

T18

1

disabled

auto[1]

auto[1]

auto[0]

1160

1

T1

3

T2

1

T4

4

disabled

auto[1]

auto[1]

auto[1]

1130

1

T2

1

T6

1

T18

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

14474

1

T1

10

T2

5

T3

1

enabled

disabled

80

1

T7

1

T58

2

T10

1

disabled

disabled

122

1

T7

1

T31

2

T58

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

13721

1

T1

16

T2

7

T4

23

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1015	1			T2	1		T4	3		T7	3
key_invalid	sha2_none	826	1			T1	1		T4	1		T6	2
key_invalid	sha2_512	769	1			T1	1		T4	1		T6	2
key_invalid	sha2_384	768	1			T1	1		T18	2		T22	1
key_invalid	sha2_256	790	1			T1	1		T4	1		T5	1
key_none	sha2_invalid	466	1			T1	2		T4	1		T6	1
key_none	sha2_none	489	1			T1	1		T6	1		T18	1
key_none	sha2_512	2536	1			T1	1		T3	1		T4	1
key_none	sha2_384	2478	1			T1	1		T4	1		T18	1
key_none	sha2_256	1515	1			T1	1		T7	2		T8	1
key_1024	sha2_invalid	470	1			T2	1		T18	1		T7	1
key_1024	sha2_none	489	1			T1	1		T2	1		T6	1
key_1024	sha2_512	1712	1			T1	1		T2	1		T4	1
key_1024	sha2_384	890	1			T4	3		T30	60		T7	8
key_512	sha2_invalid	492	1			T1	1		T4	1		T7	2
key_512	sha2_none	529	1			T1	3		T18	1		T22	1
key_512	sha2_512	595	1			T7	1		T8	3		T21	1
key_512	sha2_384	1151	1			T1	2		T4	1		T30	120
key_512	sha2_256	810	1			T4	1		T6	1		T19	45
key_384	sha2_invalid	472	1			T4	2		T7	1		T31	1
key_384	sha2_none	499	1			T1	1		T6	1		T7	2
key_384	sha2_512	583	1			T1	1		T18	1		T7	6
key_384	sha2_384	581	1			T2	1		T4	1		T7	2
key_384	sha2_256	1051	1			T4	2		T6	1		T19	90
key_256	sha2_invalid	465	1			T2	1		T4	1		T7	1
key_256	sha2_none	548	1			T1	1		T4	1		T6	1
key_256	sha2_512	576	1			T2	1		T4	4		T18	2
key_256	sha2_384	574	1			T2	1		T18	3		T7	2
key_256	sha2_256	629	1			T1	1		T2	1		T6	2
key_128	sha2_invalid	490	1			T1	2		T2	1		T4	1
key_128	sha2_none	490	1			T1	1		T4	1		T18	1
key_128	sha2_512	536	1			T1	1		T4	3		T7	1
key_128	sha2_384	561	1			T4	3		T6	1		T7	1
key_128	sha2_256	585	1			T2	1		T6	1		T22	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

529

1

T4

1

T7

2

T8

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1015	1			T2	1		T4	3		T7	3
key_invalid	sha2_none	826	1			T1	1		T4	1		T6	2
key_invalid	sha2_512	769	1			T1	1		T4	1		T6	2
key_invalid	sha2_384	768	1			T1	1		T18	2		T22	1
key_invalid	sha2_256	790	1			T1	1		T4	1		T5	1
key_none	sha2_invalid	466	1			T1	2		T4	1		T6	1
key_none	sha2_none	489	1			T1	1		T6	1		T18	1
key_none	sha2_512	2536	1			T1	1		T3	1		T4	1
key_none	sha2_384	2478	1			T1	1		T4	1		T18	1
key_none	sha2_256	1515	1			T1	1		T7	2		T8	1
key_1024	sha2_invalid	470	1			T2	1		T18	1		T7	1
key_1024	sha2_none	489	1			T1	1		T2	1		T6	1
key_1024	sha2_512	1712	1			T1	1		T2	1		T4	1
key_1024	sha2_384	890	1			T4	3		T30	60		T7	8
key_1024	sha2_256	529	1			T4	1		T7	2		T8	2
key_512	sha2_invalid	492	1			T1	1		T4	1		T7	2
key_512	sha2_none	529	1			T1	3		T18	1		T22	1
key_512	sha2_512	595	1			T7	1		T8	3		T21	1
key_512	sha2_384	1151	1			T1	2		T4	1		T30	120
key_512	sha2_256	810	1			T4	1		T6	1		T19	45
key_384	sha2_invalid	472	1			T4	2		T7	1		T31	1
key_384	sha2_none	499	1			T1	1		T6	1		T7	2
key_384	sha2_512	583	1			T1	1		T18	1		T7	6
key_384	sha2_384	581	1			T2	1		T4	1		T7	2
key_384	sha2_256	1051	1			T4	2		T6	1		T19	90
key_256	sha2_invalid	465	1			T2	1		T4	1		T7	1
key_256	sha2_none	548	1			T1	1		T4	1		T6	1
key_256	sha2_512	576	1			T2	1		T4	4		T18	2
key_256	sha2_384	574	1			T2	1		T18	3		T7	2
key_256	sha2_256	629	1			T1	1		T2	1		T6	2
key_128	sha2_invalid	490	1			T1	2		T2	1		T4	1
key_128	sha2_none	490	1			T1	1		T4	1		T18	1
key_128	sha2_512	536	1			T1	1		T4	3		T7	1
key_128	sha2_384	561	1			T4	3		T6	1		T7	1
key_128	sha2_256	585	1			T2	1		T6	1		T22	1