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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.03 95.40 97.17 100.00 97.06 98.27 98.48 99.85


Total test records in report: 653
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T73 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2633663072 Aug 23 05:00:58 PM UTC 24 Aug 23 05:01:02 PM UTC 24 537032422 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3984494404 Aug 23 05:00:59 PM UTC 24 Aug 23 05:01:02 PM UTC 24 60785392 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.1402590634 Aug 23 05:00:56 PM UTC 24 Aug 23 05:01:02 PM UTC 24 1245079649 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.2289894932 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:03 PM UTC 24 10766390 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3949877314 Aug 23 05:00:58 PM UTC 24 Aug 23 05:01:03 PM UTC 24 985275268 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1274036007 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:03 PM UTC 24 49154634 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2864692995 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:03 PM UTC 24 34212565 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1479981301 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:03 PM UTC 24 99488922 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4055748269 Aug 23 05:01:02 PM UTC 24 Aug 23 05:01:04 PM UTC 24 642281461 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.192882393 Aug 23 05:01:02 PM UTC 24 Aug 23 05:01:04 PM UTC 24 107590776 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3050337114 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:05 PM UTC 24 716556067 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.855602574 Aug 23 05:00:58 PM UTC 24 Aug 23 05:01:05 PM UTC 24 607904064 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3865769259 Aug 23 05:01:03 PM UTC 24 Aug 23 05:01:05 PM UTC 24 122995499 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.915958125 Aug 23 05:01:03 PM UTC 24 Aug 23 05:01:05 PM UTC 24 98450577 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3325853562 Aug 23 05:01:03 PM UTC 24 Aug 23 05:01:05 PM UTC 24 31082982 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4117496507 Aug 23 05:01:03 PM UTC 24 Aug 23 05:01:06 PM UTC 24 605491346 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.606884076 Aug 23 05:01:01 PM UTC 24 Aug 23 05:01:07 PM UTC 24 111434814 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1937648203 Aug 23 05:01:06 PM UTC 24 Aug 23 05:01:08 PM UTC 24 212022975 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.54285291 Aug 23 05:01:06 PM UTC 24 Aug 23 05:01:08 PM UTC 24 1589244314 ps
T135 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1034138872 Aug 23 05:01:03 PM UTC 24 Aug 23 05:01:08 PM UTC 24 957698976 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.4208657705 Aug 23 05:01:06 PM UTC 24 Aug 23 05:01:08 PM UTC 24 161801453 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3860478376 Aug 23 05:01:02 PM UTC 24 Aug 23 05:01:09 PM UTC 24 308862638 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.590639749 Aug 23 05:01:07 PM UTC 24 Aug 23 05:01:09 PM UTC 24 14135082 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2119830855 Aug 23 05:01:07 PM UTC 24 Aug 23 05:01:09 PM UTC 24 95667692 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.4203909000 Aug 23 05:01:07 PM UTC 24 Aug 23 05:01:09 PM UTC 24 24198334 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.682567677 Aug 23 05:01:06 PM UTC 24 Aug 23 05:01:10 PM UTC 24 262379822 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3274720661 Aug 23 05:01:04 PM UTC 24 Aug 23 05:01:10 PM UTC 24 365213429 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2339350932 Aug 23 05:00:56 PM UTC 24 Aug 23 05:01:11 PM UTC 24 2149408915 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3166553296 Aug 23 05:01:09 PM UTC 24 Aug 23 05:01:12 PM UTC 24 33760601 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.893839039 Aug 23 05:01:10 PM UTC 24 Aug 23 05:01:12 PM UTC 24 23337875 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.30418348 Aug 23 05:01:10 PM UTC 24 Aug 23 05:01:12 PM UTC 24 20261740 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3069801678 Aug 23 05:01:09 PM UTC 24 Aug 23 05:01:12 PM UTC 24 120602336 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.198627590 Aug 23 05:01:09 PM UTC 24 Aug 23 05:01:12 PM UTC 24 129664364 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4220761955 Aug 23 05:00:58 PM UTC 24 Aug 23 05:01:14 PM UTC 24 5470404137 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3486177048 Aug 23 05:01:11 PM UTC 24 Aug 23 05:01:14 PM UTC 24 72451341 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.4275049936 Aug 23 05:01:06 PM UTC 24 Aug 23 05:01:14 PM UTC 24 1743380579 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.709378 Aug 23 05:01:10 PM UTC 24 Aug 23 05:01:14 PM UTC 24 689216756 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1924390046 Aug 23 05:01:12 PM UTC 24 Aug 23 05:01:14 PM UTC 24 15878983 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.1061273108 Aug 23 05:01:11 PM UTC 24 Aug 23 05:01:14 PM UTC 24 175375838 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3069550928 Aug 23 05:01:12 PM UTC 24 Aug 23 05:01:14 PM UTC 24 25171559 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2491399760 Aug 23 05:01:08 PM UTC 24 Aug 23 05:01:14 PM UTC 24 378232569 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2184224547 Aug 23 05:01:10 PM UTC 24 Aug 23 05:01:15 PM UTC 24 723063063 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3080087624 Aug 23 05:01:13 PM UTC 24 Aug 23 05:01:16 PM UTC 24 79647528 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4238178551 Aug 23 05:01:09 PM UTC 24 Aug 23 05:01:16 PM UTC 24 302596853 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4271490569 Aug 23 05:01:13 PM UTC 24 Aug 23 05:01:16 PM UTC 24 52288657 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2875372287 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:17 PM UTC 24 13268412 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3901653097 Aug 23 05:01:13 PM UTC 24 Aug 23 05:01:17 PM UTC 24 114129292 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.879077523 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:17 PM UTC 24 21809644 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.724998954 Aug 23 05:01:12 PM UTC 24 Aug 23 05:01:17 PM UTC 24 219161696 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1615921102 Aug 23 05:01:16 PM UTC 24 Aug 23 05:01:17 PM UTC 24 14286407 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2514841985 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:18 PM UTC 24 35059518 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1634409098 Aug 23 05:01:16 PM UTC 24 Aug 23 05:01:18 PM UTC 24 58287542 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.525363768 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:18 PM UTC 24 274520355 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2645106915 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:18 PM UTC 24 102507212 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.1995860861 Aug 23 05:01:16 PM UTC 24 Aug 23 05:01:19 PM UTC 24 80965614 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3832600264 Aug 23 05:01:15 PM UTC 24 Aug 23 05:01:19 PM UTC 24 270463523 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.305887858 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:19 PM UTC 24 33178629 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1655592760 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:19 PM UTC 24 51432375 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1349540772 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:19 PM UTC 24 135018920 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2736605018 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:20 PM UTC 24 88219892 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3916927887 Aug 23 05:01:19 PM UTC 24 Aug 23 05:01:20 PM UTC 24 30233911 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3454240074 Aug 23 05:01:18 PM UTC 24 Aug 23 05:01:21 PM UTC 24 295525905 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.4113426489 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:21 PM UTC 24 62170004 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.711693693 Aug 23 05:01:18 PM UTC 24 Aug 23 05:01:21 PM UTC 24 207166274 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.4179529176 Aug 23 05:01:19 PM UTC 24 Aug 23 05:01:21 PM UTC 24 210740009 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3190328775 Aug 23 05:01:18 PM UTC 24 Aug 23 05:01:22 PM UTC 24 281823583 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.78184179 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:22 PM UTC 24 21520271 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.205394806 Aug 23 05:01:17 PM UTC 24 Aug 23 05:01:22 PM UTC 24 689769401 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.870287162 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:22 PM UTC 24 37743261 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.926897744 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:22 PM UTC 24 90920011 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1020326382 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:22 PM UTC 24 139846302 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1232043100 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:23 PM UTC 24 101527531 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3659396058 Aug 23 05:01:20 PM UTC 24 Aug 23 05:01:23 PM UTC 24 90493985 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3097269344 Aug 23 05:01:21 PM UTC 24 Aug 23 05:01:23 PM UTC 24 30347949 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3693125131 Aug 23 05:01:21 PM UTC 24 Aug 23 05:01:23 PM UTC 24 88267882 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3949193370 Aug 23 05:01:21 PM UTC 24 Aug 23 05:01:24 PM UTC 24 66119578 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3040182265 Aug 23 05:01:22 PM UTC 24 Aug 23 05:01:24 PM UTC 24 123531384 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4269090039 Aug 23 05:01:22 PM UTC 24 Aug 23 05:01:25 PM UTC 24 61867360 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.454714951 Aug 23 05:01:23 PM UTC 24 Aug 23 05:01:25 PM UTC 24 522162084 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.3303478155 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:25 PM UTC 24 76528873 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.815524696 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:26 PM UTC 24 17377658 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1527163729 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:26 PM UTC 24 839408034 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.319897052 Aug 23 05:01:25 PM UTC 24 Aug 23 05:01:27 PM UTC 24 33749901 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.132011636 Aug 23 05:01:25 PM UTC 24 Aug 23 05:01:27 PM UTC 24 12567749 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2189111192 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:27 PM UTC 24 286909049 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.625215299 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:27 PM UTC 24 136144179 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.3624398128 Aug 23 05:01:22 PM UTC 24 Aug 23 05:01:27 PM UTC 24 3105207339 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1097437341 Aug 23 05:01:25 PM UTC 24 Aug 23 05:01:28 PM UTC 24 441293856 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3504315233 Aug 23 05:01:22 PM UTC 24 Aug 23 05:01:28 PM UTC 24 958407159 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.2281456783 Aug 23 05:01:25 PM UTC 24 Aug 23 05:01:28 PM UTC 24 582794366 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2584014375 Aug 23 05:01:23 PM UTC 24 Aug 23 05:01:28 PM UTC 24 90369179 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2599216895 Aug 23 05:01:24 PM UTC 24 Aug 23 05:01:28 PM UTC 24 513409588 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3605164840 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:30 PM UTC 24 15591645 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1914154254 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:30 PM UTC 24 13578184 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3100420172 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:31 PM UTC 24 12182619 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.2731947647 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:31 PM UTC 24 31667275 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1487747493 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:31 PM UTC 24 327851790 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1256420688 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:31 PM UTC 24 66293710 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2525386897 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:32 PM UTC 24 511194306 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1302476332 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:32 PM UTC 24 103662333 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1114130036 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:32 PM UTC 24 152371682 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2436119330 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:32 PM UTC 24 347336704 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1425184603 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:32 PM UTC 24 229945101 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3035587784 Aug 23 05:01:31 PM UTC 24 Aug 23 05:01:33 PM UTC 24 11981085 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3581393335 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:33 PM UTC 24 666377130 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3092301147 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:33 PM UTC 24 310451674 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3106710197 Aug 23 05:01:31 PM UTC 24 Aug 23 05:01:33 PM UTC 24 40244079 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2720102662 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:33 PM UTC 24 926860160 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2346101198 Aug 23 05:01:29 PM UTC 24 Aug 23 05:01:34 PM UTC 24 461203149 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2115542383 Aug 23 05:01:31 PM UTC 24 Aug 23 05:01:34 PM UTC 24 110400989 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3727917430 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:34 PM UTC 24 13473164 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1725163240 Aug 23 05:01:31 PM UTC 24 Aug 23 05:01:35 PM UTC 24 604432903 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.624937242 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:35 PM UTC 24 51428036 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.461934427 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:35 PM UTC 24 144926861 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.853314095 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:36 PM UTC 24 373705919 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4044555917 Aug 23 05:01:34 PM UTC 24 Aug 23 05:01:36 PM UTC 24 18136922 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1437108186 Aug 23 05:01:34 PM UTC 24 Aug 23 05:01:36 PM UTC 24 96786190 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3692629836 Aug 23 05:01:34 PM UTC 24 Aug 23 05:01:37 PM UTC 24 541730801 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1205987389 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:37 PM UTC 24 337260506 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3967140661 Aug 23 05:01:34 PM UTC 24 Aug 23 05:01:37 PM UTC 24 441022360 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3347181916 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:37 PM UTC 24 267232534 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2129248771 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 28969690 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1738469630 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 25888863 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3375506724 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 23287476 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3828145091 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 14396477 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.773148621 Aug 23 05:01:33 PM UTC 24 Aug 23 05:01:37 PM UTC 24 128119332 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1534524396 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 27317438 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2886543713 Aug 23 05:01:35 PM UTC 24 Aug 23 05:01:37 PM UTC 24 25102158 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3746071634 Aug 23 05:01:34 PM UTC 24 Aug 23 05:01:38 PM UTC 24 962070297 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.860610794 Aug 23 05:01:37 PM UTC 24 Aug 23 05:01:38 PM UTC 24 17525638 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.114318434 Aug 23 05:01:37 PM UTC 24 Aug 23 05:01:38 PM UTC 24 12679790 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1815185128 Aug 23 05:01:37 PM UTC 24 Aug 23 05:01:38 PM UTC 24 15431237 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.151357084 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 30327199 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.695848881 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 24871199 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2442296403 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 24267065 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2995919175 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 32592979 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.4006910130 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 40628369 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2763876077 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 23351691 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1775580496 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 22408567 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.439680798 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 13897358 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1463659140 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 25266852 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.42523221 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 18223806 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1510938023 Aug 23 05:01:38 PM UTC 24 Aug 23 05:01:40 PM UTC 24 59772364 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1876807037 Aug 23 05:01:40 PM UTC 24 Aug 23 05:01:41 PM UTC 24 23726329 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2275025024 Aug 23 05:01:40 PM UTC 24 Aug 23 05:01:41 PM UTC 24 36510930 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2568757526 Aug 23 05:01:40 PM UTC 24 Aug 23 05:01:42 PM UTC 24 43898861 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3811083097 Aug 23 05:01:40 PM UTC 24 Aug 23 05:01:42 PM UTC 24 32739697 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3093662792 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 16387303 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1448723383 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 43017854 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2707698755 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 14042884 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1842475444 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 24621957 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2064825895 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 27957916 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1832311300 Aug 23 05:01:41 PM UTC 24 Aug 23 05:01:43 PM UTC 24 14215739 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_smoke.3131011071
Short name T4
Test name
Test status
Simulation time 793755147 ps
CPU time 11.7 seconds
Started Aug 23 03:53:33 PM UTC 24
Finished Aug 23 03:53:46 PM UTC 24
Peak memory 207400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131011071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3131011071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_stress_all_with_rand_reset.473576514
Short name T10
Test name
Test status
Simulation time 15734012044 ps
CPU time 256.45 seconds
Started Aug 23 03:53:28 PM UTC 24
Finished Aug 23 03:57:48 PM UTC 24
Peak memory 475632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47357651
4 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.473576514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_stress_all.579752916
Short name T7
Test name
Test status
Simulation time 4374951571 ps
CPU time 56.06 seconds
Started Aug 23 03:53:22 PM UTC 24
Finished Aug 23 03:54:20 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579752916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.579752916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_stress_all_with_rand_reset.1474665392
Short name T11
Test name
Test status
Simulation time 10526054824 ps
CPU time 89.85 seconds
Started Aug 23 03:57:42 PM UTC 24
Finished Aug 23 03:59:13 PM UTC 24
Peak memory 244072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14746653
92 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1474665392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_burst_wr.172463052
Short name T26
Test name
Test status
Simulation time 4475678294 ps
CPU time 50.85 seconds
Started Aug 23 04:00:10 PM UTC 24
Finished Aug 23 04:01:03 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172463052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.172463052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_intg_err.3148795715
Short name T68
Test name
Test status
Simulation time 134093015 ps
CPU time 3.55 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:01:00 PM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3148795715 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3148795715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_stress_all.3474376444
Short name T51
Test name
Test status
Simulation time 38388297888 ps
CPU time 564.93 seconds
Started Aug 23 03:55:17 PM UTC 24
Finished Aug 23 04:04:48 PM UTC 24
Peak memory 727392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474376444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3474376444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_sec_cm.3718959474
Short name T16
Test name
Test status
Simulation time 35299180 ps
CPU time 0.76 seconds
Started Aug 23 03:53:29 PM UTC 24
Finished Aug 23 03:53:31 PM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718959474 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3718959474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_hw_reset.3939402394
Short name T85
Test name
Test status
Simulation time 21276230 ps
CPU time 0.65 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:00:58 PM UTC 24
Peak memory 206188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939402394 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3939402394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_back_pressure.4121029492
Short name T14
Test name
Test status
Simulation time 552915283 ps
CPU time 27.45 seconds
Started Aug 23 04:32:44 PM UTC 24
Finished Aug 23 04:33:13 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121029492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4121029492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_datapath_stress.745477876
Short name T62
Test name
Test status
Simulation time 8590093981 ps
CPU time 165.41 seconds
Started Aug 23 03:53:49 PM UTC 24
Finished Aug 23 03:56:37 PM UTC 24
Peak memory 680164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745477876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.745477876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_burst_wr.233883736
Short name T160
Test name
Test status
Simulation time 987006102 ps
CPU time 45.24 seconds
Started Aug 23 04:12:29 PM UTC 24
Finished Aug 23 04:13:15 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233883736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.233883736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_intg_err.2184224547
Short name T134
Test name
Test status
Simulation time 723063063 ps
CPU time 3.89 seconds
Started Aug 23 05:01:10 PM UTC 24
Finished Aug 23 05:01:15 PM UTC 24
Peak memory 207740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184224547 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2184224547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_burst_wr.2339657863
Short name T20
Test name
Test status
Simulation time 4592565900 ps
CPU time 19.81 seconds
Started Aug 23 03:56:25 PM UTC 24
Finished Aug 23 03:56:46 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339657863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2339657863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_alert_test.3608119367
Short name T17
Test name
Test status
Simulation time 14799119 ps
CPU time 0.55 seconds
Started Aug 23 03:53:31 PM UTC 24
Finished Aug 23 03:53:33 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608119367 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3608119367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_intg_err.724998954
Short name T137
Test name
Test status
Simulation time 219161696 ps
CPU time 3.56 seconds
Started Aug 23 05:01:12 PM UTC 24
Finished Aug 23 05:01:17 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724998954 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.724998954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_stress_all.2846505470
Short name T274
Test name
Test status
Simulation time 227194653507 ps
CPU time 845.57 seconds
Started Aug 23 04:18:06 PM UTC 24
Finished Aug 23 04:32:20 PM UTC 24
Peak memory 223780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846505470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2846505470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_burst_wr.1138540985
Short name T167
Test name
Test status
Simulation time 866769057 ps
CPU time 39.94 seconds
Started Aug 23 04:41:32 PM UTC 24
Finished Aug 23 04:42:13 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138540985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1138540985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_sha256_vectors.2359356673
Short name T151
Test name
Test status
Simulation time 11606223842 ps
CPU time 563.45 seconds
Started Aug 23 04:01:04 PM UTC 24
Finished Aug 23 04:10:34 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359356673 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2359356673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_rw.1464820835
Short name T103
Test name
Test status
Simulation time 28040430 ps
CPU time 0.74 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:00:58 PM UTC 24
Peak memory 206772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464820835 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1464820835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_wipe_secret.2743745094
Short name T18
Test name
Test status
Simulation time 36273557781 ps
CPU time 40.32 seconds
Started Aug 23 03:53:13 PM UTC 24
Finished Aug 23 03:53:55 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743745094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2743745094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_hmac256_vectors.1608585876
Short name T19
Test name
Test status
Simulation time 2033619035 ps
CPU time 39.3 seconds
Started Aug 23 03:53:16 PM UTC 24
Finished Aug 23 03:53:57 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608585876 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1608585876
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_back_pressure.368758406
Short name T8
Test name
Test status
Simulation time 1584033795 ps
CPU time 79.58 seconds
Started Aug 23 03:53:46 PM UTC 24
Finished Aug 23 03:55:08 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368758406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.368758406
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_back_pressure.3278218029
Short name T53
Test name
Test status
Simulation time 1562647068 ps
CPU time 76.49 seconds
Started Aug 23 04:13:24 PM UTC 24
Finished Aug 23 04:14:43 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278218029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3278218029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_stress_all_with_rand_reset.2325498972
Short name T12
Test name
Test status
Simulation time 9275454963 ps
CPU time 45.2 seconds
Started Aug 23 04:05:39 PM UTC 24
Finished Aug 23 04:06:25 PM UTC 24
Peak memory 215896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23254989
72 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2325498972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_aliasing.1402590634
Short name T104
Test name
Test status
Simulation time 1245079649 ps
CPU time 5.11 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:01:02 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402590634 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1402590634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_bit_bash.2339350932
Short name T545
Test name
Test status
Simulation time 2149408915 ps
CPU time 14.05 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:01:11 PM UTC 24
Peak memory 208068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339350932 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2339350932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1144226119
Short name T72
Test name
Test status
Simulation time 325797632 ps
CPU time 1.15 seconds
Started Aug 23 05:00:57 PM UTC 24
Finished Aug 23 05:00:59 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1144226119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_r
eset.1144226119
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_intr_test.2516509437
Short name T531
Test name
Test status
Simulation time 13989727 ps
CPU time 0.52 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:00:57 PM UTC 24
Peak memory 204724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516509437 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2516509437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1105643535
Short name T86
Test name
Test status
Simulation time 94478647 ps
CPU time 0.99 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:00:58 PM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105643535 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.1105643535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/0.hmac_tl_errors.2292386053
Short name T71
Test name
Test status
Simulation time 92870506 ps
CPU time 2.05 seconds
Started Aug 23 05:00:56 PM UTC 24
Finished Aug 23 05:00:59 PM UTC 24
Peak memory 207812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292386053 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2292386053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_aliasing.855602574
Short name T105
Test name
Test status
Simulation time 607904064 ps
CPU time 5.31 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:05 PM UTC 24
Peak memory 207600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855602574 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.855602574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_bit_bash.4220761955
Short name T550
Test name
Test status
Simulation time 5470404137 ps
CPU time 14.2 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220761955 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4220761955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_hw_reset.2462056051
Short name T87
Test name
Test status
Simulation time 56250486 ps
CPU time 0.64 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:00 PM UTC 24
Peak memory 207024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462056051 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2462056051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3984494404
Short name T74
Test name
Test status
Simulation time 60785392 ps
CPU time 1.49 seconds
Started Aug 23 05:00:59 PM UTC 24
Finished Aug 23 05:01:02 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3984494404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_r
eset.3984494404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_csr_rw.1777272319
Short name T117
Test name
Test status
Simulation time 24194122 ps
CPU time 0.62 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:00 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777272319 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1777272319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_intr_test.2743462287
Short name T533
Test name
Test status
Simulation time 33582963 ps
CPU time 0.49 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:00 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743462287 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2743462287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1940214111
Short name T118
Test name
Test status
Simulation time 58921123 ps
CPU time 1.11 seconds
Started Aug 23 05:00:59 PM UTC 24
Finished Aug 23 05:01:01 PM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940214111 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_outstanding.1940214111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_errors.2633663072
Short name T73
Test name
Test status
Simulation time 537032422 ps
CPU time 2.69 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:02 PM UTC 24
Peak memory 207992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633663072 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2633663072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/1.hmac_tl_intg_err.3949877314
Short name T69
Test name
Test status
Simulation time 985275268 ps
CPU time 3.71 seconds
Started Aug 23 05:00:58 PM UTC 24
Finished Aug 23 05:01:03 PM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949877314 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3949877314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.926897744
Short name T579
Test name
Test status
Simulation time 90920011 ps
CPU time 1.29 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 206388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=926897744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_r
eset.926897744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_csr_rw.870287162
Short name T578
Test name
Test status
Simulation time 37743261 ps
CPU time 0.82 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 206716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870287162 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.870287162
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_intr_test.3916927887
Short name T571
Test name
Test status
Simulation time 30233911 ps
CPU time 0.52 seconds
Started Aug 23 05:01:19 PM UTC 24
Finished Aug 23 05:01:20 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916927887 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3916927887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1020326382
Short name T580
Test name
Test status
Simulation time 139846302 ps
CPU time 1.47 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020326382 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_outstanding.1020326382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_errors.711693693
Short name T574
Test name
Test status
Simulation time 207166274 ps
CPU time 1.42 seconds
Started Aug 23 05:01:18 PM UTC 24
Finished Aug 23 05:01:21 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711693693 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.711693693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/10.hmac_tl_intg_err.4179529176
Short name T138
Test name
Test status
Simulation time 210740009 ps
CPU time 1.68 seconds
Started Aug 23 05:01:19 PM UTC 24
Finished Aug 23 05:01:21 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179529176 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.4179529176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3949193370
Short name T585
Test name
Test status
Simulation time 66119578 ps
CPU time 1.41 seconds
Started Aug 23 05:01:21 PM UTC 24
Finished Aug 23 05:01:24 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3949193370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_
reset.3949193370
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_csr_rw.3097269344
Short name T583
Test name
Test status
Simulation time 30347949 ps
CPU time 0.88 seconds
Started Aug 23 05:01:21 PM UTC 24
Finished Aug 23 05:01:23 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097269344 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3097269344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_intr_test.78184179
Short name T576
Test name
Test status
Simulation time 21520271 ps
CPU time 0.48 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78184179 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.78184179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3693125131
Short name T584
Test name
Test status
Simulation time 88267882 ps
CPU time 1.01 seconds
Started Aug 23 05:01:21 PM UTC 24
Finished Aug 23 05:01:23 PM UTC 24
Peak memory 206548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693125131 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr_outstanding.3693125131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_errors.3659396058
Short name T582
Test name
Test status
Simulation time 90493985 ps
CPU time 1.64 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:23 PM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659396058 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3659396058
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/11.hmac_tl_intg_err.1232043100
Short name T581
Test name
Test status
Simulation time 101527531 ps
CPU time 1.62 seconds
Started Aug 23 05:01:20 PM UTC 24
Finished Aug 23 05:01:23 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232043100 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1232043100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.454714951
Short name T587
Test name
Test status
Simulation time 522162084 ps
CPU time 1.66 seconds
Started Aug 23 05:01:23 PM UTC 24
Finished Aug 23 05:01:25 PM UTC 24
Peak memory 205260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=454714951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_r
eset.454714951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_csr_rw.3040182265
Short name T113
Test name
Test status
Simulation time 123531384 ps
CPU time 0.81 seconds
Started Aug 23 05:01:22 PM UTC 24
Finished Aug 23 05:01:24 PM UTC 24
Peak memory 203952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040182265 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3040182265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_intr_test.3553395151
Short name T532
Test name
Test status
Simulation time 72115413 ps
CPU time 0.49 seconds
Started Aug 23 05:01:22 PM UTC 24
Finished Aug 23 05:01:24 PM UTC 24
Peak memory 204720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553395151 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3553395151
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_same_csr_outstanding.4269090039
Short name T586
Test name
Test status
Simulation time 61867360 ps
CPU time 1.07 seconds
Started Aug 23 05:01:22 PM UTC 24
Finished Aug 23 05:01:25 PM UTC 24
Peak memory 206792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269090039 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr_outstanding.4269090039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_errors.3504315233
Short name T595
Test name
Test status
Simulation time 958407159 ps
CPU time 4.14 seconds
Started Aug 23 05:01:22 PM UTC 24
Finished Aug 23 05:01:28 PM UTC 24
Peak memory 206992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504315233 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3504315233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/12.hmac_tl_intg_err.3624398128
Short name T142
Test name
Test status
Simulation time 3105207339 ps
CPU time 3.7 seconds
Started Aug 23 05:01:22 PM UTC 24
Finished Aug 23 05:01:27 PM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624398128 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3624398128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2189111192
Short name T592
Test name
Test status
Simulation time 286909049 ps
CPU time 1.86 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:27 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2189111192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_
reset.2189111192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_csr_rw.815524696
Short name T589
Test name
Test status
Simulation time 17377658 ps
CPU time 0.61 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:26 PM UTC 24
Peak memory 206520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815524696 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.815524696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_intr_test.3303478155
Short name T588
Test name
Test status
Simulation time 76528873 ps
CPU time 0.5 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:25 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303478155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3303478155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_same_csr_outstanding.625215299
Short name T593
Test name
Test status
Simulation time 136144179 ps
CPU time 2.14 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:27 PM UTC 24
Peak memory 207744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625215299 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr_outstanding.625215299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_errors.2584014375
Short name T596
Test name
Test status
Simulation time 90369179 ps
CPU time 4.06 seconds
Started Aug 23 05:01:23 PM UTC 24
Finished Aug 23 05:01:28 PM UTC 24
Peak memory 207852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584014375 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2584014375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/13.hmac_tl_intg_err.1527163729
Short name T141
Test name
Test status
Simulation time 839408034 ps
CPU time 1.69 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:26 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527163729 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1527163729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2525386897
Short name T602
Test name
Test status
Simulation time 511194306 ps
CPU time 2.1 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:32 PM UTC 24
Peak memory 218224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2525386897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_
reset.2525386897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_csr_rw.132011636
Short name T591
Test name
Test status
Simulation time 12567749 ps
CPU time 0.58 seconds
Started Aug 23 05:01:25 PM UTC 24
Finished Aug 23 05:01:27 PM UTC 24
Peak memory 206700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132011636 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.132011636
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_intr_test.319897052
Short name T590
Test name
Test status
Simulation time 33749901 ps
CPU time 0.48 seconds
Started Aug 23 05:01:25 PM UTC 24
Finished Aug 23 05:01:27 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319897052 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.319897052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1097437341
Short name T594
Test name
Test status
Simulation time 441293856 ps
CPU time 1.46 seconds
Started Aug 23 05:01:25 PM UTC 24
Finished Aug 23 05:01:28 PM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097437341 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr_outstanding.1097437341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_errors.2599216895
Short name T597
Test name
Test status
Simulation time 513409588 ps
CPU time 2.79 seconds
Started Aug 23 05:01:24 PM UTC 24
Finished Aug 23 05:01:28 PM UTC 24
Peak memory 208056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599216895 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2599216895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/14.hmac_tl_intg_err.2281456783
Short name T144
Test name
Test status
Simulation time 582794366 ps
CPU time 1.57 seconds
Started Aug 23 05:01:25 PM UTC 24
Finished Aug 23 05:01:28 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281456783 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2281456783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1256420688
Short name T601
Test name
Test status
Simulation time 66293710 ps
CPU time 1.56 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:31 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1256420688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_
reset.1256420688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_csr_rw.3605164840
Short name T114
Test name
Test status
Simulation time 15591645 ps
CPU time 0.6 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:30 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605164840 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3605164840
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_intr_test.1914154254
Short name T598
Test name
Test status
Simulation time 13578184 ps
CPU time 0.58 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:30 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914154254 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1914154254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1302476332
Short name T603
Test name
Test status
Simulation time 103662333 ps
CPU time 1.9 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:32 PM UTC 24
Peak memory 206728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302476332 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr_outstanding.1302476332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_errors.3092301147
Short name T609
Test name
Test status
Simulation time 310451674 ps
CPU time 3.24 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:33 PM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092301147 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3092301147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/15.hmac_tl_intg_err.2720102662
Short name T610
Test name
Test status
Simulation time 926860160 ps
CPU time 3.59 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:33 PM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720102662 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2720102662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1114130036
Short name T604
Test name
Test status
Simulation time 152371682 ps
CPU time 1.72 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:32 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1114130036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_
reset.1114130036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_csr_rw.2731947647
Short name T115
Test name
Test status
Simulation time 31667275 ps
CPU time 0.7 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:31 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731947647 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2731947647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_intr_test.3100420172
Short name T599
Test name
Test status
Simulation time 12182619 ps
CPU time 0.52 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:31 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100420172 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3100420172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1425184603
Short name T606
Test name
Test status
Simulation time 229945101 ps
CPU time 2.08 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:32 PM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425184603 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr_outstanding.1425184603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_errors.3581393335
Short name T608
Test name
Test status
Simulation time 666377130 ps
CPU time 2.86 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:33 PM UTC 24
Peak memory 207796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581393335 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3581393335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/16.hmac_tl_intg_err.2346101198
Short name T143
Test name
Test status
Simulation time 461203149 ps
CPU time 3.64 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:34 PM UTC 24
Peak memory 207656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346101198 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2346101198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2115542383
Short name T611
Test name
Test status
Simulation time 110400989 ps
CPU time 1.55 seconds
Started Aug 23 05:01:31 PM UTC 24
Finished Aug 23 05:01:34 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2115542383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_
reset.2115542383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_csr_rw.3106710197
Short name T116
Test name
Test status
Simulation time 40244079 ps
CPU time 0.62 seconds
Started Aug 23 05:01:31 PM UTC 24
Finished Aug 23 05:01:33 PM UTC 24
Peak memory 205716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106710197 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3106710197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_intr_test.3035587784
Short name T607
Test name
Test status
Simulation time 11981085 ps
CPU time 0.51 seconds
Started Aug 23 05:01:31 PM UTC 24
Finished Aug 23 05:01:33 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035587784 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3035587784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1725163240
Short name T613
Test name
Test status
Simulation time 604432903 ps
CPU time 2.1 seconds
Started Aug 23 05:01:31 PM UTC 24
Finished Aug 23 05:01:35 PM UTC 24
Peak memory 207936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725163240 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr_outstanding.1725163240
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_errors.1487747493
Short name T600
Test name
Test status
Simulation time 327851790 ps
CPU time 1.2 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:31 PM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487747493 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1487747493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/17.hmac_tl_intg_err.2436119330
Short name T605
Test name
Test status
Simulation time 347336704 ps
CPU time 1.67 seconds
Started Aug 23 05:01:29 PM UTC 24
Finished Aug 23 05:01:32 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436119330 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2436119330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.461934427
Short name T615
Test name
Test status
Simulation time 144926861 ps
CPU time 1.06 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:35 PM UTC 24
Peak memory 206484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=461934427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_r
eset.461934427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_csr_rw.624937242
Short name T614
Test name
Test status
Simulation time 51428036 ps
CPU time 0.82 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:35 PM UTC 24
Peak memory 206480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624937242 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.624937242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_intr_test.3727917430
Short name T612
Test name
Test status
Simulation time 13473164 ps
CPU time 0.54 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:34 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727917430 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3727917430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_same_csr_outstanding.853314095
Short name T616
Test name
Test status
Simulation time 373705919 ps
CPU time 1.77 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:36 PM UTC 24
Peak memory 206204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853314095 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr_outstanding.853314095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_errors.3347181916
Short name T622
Test name
Test status
Simulation time 267232534 ps
CPU time 3.17 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 207720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347181916 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3347181916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/18.hmac_tl_intg_err.773148621
Short name T139
Test name
Test status
Simulation time 128119332 ps
CPU time 3.37 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773148621 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.773148621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3692629836
Short name T619
Test name
Test status
Simulation time 541730801 ps
CPU time 1.38 seconds
Started Aug 23 05:01:34 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3692629836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_
reset.3692629836
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_csr_rw.1437108186
Short name T618
Test name
Test status
Simulation time 96786190 ps
CPU time 0.71 seconds
Started Aug 23 05:01:34 PM UTC 24
Finished Aug 23 05:01:36 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437108186 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1437108186
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_intr_test.4044555917
Short name T617
Test name
Test status
Simulation time 18136922 ps
CPU time 0.52 seconds
Started Aug 23 05:01:34 PM UTC 24
Finished Aug 23 05:01:36 PM UTC 24
Peak memory 203656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044555917 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4044555917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3967140661
Short name T621
Test name
Test status
Simulation time 441022360 ps
CPU time 1.64 seconds
Started Aug 23 05:01:34 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 206800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967140661 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr_outstanding.3967140661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_errors.1205987389
Short name T620
Test name
Test status
Simulation time 337260506 ps
CPU time 2.86 seconds
Started Aug 23 05:01:33 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 207864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205987389 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1205987389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/19.hmac_tl_intg_err.3746071634
Short name T629
Test name
Test status
Simulation time 962070297 ps
CPU time 2.57 seconds
Started Aug 23 05:01:34 PM UTC 24
Finished Aug 23 05:01:38 PM UTC 24
Peak memory 207644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746071634 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3746071634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_aliasing.3860478376
Short name T107
Test name
Test status
Simulation time 308862638 ps
CPU time 5.33 seconds
Started Aug 23 05:01:02 PM UTC 24
Finished Aug 23 05:01:09 PM UTC 24
Peak memory 207824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860478376 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3860478376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_bit_bash.606884076
Short name T111
Test name
Test status
Simulation time 111434814 ps
CPU time 4.49 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:07 PM UTC 24
Peak memory 207616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606884076 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.606884076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_hw_reset.1274036007
Short name T535
Test name
Test status
Simulation time 49154634 ps
CPU time 0.65 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:03 PM UTC 24
Peak memory 205752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274036007 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1274036007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4055748269
Short name T537
Test name
Test status
Simulation time 642281461 ps
CPU time 1.06 seconds
Started Aug 23 05:01:02 PM UTC 24
Finished Aug 23 05:01:04 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4055748269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_r
eset.4055748269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_csr_rw.2864692995
Short name T119
Test name
Test status
Simulation time 34212565 ps
CPU time 0.83 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:03 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864692995 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2864692995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_intr_test.2289894932
Short name T534
Test name
Test status
Simulation time 10766390 ps
CPU time 0.49 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:03 PM UTC 24
Peak memory 203468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289894932 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2289894932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_same_csr_outstanding.192882393
Short name T120
Test name
Test status
Simulation time 107590776 ps
CPU time 1.08 seconds
Started Aug 23 05:01:02 PM UTC 24
Finished Aug 23 05:01:04 PM UTC 24
Peak memory 206688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192882393 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_outstanding.192882393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_errors.1479981301
Short name T536
Test name
Test status
Simulation time 99488922 ps
CPU time 1.22 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:03 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479981301 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1479981301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/2.hmac_tl_intg_err.3050337114
Short name T70
Test name
Test status
Simulation time 716556067 ps
CPU time 2.63 seconds
Started Aug 23 05:01:01 PM UTC 24
Finished Aug 23 05:01:05 PM UTC 24
Peak memory 207684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050337114 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3050337114
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/20.hmac_intr_test.3375506724
Short name T625
Test name
Test status
Simulation time 23287476 ps
CPU time 0.49 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375506724 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3375506724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/21.hmac_intr_test.1534524396
Short name T627
Test name
Test status
Simulation time 27317438 ps
CPU time 0.54 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534524396 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1534524396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/22.hmac_intr_test.1738469630
Short name T624
Test name
Test status
Simulation time 25888863 ps
CPU time 0.53 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738469630 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1738469630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/23.hmac_intr_test.2129248771
Short name T623
Test name
Test status
Simulation time 28969690 ps
CPU time 0.53 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129248771 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2129248771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/24.hmac_intr_test.3828145091
Short name T626
Test name
Test status
Simulation time 14396477 ps
CPU time 0.51 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828145091 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3828145091
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/25.hmac_intr_test.2886543713
Short name T628
Test name
Test status
Simulation time 25102158 ps
CPU time 0.5 seconds
Started Aug 23 05:01:35 PM UTC 24
Finished Aug 23 05:01:37 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886543713 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2886543713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/26.hmac_intr_test.860610794
Short name T630
Test name
Test status
Simulation time 17525638 ps
CPU time 0.51 seconds
Started Aug 23 05:01:37 PM UTC 24
Finished Aug 23 05:01:38 PM UTC 24
Peak memory 203592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860610794 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.860610794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/27.hmac_intr_test.1815185128
Short name T632
Test name
Test status
Simulation time 15431237 ps
CPU time 0.53 seconds
Started Aug 23 05:01:37 PM UTC 24
Finished Aug 23 05:01:38 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815185128 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1815185128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/28.hmac_intr_test.114318434
Short name T631
Test name
Test status
Simulation time 12679790 ps
CPU time 0.52 seconds
Started Aug 23 05:01:37 PM UTC 24
Finished Aug 23 05:01:38 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114318434 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.114318434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/29.hmac_intr_test.2442296403
Short name T635
Test name
Test status
Simulation time 24267065 ps
CPU time 0.49 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442296403 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2442296403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_aliasing.4275049936
Short name T552
Test name
Test status
Simulation time 1743380579 ps
CPU time 7 seconds
Started Aug 23 05:01:06 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 207292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275049936 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4275049936
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_bit_bash.3274720661
Short name T544
Test name
Test status
Simulation time 365213429 ps
CPU time 4.84 seconds
Started Aug 23 05:01:04 PM UTC 24
Finished Aug 23 05:01:10 PM UTC 24
Peak memory 207612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274720661 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3274720661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_hw_reset.915958125
Short name T539
Test name
Test status
Simulation time 98450577 ps
CPU time 0.66 seconds
Started Aug 23 05:01:03 PM UTC 24
Finished Aug 23 05:01:05 PM UTC 24
Peak memory 205924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915958125 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.915958125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1937648203
Short name T541
Test name
Test status
Simulation time 212022975 ps
CPU time 1.4 seconds
Started Aug 23 05:01:06 PM UTC 24
Finished Aug 23 05:01:08 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1937648203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_r
eset.1937648203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_csr_rw.3325853562
Short name T106
Test name
Test status
Simulation time 31082982 ps
CPU time 0.76 seconds
Started Aug 23 05:01:03 PM UTC 24
Finished Aug 23 05:01:05 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325853562 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3325853562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_intr_test.3865769259
Short name T538
Test name
Test status
Simulation time 122995499 ps
CPU time 0.49 seconds
Started Aug 23 05:01:03 PM UTC 24
Finished Aug 23 05:01:05 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865769259 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3865769259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_same_csr_outstanding.54285291
Short name T121
Test name
Test status
Simulation time 1589244314 ps
CPU time 1.57 seconds
Started Aug 23 05:01:06 PM UTC 24
Finished Aug 23 05:01:08 PM UTC 24
Peak memory 206252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54285291 -assert nopostproc +UVM_
TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_outstanding.54285291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_errors.4117496507
Short name T540
Test name
Test status
Simulation time 605491346 ps
CPU time 1.64 seconds
Started Aug 23 05:01:03 PM UTC 24
Finished Aug 23 05:01:06 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117496507 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4117496507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/3.hmac_tl_intg_err.1034138872
Short name T135
Test name
Test status
Simulation time 957698976 ps
CPU time 3.69 seconds
Started Aug 23 05:01:03 PM UTC 24
Finished Aug 23 05:01:08 PM UTC 24
Peak memory 207668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034138872 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1034138872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/30.hmac_intr_test.2995919175
Short name T636
Test name
Test status
Simulation time 32592979 ps
CPU time 0.52 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995919175 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2995919175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/31.hmac_intr_test.151357084
Short name T633
Test name
Test status
Simulation time 30327199 ps
CPU time 0.54 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151357084 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.151357084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/32.hmac_intr_test.1775580496
Short name T639
Test name
Test status
Simulation time 22408567 ps
CPU time 0.49 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775580496 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1775580496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/33.hmac_intr_test.695848881
Short name T634
Test name
Test status
Simulation time 24871199 ps
CPU time 0.51 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695848881 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.695848881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/34.hmac_intr_test.2763876077
Short name T638
Test name
Test status
Simulation time 23351691 ps
CPU time 0.56 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763876077 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2763876077
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/35.hmac_intr_test.4006910130
Short name T637
Test name
Test status
Simulation time 40628369 ps
CPU time 0.51 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006910130 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.4006910130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/36.hmac_intr_test.439680798
Short name T640
Test name
Test status
Simulation time 13897358 ps
CPU time 0.55 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439680798 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.439680798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/37.hmac_intr_test.1463659140
Short name T641
Test name
Test status
Simulation time 25266852 ps
CPU time 0.53 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463659140 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1463659140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/38.hmac_intr_test.42523221
Short name T642
Test name
Test status
Simulation time 18223806 ps
CPU time 0.54 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42523221 -assert nopostproc +UVM_TESTNAME=hmac_base_te
st +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim
-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.42523221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/39.hmac_intr_test.1510938023
Short name T643
Test name
Test status
Simulation time 59772364 ps
CPU time 0.53 seconds
Started Aug 23 05:01:38 PM UTC 24
Finished Aug 23 05:01:40 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510938023 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1510938023
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_aliasing.4238178551
Short name T112
Test name
Test status
Simulation time 302596853 ps
CPU time 5.12 seconds
Started Aug 23 05:01:09 PM UTC 24
Finished Aug 23 05:01:16 PM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238178551 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.4238178551
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_bit_bash.2491399760
Short name T555
Test name
Test status
Simulation time 378232569 ps
CPU time 4.96 seconds
Started Aug 23 05:01:08 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491399760 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2491399760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_hw_reset.4203909000
Short name T109
Test name
Test status
Simulation time 24198334 ps
CPU time 0.72 seconds
Started Aug 23 05:01:07 PM UTC 24
Finished Aug 23 05:01:09 PM UTC 24
Peak memory 206396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203909000 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4203909000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3069801678
Short name T549
Test name
Test status
Simulation time 120602336 ps
CPU time 1.44 seconds
Started Aug 23 05:01:09 PM UTC 24
Finished Aug 23 05:01:12 PM UTC 24
Peak memory 206604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3069801678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_r
eset.3069801678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_csr_rw.2119830855
Short name T108
Test name
Test status
Simulation time 95667692 ps
CPU time 0.59 seconds
Started Aug 23 05:01:07 PM UTC 24
Finished Aug 23 05:01:09 PM UTC 24
Peak memory 206608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119830855 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2119830855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_intr_test.590639749
Short name T542
Test name
Test status
Simulation time 14135082 ps
CPU time 0.54 seconds
Started Aug 23 05:01:07 PM UTC 24
Finished Aug 23 05:01:09 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590639749 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.590639749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_same_csr_outstanding.198627590
Short name T122
Test name
Test status
Simulation time 129664364 ps
CPU time 1.5 seconds
Started Aug 23 05:01:09 PM UTC 24
Finished Aug 23 05:01:12 PM UTC 24
Peak memory 206244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198627590 -assert nopostproc +UVM
_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_outstanding.198627590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_errors.682567677
Short name T543
Test name
Test status
Simulation time 262379822 ps
CPU time 3.05 seconds
Started Aug 23 05:01:06 PM UTC 24
Finished Aug 23 05:01:10 PM UTC 24
Peak memory 207800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682567677 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.682567677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/4.hmac_tl_intg_err.4208657705
Short name T140
Test name
Test status
Simulation time 161801453 ps
CPU time 1.58 seconds
Started Aug 23 05:01:06 PM UTC 24
Finished Aug 23 05:01:08 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208657705 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.4208657705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/40.hmac_intr_test.3811083097
Short name T647
Test name
Test status
Simulation time 32739697 ps
CPU time 0.58 seconds
Started Aug 23 05:01:40 PM UTC 24
Finished Aug 23 05:01:42 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811083097 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3811083097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/41.hmac_intr_test.2568757526
Short name T646
Test name
Test status
Simulation time 43898861 ps
CPU time 0.54 seconds
Started Aug 23 05:01:40 PM UTC 24
Finished Aug 23 05:01:42 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568757526 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2568757526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/42.hmac_intr_test.1876807037
Short name T644
Test name
Test status
Simulation time 23726329 ps
CPU time 0.49 seconds
Started Aug 23 05:01:40 PM UTC 24
Finished Aug 23 05:01:41 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876807037 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1876807037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/43.hmac_intr_test.2275025024
Short name T645
Test name
Test status
Simulation time 36510930 ps
CPU time 0.55 seconds
Started Aug 23 05:01:40 PM UTC 24
Finished Aug 23 05:01:41 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275025024 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2275025024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/44.hmac_intr_test.3093662792
Short name T648
Test name
Test status
Simulation time 16387303 ps
CPU time 0.5 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093662792 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3093662792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/45.hmac_intr_test.1448723383
Short name T649
Test name
Test status
Simulation time 43017854 ps
CPU time 0.55 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448723383 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1448723383
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/46.hmac_intr_test.2707698755
Short name T650
Test name
Test status
Simulation time 14042884 ps
CPU time 0.52 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707698755 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2707698755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/47.hmac_intr_test.1842475444
Short name T651
Test name
Test status
Simulation time 24621957 ps
CPU time 0.53 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842475444 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1842475444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/48.hmac_intr_test.1832311300
Short name T653
Test name
Test status
Simulation time 14215739 ps
CPU time 0.55 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832311300 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1832311300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/49.hmac_intr_test.2064825895
Short name T652
Test name
Test status
Simulation time 27957916 ps
CPU time 0.52 seconds
Started Aug 23 05:01:41 PM UTC 24
Finished Aug 23 05:01:43 PM UTC 24
Peak memory 203660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064825895 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2064825895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3486177048
Short name T551
Test name
Test status
Simulation time 72451341 ps
CPU time 1.27 seconds
Started Aug 23 05:01:11 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3486177048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_r
eset.3486177048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_csr_rw.30418348
Short name T548
Test name
Test status
Simulation time 20261740 ps
CPU time 0.62 seconds
Started Aug 23 05:01:10 PM UTC 24
Finished Aug 23 05:01:12 PM UTC 24
Peak memory 207000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30418348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.30418348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_intr_test.893839039
Short name T547
Test name
Test status
Simulation time 23337875 ps
CPU time 0.48 seconds
Started Aug 23 05:01:10 PM UTC 24
Finished Aug 23 05:01:12 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893839039 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.893839039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_same_csr_outstanding.709378
Short name T123
Test name
Test status
Simulation time 689216756 ps
CPU time 2.41 seconds
Started Aug 23 05:01:10 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 207916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709378 -assert nopostproc +UVM_TE
STNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_outstanding.709378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/5.hmac_tl_errors.3166553296
Short name T546
Test name
Test status
Simulation time 33760601 ps
CPU time 1.1 seconds
Started Aug 23 05:01:09 PM UTC 24
Finished Aug 23 05:01:12 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166553296 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.3166553296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3080087624
Short name T556
Test name
Test status
Simulation time 79647528 ps
CPU time 0.96 seconds
Started Aug 23 05:01:13 PM UTC 24
Finished Aug 23 05:01:16 PM UTC 24
Peak memory 206316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3080087624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_r
eset.3080087624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_csr_rw.3069550928
Short name T110
Test name
Test status
Simulation time 25171559 ps
CPU time 0.66 seconds
Started Aug 23 05:01:12 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069550928 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3069550928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_intr_test.1924390046
Short name T553
Test name
Test status
Simulation time 15878983 ps
CPU time 0.47 seconds
Started Aug 23 05:01:12 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924390046 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.1924390046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_same_csr_outstanding.4271490569
Short name T557
Test name
Test status
Simulation time 52288657 ps
CPU time 1.02 seconds
Started Aug 23 05:01:13 PM UTC 24
Finished Aug 23 05:01:16 PM UTC 24
Peak memory 206520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271490569 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.4271490569
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/6.hmac_tl_errors.1061273108
Short name T554
Test name
Test status
Simulation time 175375838 ps
CPU time 1.78 seconds
Started Aug 23 05:01:11 PM UTC 24
Finished Aug 23 05:01:14 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061273108 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1061273108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.525363768
Short name T564
Test name
Test status
Simulation time 274520355 ps
CPU time 1.51 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:18 PM UTC 24
Peak memory 206576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=525363768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_re
set.525363768
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_csr_rw.2875372287
Short name T558
Test name
Test status
Simulation time 13268412 ps
CPU time 0.61 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:17 PM UTC 24
Peak memory 206132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875372287 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2875372287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_intr_test.879077523
Short name T560
Test name
Test status
Simulation time 21809644 ps
CPU time 0.51 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:17 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879077523 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.879077523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2514841985
Short name T562
Test name
Test status
Simulation time 35059518 ps
CPU time 1.39 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:18 PM UTC 24
Peak memory 206736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514841985 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_outstanding.2514841985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_errors.3901653097
Short name T559
Test name
Test status
Simulation time 114129292 ps
CPU time 1.97 seconds
Started Aug 23 05:01:13 PM UTC 24
Finished Aug 23 05:01:17 PM UTC 24
Peak memory 206612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901653097 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3901653097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/7.hmac_tl_intg_err.3832600264
Short name T136
Test name
Test status
Simulation time 270463523 ps
CPU time 2.75 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:19 PM UTC 24
Peak memory 207748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832600264 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3832600264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.1349540772
Short name T569
Test name
Test status
Simulation time 135018920 ps
CPU time 0.99 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:19 PM UTC 24
Peak memory 206544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1349540772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_r
eset.1349540772
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_csr_rw.1634409098
Short name T563
Test name
Test status
Simulation time 58287542 ps
CPU time 0.6 seconds
Started Aug 23 05:01:16 PM UTC 24
Finished Aug 23 05:01:18 PM UTC 24
Peak memory 205836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634409098 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1634409098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_intr_test.1615921102
Short name T561
Test name
Test status
Simulation time 14286407 ps
CPU time 0.53 seconds
Started Aug 23 05:01:16 PM UTC 24
Finished Aug 23 05:01:17 PM UTC 24
Peak memory 203604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615921102 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1615921102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2736605018
Short name T570
Test name
Test status
Simulation time 88219892 ps
CPU time 1.45 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:20 PM UTC 24
Peak memory 206540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736605018 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr_outstanding.2736605018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_errors.2645106915
Short name T565
Test name
Test status
Simulation time 102507212 ps
CPU time 2.33 seconds
Started Aug 23 05:01:15 PM UTC 24
Finished Aug 23 05:01:18 PM UTC 24
Peak memory 208060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645106915 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2645106915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/8.hmac_tl_intg_err.1995860861
Short name T566
Test name
Test status
Simulation time 80965614 ps
CPU time 1.53 seconds
Started Aug 23 05:01:16 PM UTC 24
Finished Aug 23 05:01:19 PM UTC 24
Peak memory 206600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995860861 -assert nopostproc +UVM_TESTNAM
E=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1995860861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3454240074
Short name T572
Test name
Test status
Simulation time 295525905 ps
CPU time 1.03 seconds
Started Aug 23 05:01:18 PM UTC 24
Finished Aug 23 05:01:21 PM UTC 24
Peak memory 205968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb
=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3454240074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_r
eset.3454240074
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_csr_rw.1655592760
Short name T568
Test name
Test status
Simulation time 51432375 ps
CPU time 0.59 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:19 PM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655592760 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1655592760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_intr_test.305887858
Short name T567
Test name
Test status
Simulation time 33178629 ps
CPU time 0.54 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:19 PM UTC 24
Peak memory 203600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305887858 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-si
m-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.305887858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3190328775
Short name T575
Test name
Test status
Simulation time 281823583 ps
CPU time 1.99 seconds
Started Aug 23 05:01:18 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 206676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190328775 -assert nopostproc +UV
M_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr_outstanding.3190328775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_errors.4113426489
Short name T573
Test name
Test status
Simulation time 62170004 ps
CPU time 2.72 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:21 PM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4113426489 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.4113426489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/cover_reg_top/9.hmac_tl_intg_err.205394806
Short name T577
Test name
Test status
Simulation time 689769401 ps
CPU time 3.43 seconds
Started Aug 23 05:01:17 PM UTC 24
Finished Aug 23 05:01:22 PM UTC 24
Peak memory 207940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205394806 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/hmac-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.205394806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_back_pressure.3765526850
Short name T6
Test name
Test status
Simulation time 771861644 ps
CPU time 38.39 seconds
Started Aug 23 03:53:12 PM UTC 24
Finished Aug 23 03:53:52 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765526850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3765526850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_burst_wr.696793013
Short name T2
Test name
Test status
Simulation time 1001402450 ps
CPU time 11.83 seconds
Started Aug 23 03:53:13 PM UTC 24
Finished Aug 23 03:53:26 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696793013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.696793013
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_datapath_stress.424640563
Short name T9
Test name
Test status
Simulation time 3614356969 ps
CPU time 120.68 seconds
Started Aug 23 03:53:13 PM UTC 24
Finished Aug 23 03:55:16 PM UTC 24
Peak memory 459176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424640563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.424640563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_error.57648127
Short name T31
Test name
Test status
Simulation time 8013819233 ps
CPU time 96.13 seconds
Started Aug 23 03:53:13 PM UTC 24
Finished Aug 23 03:54:52 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57648127 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.57648127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_long_msg.2605163684
Short name T3
Test name
Test status
Simulation time 3333672448 ps
CPU time 15.34 seconds
Started Aug 23 03:53:12 PM UTC 24
Finished Aug 23 03:53:29 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605163684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2605163684
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_smoke.2122043157
Short name T1
Test name
Test status
Simulation time 648910412 ps
CPU time 7.61 seconds
Started Aug 23 03:53:12 PM UTC 24
Finished Aug 23 03:53:21 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122043157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2122043157
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_hmac384_vectors.2599890022
Short name T30
Test name
Test status
Simulation time 8955849252 ps
CPU time 51.03 seconds
Started Aug 23 03:53:16 PM UTC 24
Finished Aug 23 03:54:08 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599890022 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2599890022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_hmac512_vectors.2527397286
Short name T56
Test name
Test status
Simulation time 15088823310 ps
CPU time 111.74 seconds
Started Aug 23 03:53:16 PM UTC 24
Finished Aug 23 03:55:10 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527397286 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2527397286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_sha256_vectors.2650159475
Short name T148
Test name
Test status
Simulation time 43727377997 ps
CPU time 495.55 seconds
Started Aug 23 03:53:13 PM UTC 24
Finished Aug 23 04:01:35 PM UTC 24
Peak memory 210988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650159475 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2650159475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_sha384_vectors.828846068
Short name T277
Test name
Test status
Simulation time 212728715170 ps
CPU time 2334.97 seconds
Started Aug 23 03:53:14 PM UTC 24
Finished Aug 23 04:32:31 PM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828846068 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.828846068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/0.hmac_test_sha512_vectors.4042464256
Short name T251
Test name
Test status
Simulation time 559641349533 ps
CPU time 2030.67 seconds
Started Aug 23 03:53:14 PM UTC 24
Finished Aug 23 04:27:24 PM UTC 24
Peak memory 221308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042464256 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.4042464256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/0.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_alert_test.1977571339
Short name T60
Test name
Test status
Simulation time 40803823 ps
CPU time 0.49 seconds
Started Aug 23 03:55:56 PM UTC 24
Finished Aug 23 03:55:57 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977571339 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1977571339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_burst_wr.3052407283
Short name T22
Test name
Test status
Simulation time 2160156321 ps
CPU time 7.67 seconds
Started Aug 23 03:53:53 PM UTC 24
Finished Aug 23 03:54:02 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052407283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3052407283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_error.3972786904
Short name T58
Test name
Test status
Simulation time 121403855212 ps
CPU time 173.95 seconds
Started Aug 23 03:53:56 PM UTC 24
Finished Aug 23 03:56:53 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972786904 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3972786904
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_long_msg.2427184519
Short name T5
Test name
Test status
Simulation time 149005484 ps
CPU time 7.11 seconds
Started Aug 23 03:53:40 PM UTC 24
Finished Aug 23 03:53:49 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427184519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2427184519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_sec_cm.360948458
Short name T64
Test name
Test status
Simulation time 43283170 ps
CPU time 0.72 seconds
Started Aug 23 03:55:54 PM UTC 24
Finished Aug 23 03:55:56 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360948458 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.360948458
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_hmac256_vectors.3768293277
Short name T57
Test name
Test status
Simulation time 19606001525 ps
CPU time 67.33 seconds
Started Aug 23 03:54:53 PM UTC 24
Finished Aug 23 03:56:02 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768293277 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3768293277
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_hmac384_vectors.3539550237
Short name T169
Test name
Test status
Simulation time 4496268084 ps
CPU time 73.58 seconds
Started Aug 23 03:55:09 PM UTC 24
Finished Aug 23 03:56:24 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539550237 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3539550237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_hmac512_vectors.2421602145
Short name T175
Test name
Test status
Simulation time 83439025688 ps
CPU time 113.89 seconds
Started Aug 23 03:55:11 PM UTC 24
Finished Aug 23 03:57:07 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421602145 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2421602145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_sha256_vectors.3488248733
Short name T149
Test name
Test status
Simulation time 164663180989 ps
CPU time 528.75 seconds
Started Aug 23 03:54:02 PM UTC 24
Finished Aug 23 04:02:57 PM UTC 24
Peak memory 207168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488248733 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3488248733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_sha384_vectors.1835742460
Short name T276
Test name
Test status
Simulation time 850610642229 ps
CPU time 2277.73 seconds
Started Aug 23 03:54:09 PM UTC 24
Finished Aug 23 04:32:29 PM UTC 24
Peak memory 221308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835742460 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1835742460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_test_sha512_vectors.502847736
Short name T252
Test name
Test status
Simulation time 135051588958 ps
CPU time 1974.34 seconds
Started Aug 23 03:54:21 PM UTC 24
Finished Aug 23 04:27:34 PM UTC 24
Peak memory 227460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502847736 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.502847736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/1.hmac_wipe_secret.1024198148
Short name T21
Test name
Test status
Simulation time 152259034452 ps
CPU time 113.45 seconds
Started Aug 23 03:53:57 PM UTC 24
Finished Aug 23 03:55:53 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024198148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1024198148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/1.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_alert_test.2894039323
Short name T207
Test name
Test status
Simulation time 37019393 ps
CPU time 0.48 seconds
Started Aug 23 04:11:41 PM UTC 24
Finished Aug 23 04:11:42 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894039323 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2894039323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_back_pressure.338228884
Short name T55
Test name
Test status
Simulation time 2740329753 ps
CPU time 38.12 seconds
Started Aug 23 04:10:34 PM UTC 24
Finished Aug 23 04:11:13 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338228884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.338228884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_burst_wr.1559016799
Short name T162
Test name
Test status
Simulation time 7303290112 ps
CPU time 33.25 seconds
Started Aug 23 04:11:04 PM UTC 24
Finished Aug 23 04:11:39 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559016799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1559016799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_datapath_stress.767681205
Short name T286
Test name
Test status
Simulation time 16412588082 ps
CPU time 1340.19 seconds
Started Aug 23 04:10:36 PM UTC 24
Finished Aug 23 04:33:08 PM UTC 24
Peak memory 799148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767681205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.767681205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_error.53949748
Short name T212
Test name
Test status
Simulation time 37536953739 ps
CPU time 144.81 seconds
Started Aug 23 04:11:06 PM UTC 24
Finished Aug 23 04:13:33 PM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53949748 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.53949748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_long_msg.4233121229
Short name T209
Test name
Test status
Simulation time 166562722539 ps
CPU time 112.94 seconds
Started Aug 23 04:10:33 PM UTC 24
Finished Aug 23 04:12:28 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233121229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4233121229
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_smoke.3261120300
Short name T155
Test name
Test status
Simulation time 734811106 ps
CPU time 2.92 seconds
Started Aug 23 04:10:29 PM UTC 24
Finished Aug 23 04:10:33 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261120300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3261120300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_stress_all.251709797
Short name T208
Test name
Test status
Simulation time 9545425190 ps
CPU time 41.98 seconds
Started Aug 23 04:11:14 PM UTC 24
Finished Aug 23 04:11:58 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251709797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.251709797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/10.hmac_wipe_secret.1061261131
Short name T129
Test name
Test status
Simulation time 2360392889 ps
CPU time 98.57 seconds
Started Aug 23 04:11:12 PM UTC 24
Finished Aug 23 04:12:53 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061261131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1061261131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/10.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_alert_test.2685899172
Short name T211
Test name
Test status
Simulation time 22417080 ps
CPU time 0.5 seconds
Started Aug 23 04:13:16 PM UTC 24
Finished Aug 23 04:13:18 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685899172 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2685899172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_back_pressure.120042207
Short name T156
Test name
Test status
Simulation time 2566781515 ps
CPU time 65.1 seconds
Started Aug 23 04:11:50 PM UTC 24
Finished Aug 23 04:12:57 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120042207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.120042207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_datapath_stress.4270097204
Short name T33
Test name
Test status
Simulation time 3852163770 ps
CPU time 251.3 seconds
Started Aug 23 04:11:58 PM UTC 24
Finished Aug 23 04:16:13 PM UTC 24
Peak memory 508248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270097204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4270097204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_error.255258507
Short name T210
Test name
Test status
Simulation time 1265718866 ps
CPU time 20.38 seconds
Started Aug 23 04:12:54 PM UTC 24
Finished Aug 23 04:13:16 PM UTC 24
Peak memory 207152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255258507 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.255258507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_long_msg.796698713
Short name T213
Test name
Test status
Simulation time 8074620534 ps
CPU time 128.48 seconds
Started Aug 23 04:11:45 PM UTC 24
Finished Aug 23 04:13:56 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796698713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.796698713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_smoke.1436097333
Short name T153
Test name
Test status
Simulation time 1253998686 ps
CPU time 5.61 seconds
Started Aug 23 04:11:43 PM UTC 24
Finished Aug 23 04:11:50 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436097333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1436097333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_stress_all.566251955
Short name T164
Test name
Test status
Simulation time 22413835424 ps
CPU time 1787.89 seconds
Started Aug 23 04:13:11 PM UTC 24
Finished Aug 23 04:43:15 PM UTC 24
Peak memory 780712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566251955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.566251955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/11.hmac_wipe_secret.2843088488
Short name T97
Test name
Test status
Simulation time 7375988011 ps
CPU time 77.23 seconds
Started Aug 23 04:12:58 PM UTC 24
Finished Aug 23 04:14:17 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843088488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2843088488
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/11.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_alert_test.2804147726
Short name T216
Test name
Test status
Simulation time 44781867 ps
CPU time 0.5 seconds
Started Aug 23 04:14:35 PM UTC 24
Finished Aug 23 04:14:37 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804147726 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2804147726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_burst_wr.4175084252
Short name T52
Test name
Test status
Simulation time 471194070 ps
CPU time 5.09 seconds
Started Aug 23 04:13:57 PM UTC 24
Finished Aug 23 04:14:04 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175084252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4175084252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_datapath_stress.76083924
Short name T223
Test name
Test status
Simulation time 3947754000 ps
CPU time 281.86 seconds
Started Aug 23 04:13:35 PM UTC 24
Finished Aug 23 04:18:20 PM UTC 24
Peak memory 686576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76083924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.76083924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_error.3647690385
Short name T220
Test name
Test status
Simulation time 11926820139 ps
CPU time 45.41 seconds
Started Aug 23 04:14:04 PM UTC 24
Finished Aug 23 04:14:52 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647690385 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3647690385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_long_msg.1780155891
Short name T215
Test name
Test status
Simulation time 3015854786 ps
CPU time 74.47 seconds
Started Aug 23 04:13:18 PM UTC 24
Finished Aug 23 04:14:34 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780155891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1780155891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_smoke.140164330
Short name T146
Test name
Test status
Simulation time 697761112 ps
CPU time 5.04 seconds
Started Aug 23 04:13:17 PM UTC 24
Finished Aug 23 04:13:23 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140164330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.140164330
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_stress_all.767847436
Short name T43
Test name
Test status
Simulation time 161932651695 ps
CPU time 1112.19 seconds
Started Aug 23 04:14:33 PM UTC 24
Finished Aug 23 04:33:15 PM UTC 24
Peak memory 694760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767847436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.767847436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/12.hmac_wipe_secret.511443366
Short name T214
Test name
Test status
Simulation time 280676438 ps
CPU time 12.9 seconds
Started Aug 23 04:14:18 PM UTC 24
Finished Aug 23 04:14:32 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511443366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.511443366
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/12.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_alert_test.768191487
Short name T34
Test name
Test status
Simulation time 36243146 ps
CPU time 0.49 seconds
Started Aug 23 04:16:14 PM UTC 24
Finished Aug 23 04:16:15 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768191487 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.768191487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_back_pressure.2414016643
Short name T13
Test name
Test status
Simulation time 404979953 ps
CPU time 20.28 seconds
Started Aug 23 04:14:44 PM UTC 24
Finished Aug 23 04:15:05 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414016643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2414016643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_burst_wr.3123122164
Short name T32
Test name
Test status
Simulation time 1881419126 ps
CPU time 43.81 seconds
Started Aug 23 04:14:47 PM UTC 24
Finished Aug 23 04:15:32 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123122164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3123122164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_datapath_stress.4255042717
Short name T248
Test name
Test status
Simulation time 25224145071 ps
CPU time 681.69 seconds
Started Aug 23 04:14:44 PM UTC 24
Finished Aug 23 04:26:12 PM UTC 24
Peak memory 778496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255042717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.4255042717
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_error.3072822290
Short name T40
Test name
Test status
Simulation time 37789895919 ps
CPU time 165.93 seconds
Started Aug 23 04:14:52 PM UTC 24
Finished Aug 23 04:17:41 PM UTC 24
Peak memory 207216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072822290 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3072822290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_long_msg.58433792
Short name T219
Test name
Test status
Simulation time 895437525 ps
CPU time 3.7 seconds
Started Aug 23 04:14:41 PM UTC 24
Finished Aug 23 04:14:46 PM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58433792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.58433792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_smoke.4283181873
Short name T218
Test name
Test status
Simulation time 501852544 ps
CPU time 5.13 seconds
Started Aug 23 04:14:37 PM UTC 24
Finished Aug 23 04:14:44 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283181873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.4283181873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_stress_all.1799496154
Short name T527
Test name
Test status
Simulation time 153683323553 ps
CPU time 3373.26 seconds
Started Aug 23 04:15:33 PM UTC 24
Finished Aug 23 05:12:16 PM UTC 24
Peak memory 821364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799496154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1799496154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/13.hmac_wipe_secret.2918947615
Short name T36
Test name
Test status
Simulation time 21617308970 ps
CPU time 91.6 seconds
Started Aug 23 04:15:06 PM UTC 24
Finished Aug 23 04:16:40 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918947615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2918947615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/13.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_alert_test.583648275
Short name T224
Test name
Test status
Simulation time 29040792 ps
CPU time 0.49 seconds
Started Aug 23 04:18:20 PM UTC 24
Finished Aug 23 04:18:22 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583648275 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.583648275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_back_pressure.1169265127
Short name T37
Test name
Test status
Simulation time 1257247564 ps
CPU time 32.69 seconds
Started Aug 23 04:16:41 PM UTC 24
Finished Aug 23 04:17:15 PM UTC 24
Peak memory 223704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169265127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1169265127
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_burst_wr.965859559
Short name T221
Test name
Test status
Simulation time 3928367022 ps
CPU time 43.77 seconds
Started Aug 23 04:17:20 PM UTC 24
Finished Aug 23 04:18:05 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965859559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.965859559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_datapath_stress.2026765542
Short name T39
Test name
Test status
Simulation time 216977904 ps
CPU time 17.71 seconds
Started Aug 23 04:17:17 PM UTC 24
Finished Aug 23 04:17:36 PM UTC 24
Peak memory 252052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026765542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2026765542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_error.94009709
Short name T222
Test name
Test status
Simulation time 3690716008 ps
CPU time 41.18 seconds
Started Aug 23 04:17:36 PM UTC 24
Finished Aug 23 04:18:19 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94009709 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.94009709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_long_msg.3705618255
Short name T38
Test name
Test status
Simulation time 1215244460 ps
CPU time 58.68 seconds
Started Aug 23 04:16:19 PM UTC 24
Finished Aug 23 04:17:20 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705618255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3705618255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_smoke.2953370793
Short name T35
Test name
Test status
Simulation time 89221598 ps
CPU time 1.29 seconds
Started Aug 23 04:16:16 PM UTC 24
Finished Aug 23 04:16:19 PM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953370793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2953370793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/14.hmac_wipe_secret.3407935544
Short name T130
Test name
Test status
Simulation time 17808239681 ps
CPU time 65.94 seconds
Started Aug 23 04:17:42 PM UTC 24
Finished Aug 23 04:18:49 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407935544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3407935544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/14.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_alert_test.3800801705
Short name T229
Test name
Test status
Simulation time 18414130 ps
CPU time 0.49 seconds
Started Aug 23 04:19:05 PM UTC 24
Finished Aug 23 04:19:06 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800801705 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3800801705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_back_pressure.2771160485
Short name T227
Test name
Test status
Simulation time 706658393 ps
CPU time 17.5 seconds
Started Aug 23 04:18:35 PM UTC 24
Finished Aug 23 04:18:54 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771160485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2771160485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_burst_wr.1560357958
Short name T163
Test name
Test status
Simulation time 289965987 ps
CPU time 13.05 seconds
Started Aug 23 04:18:49 PM UTC 24
Finished Aug 23 04:19:03 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560357958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1560357958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_datapath_stress.2894499350
Short name T231
Test name
Test status
Simulation time 948875595 ps
CPU time 48.46 seconds
Started Aug 23 04:18:43 PM UTC 24
Finished Aug 23 04:19:33 PM UTC 24
Peak memory 399116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894499350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2894499350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_error.71765974
Short name T232
Test name
Test status
Simulation time 18569563454 ps
CPU time 66.14 seconds
Started Aug 23 04:18:50 PM UTC 24
Finished Aug 23 04:19:58 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71765974 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.71765974
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_long_msg.1472861562
Short name T226
Test name
Test status
Simulation time 2900412867 ps
CPU time 18.17 seconds
Started Aug 23 04:18:23 PM UTC 24
Finished Aug 23 04:18:42 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472861562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1472861562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_smoke.2595837865
Short name T225
Test name
Test status
Simulation time 286027494 ps
CPU time 10.95 seconds
Started Aug 23 04:18:22 PM UTC 24
Finished Aug 23 04:18:34 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595837865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2595837865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_stress_all.2422740854
Short name T513
Test name
Test status
Simulation time 29828905777 ps
CPU time 2446.86 seconds
Started Aug 23 04:19:04 PM UTC 24
Finished Aug 23 05:00:12 PM UTC 24
Peak memory 790772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422740854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2422740854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/15.hmac_wipe_secret.2477444086
Short name T228
Test name
Test status
Simulation time 486410178 ps
CPU time 8.46 seconds
Started Aug 23 04:18:55 PM UTC 24
Finished Aug 23 04:19:04 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477444086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2477444086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/15.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_alert_test.2141482608
Short name T237
Test name
Test status
Simulation time 12580422 ps
CPU time 0.52 seconds
Started Aug 23 04:22:00 PM UTC 24
Finished Aug 23 04:22:02 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141482608 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2141482608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_back_pressure.625906393
Short name T234
Test name
Test status
Simulation time 1343226718 ps
CPU time 65.61 seconds
Started Aug 23 04:19:34 PM UTC 24
Finished Aug 23 04:20:42 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625906393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.625906393
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_burst_wr.2919664397
Short name T233
Test name
Test status
Simulation time 2576588133 ps
CPU time 31.58 seconds
Started Aug 23 04:20:00 PM UTC 24
Finished Aug 23 04:20:33 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919664397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2919664397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_datapath_stress.3615923143
Short name T281
Test name
Test status
Simulation time 47366910499 ps
CPU time 770.26 seconds
Started Aug 23 04:19:52 PM UTC 24
Finished Aug 23 04:32:50 PM UTC 24
Peak memory 772296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615923143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3615923143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_error.3873049382
Short name T240
Test name
Test status
Simulation time 12287000902 ps
CPU time 133.21 seconds
Started Aug 23 04:20:34 PM UTC 24
Finished Aug 23 04:22:49 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873049382 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3873049382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_long_msg.2318758285
Short name T235
Test name
Test status
Simulation time 6445872973 ps
CPU time 79.09 seconds
Started Aug 23 04:19:23 PM UTC 24
Finished Aug 23 04:20:44 PM UTC 24
Peak memory 207580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318758285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2318758285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_smoke.1076331709
Short name T230
Test name
Test status
Simulation time 2488989134 ps
CPU time 13.89 seconds
Started Aug 23 04:19:07 PM UTC 24
Finished Aug 23 04:19:22 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076331709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1076331709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_stress_all.1015345455
Short name T132
Test name
Test status
Simulation time 92974542413 ps
CPU time 528.65 seconds
Started Aug 23 04:20:45 PM UTC 24
Finished Aug 23 04:29:39 PM UTC 24
Peak memory 678160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015345455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1015345455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/16.hmac_wipe_secret.1959708418
Short name T238
Test name
Test status
Simulation time 1874436853 ps
CPU time 82.21 seconds
Started Aug 23 04:20:42 PM UTC 24
Finished Aug 23 04:22:06 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959708418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.1959708418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/16.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_alert_test.1831168679
Short name T246
Test name
Test status
Simulation time 34114397 ps
CPU time 0.5 seconds
Started Aug 23 04:25:37 PM UTC 24
Finished Aug 23 04:25:39 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831168679 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1831168679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_back_pressure.804020209
Short name T241
Test name
Test status
Simulation time 1319278305 ps
CPU time 33.89 seconds
Started Aug 23 04:22:18 PM UTC 24
Finished Aug 23 04:22:53 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804020209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.804020209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_burst_wr.3021297584
Short name T242
Test name
Test status
Simulation time 8080820879 ps
CPU time 23.77 seconds
Started Aug 23 04:22:54 PM UTC 24
Finished Aug 23 04:23:19 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021297584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3021297584
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_datapath_stress.4172594167
Short name T264
Test name
Test status
Simulation time 10589055810 ps
CPU time 428.13 seconds
Started Aug 23 04:22:50 PM UTC 24
Finished Aug 23 04:30:03 PM UTC 24
Peak memory 686292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172594167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4172594167
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_error.2649227797
Short name T245
Test name
Test status
Simulation time 17592520359 ps
CPU time 133.82 seconds
Started Aug 23 04:23:20 PM UTC 24
Finished Aug 23 04:25:36 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649227797 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.2649227797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_long_msg.3029580627
Short name T243
Test name
Test status
Simulation time 16144885872 ps
CPU time 89.52 seconds
Started Aug 23 04:22:08 PM UTC 24
Finished Aug 23 04:23:39 PM UTC 24
Peak memory 223672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029580627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3029580627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_smoke.2875757854
Short name T239
Test name
Test status
Simulation time 680637447 ps
CPU time 13.95 seconds
Started Aug 23 04:22:02 PM UTC 24
Finished Aug 23 04:22:17 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875757854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2875757854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_stress_all.3128256010
Short name T317
Test name
Test status
Simulation time 6742232082 ps
CPU time 700.71 seconds
Started Aug 23 04:24:10 PM UTC 24
Finished Aug 23 04:35:58 PM UTC 24
Peak memory 719212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128256010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3128256010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/17.hmac_wipe_secret.929154649
Short name T244
Test name
Test status
Simulation time 3414469106 ps
CPU time 27.81 seconds
Started Aug 23 04:23:40 PM UTC 24
Finished Aug 23 04:24:09 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929154649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.929154649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/17.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_alert_test.2504298755
Short name T254
Test name
Test status
Simulation time 11464278 ps
CPU time 0.5 seconds
Started Aug 23 04:28:28 PM UTC 24
Finished Aug 23 04:28:30 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504298755 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2504298755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_back_pressure.470101141
Short name T249
Test name
Test status
Simulation time 6125467451 ps
CPU time 32.29 seconds
Started Aug 23 04:26:14 PM UTC 24
Finished Aug 23 04:26:48 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470101141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.470101141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_burst_wr.2108827130
Short name T253
Test name
Test status
Simulation time 16526984854 ps
CPU time 54.16 seconds
Started Aug 23 04:27:11 PM UTC 24
Finished Aug 23 04:28:07 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108827130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2108827130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_datapath_stress.2777811885
Short name T266
Test name
Test status
Simulation time 3574424893 ps
CPU time 213.13 seconds
Started Aug 23 04:26:49 PM UTC 24
Finished Aug 23 04:30:24 PM UTC 24
Peak memory 452828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777811885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2777811885
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_error.675223714
Short name T256
Test name
Test status
Simulation time 1429228596 ps
CPU time 71.61 seconds
Started Aug 23 04:27:30 PM UTC 24
Finished Aug 23 04:28:44 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675223714 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.675223714
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_long_msg.4233824313
Short name T250
Test name
Test status
Simulation time 4779721186 ps
CPU time 72.68 seconds
Started Aug 23 04:25:55 PM UTC 24
Finished Aug 23 04:27:09 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233824313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.4233824313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_smoke.3944514026
Short name T247
Test name
Test status
Simulation time 5330761433 ps
CPU time 13.71 seconds
Started Aug 23 04:25:39 PM UTC 24
Finished Aug 23 04:25:54 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944514026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3944514026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_stress_all.2606721732
Short name T133
Test name
Test status
Simulation time 12267145956 ps
CPU time 152.64 seconds
Started Aug 23 04:28:07 PM UTC 24
Finished Aug 23 04:30:42 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606721732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2606721732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/18.hmac_wipe_secret.1676071399
Short name T259
Test name
Test status
Simulation time 4761949621 ps
CPU time 96.45 seconds
Started Aug 23 04:27:41 PM UTC 24
Finished Aug 23 04:29:19 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676071399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1676071399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/18.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_alert_test.1673658327
Short name T262
Test name
Test status
Simulation time 14159818 ps
CPU time 0.5 seconds
Started Aug 23 04:29:42 PM UTC 24
Finished Aug 23 04:29:43 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673658327 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1673658327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_back_pressure.766998593
Short name T258
Test name
Test status
Simulation time 2594543927 ps
CPU time 31.8 seconds
Started Aug 23 04:28:45 PM UTC 24
Finished Aug 23 04:29:18 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766998593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.766998593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_burst_wr.97689241
Short name T260
Test name
Test status
Simulation time 1283269303 ps
CPU time 4.67 seconds
Started Aug 23 04:29:19 PM UTC 24
Finished Aug 23 04:29:24 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97689241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.97689241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_datapath_stress.3344297810
Short name T272
Test name
Test status
Simulation time 1064888745 ps
CPU time 147.03 seconds
Started Aug 23 04:28:59 PM UTC 24
Finished Aug 23 04:31:29 PM UTC 24
Peak memory 657568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344297810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3344297810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_error.11511126
Short name T267
Test name
Test status
Simulation time 8565946230 ps
CPU time 102.94 seconds
Started Aug 23 04:29:20 PM UTC 24
Finished Aug 23 04:31:05 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11511126 -assert nopostproc +UVM_TESTNAME=hmac
_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.11511126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_long_msg.3210729778
Short name T261
Test name
Test status
Simulation time 1680184884 ps
CPU time 61.21 seconds
Started Aug 23 04:28:38 PM UTC 24
Finished Aug 23 04:29:40 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210729778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3210729778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_smoke.2202553478
Short name T255
Test name
Test status
Simulation time 469823279 ps
CPU time 4.71 seconds
Started Aug 23 04:28:30 PM UTC 24
Finished Aug 23 04:28:36 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202553478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2202553478
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_stress_all.832378774
Short name T404
Test name
Test status
Simulation time 11673667401 ps
CPU time 1032.63 seconds
Started Aug 23 04:29:42 PM UTC 24
Finished Aug 23 04:47:04 PM UTC 24
Peak memory 731564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832378774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.832378774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/19.hmac_wipe_secret.1885535288
Short name T265
Test name
Test status
Simulation time 3549168191 ps
CPU time 39.38 seconds
Started Aug 23 04:29:25 PM UTC 24
Finished Aug 23 04:30:06 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885535288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.1885535288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/19.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_alert_test.3841898718
Short name T61
Test name
Test status
Simulation time 46518922 ps
CPU time 0.49 seconds
Started Aug 23 03:57:52 PM UTC 24
Finished Aug 23 03:57:54 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841898718 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3841898718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_back_pressure.4171788718
Short name T23
Test name
Test status
Simulation time 870798992 ps
CPU time 44.43 seconds
Started Aug 23 03:56:03 PM UTC 24
Finished Aug 23 03:56:49 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171788718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4171788718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_datapath_stress.3167002805
Short name T178
Test name
Test status
Simulation time 5211614362 ps
CPU time 168.19 seconds
Started Aug 23 03:56:07 PM UTC 24
Finished Aug 23 03:58:58 PM UTC 24
Peak memory 612712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167002805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3167002805
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_error.3269343574
Short name T59
Test name
Test status
Simulation time 6738794409 ps
CPU time 81.32 seconds
Started Aug 23 03:56:28 PM UTC 24
Finished Aug 23 03:57:51 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269343574 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3269343574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_long_msg.3780018580
Short name T75
Test name
Test status
Simulation time 7848388849 ps
CPU time 106.51 seconds
Started Aug 23 03:56:03 PM UTC 24
Finished Aug 23 03:57:52 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780018580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3780018580
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_sec_cm.1729902278
Short name T65
Test name
Test status
Simulation time 105058404 ps
CPU time 0.79 seconds
Started Aug 23 03:57:49 PM UTC 24
Finished Aug 23 03:57:51 PM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729902278 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1729902278
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_smoke.4252573346
Short name T131
Test name
Test status
Simulation time 296872851 ps
CPU time 3.27 seconds
Started Aug 23 03:55:58 PM UTC 24
Finished Aug 23 03:56:02 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252573346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4252573346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_stress_all.1022822070
Short name T289
Test name
Test status
Simulation time 59881622095 ps
CPU time 2153.11 seconds
Started Aug 23 03:57:18 PM UTC 24
Finished Aug 23 04:33:30 PM UTC 24
Peak memory 843972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022822070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1022822070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_hmac256_vectors.3614444807
Short name T76
Test name
Test status
Simulation time 4279543105 ps
CPU time 62.21 seconds
Started Aug 23 03:56:50 PM UTC 24
Finished Aug 23 03:57:54 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614444807 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3614444807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_hmac384_vectors.2852949835
Short name T177
Test name
Test status
Simulation time 19391415749 ps
CPU time 95.06 seconds
Started Aug 23 03:56:54 PM UTC 24
Finished Aug 23 03:58:31 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852949835 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.2852949835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_hmac512_vectors.42428160
Short name T78
Test name
Test status
Simulation time 8587045218 ps
CPU time 59.61 seconds
Started Aug 23 03:57:08 PM UTC 24
Finished Aug 23 03:58:09 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42428160 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.42428160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_sha256_vectors.1680038053
Short name T150
Test name
Test status
Simulation time 106750585879 ps
CPU time 562.56 seconds
Started Aug 23 03:56:32 PM UTC 24
Finished Aug 23 04:06:01 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680038053 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1680038053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_sha384_vectors.164165067
Short name T285
Test name
Test status
Simulation time 234026980247 ps
CPU time 2166.28 seconds
Started Aug 23 03:56:39 PM UTC 24
Finished Aug 23 04:33:06 PM UTC 24
Peak memory 225540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164165067 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.164165067
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_test_sha512_vectors.1852240787
Short name T300
Test name
Test status
Simulation time 1999738352922 ps
CPU time 2239.21 seconds
Started Aug 23 03:56:47 PM UTC 24
Finished Aug 23 04:34:28 PM UTC 24
Peak memory 221176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852240787 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1852240787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/2.hmac_wipe_secret.2427083984
Short name T124
Test name
Test status
Simulation time 14860050214 ps
CPU time 111.16 seconds
Started Aug 23 03:56:28 PM UTC 24
Finished Aug 23 03:58:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427083984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2427083984
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/2.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_alert_test.1463515063
Short name T270
Test name
Test status
Simulation time 25767500 ps
CPU time 0.51 seconds
Started Aug 23 04:31:09 PM UTC 24
Finished Aug 23 04:31:11 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463515063 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1463515063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_back_pressure.3469469994
Short name T269
Test name
Test status
Simulation time 1200166564 ps
CPU time 63.06 seconds
Started Aug 23 04:30:04 PM UTC 24
Finished Aug 23 04:31:08 PM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469469994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3469469994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_burst_wr.3236933051
Short name T54
Test name
Test status
Simulation time 2853142861 ps
CPU time 44.98 seconds
Started Aug 23 04:30:25 PM UTC 24
Finished Aug 23 04:31:12 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236933051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3236933051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_datapath_stress.2674360633
Short name T275
Test name
Test status
Simulation time 3371455154 ps
CPU time 132.64 seconds
Started Aug 23 04:30:07 PM UTC 24
Finished Aug 23 04:32:22 PM UTC 24
Peak memory 631000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674360633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2674360633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_error.3431856536
Short name T41
Test name
Test status
Simulation time 3746200187 ps
CPU time 149.35 seconds
Started Aug 23 04:30:43 PM UTC 24
Finished Aug 23 04:33:15 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431856536 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3431856536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_long_msg.1662565474
Short name T268
Test name
Test status
Simulation time 6588720553 ps
CPU time 70.39 seconds
Started Aug 23 04:29:53 PM UTC 24
Finished Aug 23 04:31:05 PM UTC 24
Peak memory 217804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662565474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1662565474
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_smoke.3933843889
Short name T263
Test name
Test status
Simulation time 2061951897 ps
CPU time 7.19 seconds
Started Aug 23 04:29:44 PM UTC 24
Finished Aug 23 04:29:52 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933843889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3933843889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_stress_all.661942806
Short name T82
Test name
Test status
Simulation time 272353278842 ps
CPU time 2062.06 seconds
Started Aug 23 04:31:06 PM UTC 24
Finished Aug 23 05:05:47 PM UTC 24
Peak memory 805104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661942806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.661942806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/20.hmac_wipe_secret.3794610826
Short name T273
Test name
Test status
Simulation time 3199950248 ps
CPU time 37.94 seconds
Started Aug 23 04:31:06 PM UTC 24
Finished Aug 23 04:31:45 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794610826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3794610826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/20.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_alert_test.2699411773
Short name T279
Test name
Test status
Simulation time 12780775 ps
CPU time 0.49 seconds
Started Aug 23 04:32:36 PM UTC 24
Finished Aug 23 04:32:38 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699411773 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2699411773
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_back_pressure.3711678275
Short name T280
Test name
Test status
Simulation time 19139085563 ps
CPU time 76.79 seconds
Started Aug 23 04:31:24 PM UTC 24
Finished Aug 23 04:32:43 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711678275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3711678275
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_burst_wr.2344563230
Short name T278
Test name
Test status
Simulation time 2898553383 ps
CPU time 43.94 seconds
Started Aug 23 04:31:46 PM UTC 24
Finished Aug 23 04:32:31 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344563230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2344563230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_datapath_stress.4111260140
Short name T324
Test name
Test status
Simulation time 8371221841 ps
CPU time 335.43 seconds
Started Aug 23 04:31:30 PM UTC 24
Finished Aug 23 04:37:09 PM UTC 24
Peak memory 676128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111260140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4111260140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_error.1899715921
Short name T282
Test name
Test status
Simulation time 579869246 ps
CPU time 26.73 seconds
Started Aug 23 04:32:24 PM UTC 24
Finished Aug 23 04:32:53 PM UTC 24
Peak memory 206828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899715921 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1899715921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_long_msg.12527196
Short name T284
Test name
Test status
Simulation time 37093220990 ps
CPU time 109.92 seconds
Started Aug 23 04:31:13 PM UTC 24
Finished Aug 23 04:33:05 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12527196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.12527196
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_smoke.1195068847
Short name T271
Test name
Test status
Simulation time 945445160 ps
CPU time 11.17 seconds
Started Aug 23 04:31:11 PM UTC 24
Finished Aug 23 04:31:24 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195068847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1195068847
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_stress_all.988236957
Short name T469
Test name
Test status
Simulation time 53857164629 ps
CPU time 1289.71 seconds
Started Aug 23 04:32:36 PM UTC 24
Finished Aug 23 04:54:18 PM UTC 24
Peak memory 780648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988236957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.988236957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/21.hmac_wipe_secret.3079885602
Short name T45
Test name
Test status
Simulation time 3208164097 ps
CPU time 51.27 seconds
Started Aug 23 04:32:24 PM UTC 24
Finished Aug 23 04:33:18 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079885602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3079885602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/21.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_alert_test.738469225
Short name T44
Test name
Test status
Simulation time 31345827 ps
CPU time 0.58 seconds
Started Aug 23 04:33:14 PM UTC 24
Finished Aug 23 04:33:16 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738469225 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.738469225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_burst_wr.2672689544
Short name T287
Test name
Test status
Simulation time 3988463330 ps
CPU time 16.33 seconds
Started Aug 23 04:32:54 PM UTC 24
Finished Aug 23 04:33:12 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672689544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2672689544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_datapath_stress.1359892890
Short name T42
Test name
Test status
Simulation time 235856507 ps
CPU time 21.87 seconds
Started Aug 23 04:32:52 PM UTC 24
Finished Aug 23 04:33:15 PM UTC 24
Peak memory 260380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359892890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1359892890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_error.2668644819
Short name T325
Test name
Test status
Simulation time 39336213378 ps
CPU time 248.39 seconds
Started Aug 23 04:32:57 PM UTC 24
Finished Aug 23 04:37:09 PM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668644819 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2668644819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_long_msg.1381529786
Short name T292
Test name
Test status
Simulation time 5305888864 ps
CPU time 60.69 seconds
Started Aug 23 04:32:42 PM UTC 24
Finished Aug 23 04:33:45 PM UTC 24
Peak memory 223476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381529786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1381529786
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_smoke.1489992685
Short name T283
Test name
Test status
Simulation time 2409176935 ps
CPU time 12.47 seconds
Started Aug 23 04:32:42 PM UTC 24
Finished Aug 23 04:32:56 PM UTC 24
Peak memory 207012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489992685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1489992685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_stress_all.2809911487
Short name T318
Test name
Test status
Simulation time 16564857066 ps
CPU time 170.78 seconds
Started Aug 23 04:33:14 PM UTC 24
Finished Aug 23 04:36:08 PM UTC 24
Peak memory 207156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809911487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2809911487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/22.hmac_wipe_secret.2920468150
Short name T294
Test name
Test status
Simulation time 13787993523 ps
CPU time 38.45 seconds
Started Aug 23 04:33:14 PM UTC 24
Finished Aug 23 04:33:54 PM UTC 24
Peak memory 207132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920468150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2920468150
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/22.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_alert_test.626885910
Short name T48
Test name
Test status
Simulation time 40926954 ps
CPU time 0.5 seconds
Started Aug 23 04:33:24 PM UTC 24
Finished Aug 23 04:33:25 PM UTC 24
Peak memory 203732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626885910 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.626885910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_back_pressure.2715354345
Short name T296
Test name
Test status
Simulation time 3982478321 ps
CPU time 57.32 seconds
Started Aug 23 04:33:16 PM UTC 24
Finished Aug 23 04:34:15 PM UTC 24
Peak memory 215720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715354345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2715354345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_burst_wr.1689580048
Short name T47
Test name
Test status
Simulation time 203046253 ps
CPU time 2.57 seconds
Started Aug 23 04:33:20 PM UTC 24
Finished Aug 23 04:33:23 PM UTC 24
Peak memory 207064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689580048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1689580048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_datapath_stress.2441277764
Short name T326
Test name
Test status
Simulation time 7423820337 ps
CPU time 233.47 seconds
Started Aug 23 04:33:16 PM UTC 24
Finished Aug 23 04:37:12 PM UTC 24
Peak memory 717224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441277764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.2441277764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_error.2096594384
Short name T307
Test name
Test status
Simulation time 4490592644 ps
CPU time 103.6 seconds
Started Aug 23 04:33:20 PM UTC 24
Finished Aug 23 04:35:05 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096594384 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2096594384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_long_msg.2802348282
Short name T290
Test name
Test status
Simulation time 406749833 ps
CPU time 18.42 seconds
Started Aug 23 04:33:14 PM UTC 24
Finished Aug 23 04:33:34 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802348282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2802348282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_smoke.579557524
Short name T46
Test name
Test status
Simulation time 1562227768 ps
CPU time 4.65 seconds
Started Aug 23 04:33:14 PM UTC 24
Finished Aug 23 04:33:20 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579557524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.579557524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_stress_all.2473261144
Short name T481
Test name
Test status
Simulation time 18471000456 ps
CPU time 1345.33 seconds
Started Aug 23 04:33:21 PM UTC 24
Finished Aug 23 04:55:59 PM UTC 24
Peak memory 780516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473261144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2473261144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/23.hmac_wipe_secret.3848355992
Short name T288
Test name
Test status
Simulation time 396228242 ps
CPU time 6.39 seconds
Started Aug 23 04:33:20 PM UTC 24
Finished Aug 23 04:33:27 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848355992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3848355992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/23.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_alert_test.529973986
Short name T295
Test name
Test status
Simulation time 11005434 ps
CPU time 0.49 seconds
Started Aug 23 04:34:05 PM UTC 24
Finished Aug 23 04:34:07 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=529973986 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.529973986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_back_pressure.1130618259
Short name T302
Test name
Test status
Simulation time 1488808588 ps
CPU time 74.84 seconds
Started Aug 23 04:33:34 PM UTC 24
Finished Aug 23 04:34:51 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130618259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1130618259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_burst_wr.3674019097
Short name T161
Test name
Test status
Simulation time 4395727767 ps
CPU time 21.88 seconds
Started Aug 23 04:33:41 PM UTC 24
Finished Aug 23 04:34:04 PM UTC 24
Peak memory 215956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674019097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3674019097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_datapath_stress.427777989
Short name T380
Test name
Test status
Simulation time 14731762941 ps
CPU time 609.13 seconds
Started Aug 23 04:33:35 PM UTC 24
Finished Aug 23 04:43:50 PM UTC 24
Peak memory 754028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427777989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.427777989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_error.3353517358
Short name T298
Test name
Test status
Simulation time 25992310464 ps
CPU time 37.68 seconds
Started Aug 23 04:33:46 PM UTC 24
Finished Aug 23 04:34:25 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353517358 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3353517358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_long_msg.3802368925
Short name T293
Test name
Test status
Simulation time 1721771493 ps
CPU time 17.8 seconds
Started Aug 23 04:33:28 PM UTC 24
Finished Aug 23 04:33:47 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802368925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.3802368925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_smoke.960775092
Short name T291
Test name
Test status
Simulation time 1351931353 ps
CPU time 13.45 seconds
Started Aug 23 04:33:26 PM UTC 24
Finished Aug 23 04:33:40 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960775092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.960775092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_stress_all.2077482685
Short name T521
Test name
Test status
Simulation time 146731006851 ps
CPU time 1736.64 seconds
Started Aug 23 04:33:55 PM UTC 24
Finished Aug 23 05:03:08 PM UTC 24
Peak memory 731440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077482685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2077482685
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/24.hmac_wipe_secret.1509739570
Short name T299
Test name
Test status
Simulation time 1437658674 ps
CPU time 36.63 seconds
Started Aug 23 04:33:48 PM UTC 24
Finished Aug 23 04:34:26 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509739570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1509739570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/24.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_alert_test.3584422574
Short name T305
Test name
Test status
Simulation time 25044650 ps
CPU time 0.51 seconds
Started Aug 23 04:34:53 PM UTC 24
Finished Aug 23 04:34:54 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584422574 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3584422574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_back_pressure.1844435938
Short name T304
Test name
Test status
Simulation time 2646445430 ps
CPU time 34.71 seconds
Started Aug 23 04:34:17 PM UTC 24
Finished Aug 23 04:34:53 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844435938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1844435938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_burst_wr.868995386
Short name T303
Test name
Test status
Simulation time 1435996746 ps
CPU time 22.32 seconds
Started Aug 23 04:34:27 PM UTC 24
Finished Aug 23 04:34:51 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868995386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.868995386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_datapath_stress.2089626592
Short name T323
Test name
Test status
Simulation time 5273640361 ps
CPU time 158.54 seconds
Started Aug 23 04:34:26 PM UTC 24
Finished Aug 23 04:37:07 PM UTC 24
Peak memory 469272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089626592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2089626592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_error.2320297634
Short name T311
Test name
Test status
Simulation time 2061696783 ps
CPU time 52.27 seconds
Started Aug 23 04:34:39 PM UTC 24
Finished Aug 23 04:35:33 PM UTC 24
Peak memory 206916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320297634 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2320297634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_long_msg.3024379368
Short name T310
Test name
Test status
Simulation time 4331981255 ps
CPU time 67.46 seconds
Started Aug 23 04:34:16 PM UTC 24
Finished Aug 23 04:35:25 PM UTC 24
Peak memory 207576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024379368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3024379368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_smoke.441471926
Short name T297
Test name
Test status
Simulation time 469425869 ps
CPU time 7.95 seconds
Started Aug 23 04:34:07 PM UTC 24
Finished Aug 23 04:34:16 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441471926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.441471926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_stress_all.829400437
Short name T83
Test name
Test status
Simulation time 531840287306 ps
CPU time 1857.09 seconds
Started Aug 23 04:34:53 PM UTC 24
Finished Aug 23 05:06:07 PM UTC 24
Peak memory 751916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829400437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.829400437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/25.hmac_wipe_secret.2281949838
Short name T309
Test name
Test status
Simulation time 13598415063 ps
CPU time 37.48 seconds
Started Aug 23 04:34:39 PM UTC 24
Finished Aug 23 04:35:18 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281949838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2281949838
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/25.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_alert_test.2364896007
Short name T313
Test name
Test status
Simulation time 44407596 ps
CPU time 0.51 seconds
Started Aug 23 04:35:39 PM UTC 24
Finished Aug 23 04:35:40 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364896007 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2364896007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_back_pressure.1121419449
Short name T315
Test name
Test status
Simulation time 2605080157 ps
CPU time 44.67 seconds
Started Aug 23 04:35:03 PM UTC 24
Finished Aug 23 04:35:49 PM UTC 24
Peak memory 215748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121419449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1121419449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_burst_wr.112066576
Short name T312
Test name
Test status
Simulation time 2104847479 ps
CPU time 12.51 seconds
Started Aug 23 04:35:24 PM UTC 24
Finished Aug 23 04:35:38 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112066576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.112066576
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_datapath_stress.2454476902
Short name T370
Test name
Test status
Simulation time 12606017981 ps
CPU time 458.1 seconds
Started Aug 23 04:35:06 PM UTC 24
Finished Aug 23 04:42:49 PM UTC 24
Peak memory 766180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454476902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2454476902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_error.4032205401
Short name T329
Test name
Test status
Simulation time 2539717407 ps
CPU time 130.42 seconds
Started Aug 23 04:35:24 PM UTC 24
Finished Aug 23 04:37:37 PM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032205401 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4032205401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_long_msg.4000038500
Short name T314
Test name
Test status
Simulation time 3062307351 ps
CPU time 45.48 seconds
Started Aug 23 04:34:55 PM UTC 24
Finished Aug 23 04:35:42 PM UTC 24
Peak memory 207512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000038500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4000038500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_smoke.4193698728
Short name T306
Test name
Test status
Simulation time 630909747 ps
CPU time 6.84 seconds
Started Aug 23 04:34:54 PM UTC 24
Finished Aug 23 04:35:02 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193698728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.4193698728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_stress_all.3377457296
Short name T504
Test name
Test status
Simulation time 12995193102 ps
CPU time 1366.18 seconds
Started Aug 23 04:35:34 PM UTC 24
Finished Aug 23 04:58:32 PM UTC 24
Peak memory 803104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377457296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3377457296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/26.hmac_wipe_secret.1285041780
Short name T327
Test name
Test status
Simulation time 76272959322 ps
CPU time 112 seconds
Started Aug 23 04:35:25 PM UTC 24
Finished Aug 23 04:37:20 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285041780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1285041780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/26.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_alert_test.2441936990
Short name T322
Test name
Test status
Simulation time 12529989 ps
CPU time 0.5 seconds
Started Aug 23 04:37:04 PM UTC 24
Finished Aug 23 04:37:06 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441936990 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2441936990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_back_pressure.4245650784
Short name T321
Test name
Test status
Simulation time 1506228358 ps
CPU time 71.36 seconds
Started Aug 23 04:35:50 PM UTC 24
Finished Aug 23 04:37:03 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245650784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4245650784
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_burst_wr.4201626152
Short name T319
Test name
Test status
Simulation time 2055767968 ps
CPU time 22.38 seconds
Started Aug 23 04:36:00 PM UTC 24
Finished Aug 23 04:36:23 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201626152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.4201626152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_datapath_stress.2866105619
Short name T347
Test name
Test status
Simulation time 1975837406 ps
CPU time 230.24 seconds
Started Aug 23 04:35:55 PM UTC 24
Finished Aug 23 04:39:48 PM UTC 24
Peak memory 649372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866105619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2866105619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_error.1738369007
Short name T337
Test name
Test status
Simulation time 16182430718 ps
CPU time 121.07 seconds
Started Aug 23 04:36:09 PM UTC 24
Finished Aug 23 04:38:13 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738369007 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1738369007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_long_msg.3486147889
Short name T320
Test name
Test status
Simulation time 1202284390 ps
CPU time 45.08 seconds
Started Aug 23 04:35:43 PM UTC 24
Finished Aug 23 04:36:30 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486147889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3486147889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_smoke.4163941934
Short name T316
Test name
Test status
Simulation time 313989965 ps
CPU time 11.65 seconds
Started Aug 23 04:35:41 PM UTC 24
Finished Aug 23 04:35:54 PM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163941934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4163941934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_stress_all.234039128
Short name T491
Test name
Test status
Simulation time 27623113496 ps
CPU time 1214.84 seconds
Started Aug 23 04:36:31 PM UTC 24
Finished Aug 23 04:56:57 PM UTC 24
Peak memory 751896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234039128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.234039128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/27.hmac_wipe_secret.3616712931
Short name T98
Test name
Test status
Simulation time 10442449986 ps
CPU time 85.93 seconds
Started Aug 23 04:36:25 PM UTC 24
Finished Aug 23 04:37:52 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616712931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3616712931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/27.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_alert_test.1316635982
Short name T328
Test name
Test status
Simulation time 25345300 ps
CPU time 0.5 seconds
Started Aug 23 04:37:33 PM UTC 24
Finished Aug 23 04:37:34 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316635982 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1316635982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_back_pressure.2167109542
Short name T29
Test name
Test status
Simulation time 3009499941 ps
CPU time 77.1 seconds
Started Aug 23 04:37:08 PM UTC 24
Finished Aug 23 04:38:27 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167109542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2167109542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_burst_wr.951194357
Short name T330
Test name
Test status
Simulation time 17195053094 ps
CPU time 28.07 seconds
Started Aug 23 04:37:11 PM UTC 24
Finished Aug 23 04:37:41 PM UTC 24
Peak memory 215964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951194357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.951194357
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_datapath_stress.3295963162
Short name T416
Test name
Test status
Simulation time 10127816957 ps
CPU time 683.7 seconds
Started Aug 23 04:37:11 PM UTC 24
Finished Aug 23 04:48:42 PM UTC 24
Peak memory 743716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295963162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3295963162
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_error.3086205769
Short name T364
Test name
Test status
Simulation time 124148095370 ps
CPU time 254.37 seconds
Started Aug 23 04:37:14 PM UTC 24
Finished Aug 23 04:41:32 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086205769 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3086205769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_long_msg.768437501
Short name T336
Test name
Test status
Simulation time 4199257469 ps
CPU time 59.6 seconds
Started Aug 23 04:37:08 PM UTC 24
Finished Aug 23 04:38:09 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768437501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.768437501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_smoke.1396867063
Short name T49
Test name
Test status
Simulation time 3966477818 ps
CPU time 13.82 seconds
Started Aug 23 04:37:06 PM UTC 24
Finished Aug 23 04:37:22 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396867063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1396867063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_stress_all.3746571910
Short name T524
Test name
Test status
Simulation time 209041652995 ps
CPU time 1612.68 seconds
Started Aug 23 04:37:22 PM UTC 24
Finished Aug 23 05:04:30 PM UTC 24
Peak memory 739660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746571910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3746571910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/28.hmac_wipe_secret.3875041477
Short name T341
Test name
Test status
Simulation time 9601569183 ps
CPU time 90.37 seconds
Started Aug 23 04:37:21 PM UTC 24
Finished Aug 23 04:38:53 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875041477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3875041477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/28.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_alert_test.2509092326
Short name T335
Test name
Test status
Simulation time 63130346 ps
CPU time 0.49 seconds
Started Aug 23 04:38:02 PM UTC 24
Finished Aug 23 04:38:03 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509092326 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2509092326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_back_pressure.4032855670
Short name T332
Test name
Test status
Simulation time 645316020 ps
CPU time 8.34 seconds
Started Aug 23 04:37:41 PM UTC 24
Finished Aug 23 04:37:51 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032855670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4032855670
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_burst_wr.3078965072
Short name T333
Test name
Test status
Simulation time 248226887 ps
CPU time 1.22 seconds
Started Aug 23 04:37:51 PM UTC 24
Finished Aug 23 04:37:54 PM UTC 24
Peak memory 206228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078965072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3078965072
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_datapath_stress.770460879
Short name T429
Test name
Test status
Simulation time 6789831151 ps
CPU time 723.86 seconds
Started Aug 23 04:37:45 PM UTC 24
Finished Aug 23 04:49:56 PM UTC 24
Peak memory 754152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770460879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.770460879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_error.3923037737
Short name T346
Test name
Test status
Simulation time 23357499826 ps
CPU time 92.7 seconds
Started Aug 23 04:37:58 PM UTC 24
Finished Aug 23 04:39:32 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923037737 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3923037737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_long_msg.914607732
Short name T350
Test name
Test status
Simulation time 50063598338 ps
CPU time 146.46 seconds
Started Aug 23 04:37:38 PM UTC 24
Finished Aug 23 04:40:07 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914607732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.914607732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_smoke.1107636649
Short name T331
Test name
Test status
Simulation time 375026202 ps
CPU time 8.75 seconds
Started Aug 23 04:37:35 PM UTC 24
Finished Aug 23 04:37:45 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107636649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1107636649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_stress_all.673230190
Short name T334
Test name
Test status
Simulation time 731864142 ps
CPU time 2.35 seconds
Started Aug 23 04:37:58 PM UTC 24
Finished Aug 23 04:38:01 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673230190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.673230190
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/29.hmac_wipe_secret.1491977311
Short name T99
Test name
Test status
Simulation time 23929234188 ps
CPU time 67.66 seconds
Started Aug 23 04:37:58 PM UTC 24
Finished Aug 23 04:39:07 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491977311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1491977311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/29.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_alert_test.3805249988
Short name T179
Test name
Test status
Simulation time 12014698 ps
CPU time 0.5 seconds
Started Aug 23 03:59:17 PM UTC 24
Finished Aug 23 03:59:19 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805249988 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3805249988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_back_pressure.2439895005
Short name T50
Test name
Test status
Simulation time 6347041440 ps
CPU time 75.28 seconds
Started Aug 23 03:57:55 PM UTC 24
Finished Aug 23 03:59:12 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439895005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2439895005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_burst_wr.947149775
Short name T77
Test name
Test status
Simulation time 400693511 ps
CPU time 7.03 seconds
Started Aug 23 03:58:00 PM UTC 24
Finished Aug 23 03:58:08 PM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947149775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.947149775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_datapath_stress.4013602690
Short name T172
Test name
Test status
Simulation time 12671292743 ps
CPU time 405.81 seconds
Started Aug 23 03:57:55 PM UTC 24
Finished Aug 23 04:04:45 PM UTC 24
Peak memory 706772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013602690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4013602690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_error.2952878971
Short name T176
Test name
Test status
Simulation time 435209173 ps
CPU time 20.48 seconds
Started Aug 23 03:58:03 PM UTC 24
Finished Aug 23 03:58:25 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952878971 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2952878971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_long_msg.1831627983
Short name T79
Test name
Test status
Simulation time 4439136741 ps
CPU time 24.46 seconds
Started Aug 23 03:57:54 PM UTC 24
Finished Aug 23 03:58:20 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831627983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1831627983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_sec_cm.685031124
Short name T66
Test name
Test status
Simulation time 535374666 ps
CPU time 0.86 seconds
Started Aug 23 03:59:14 PM UTC 24
Finished Aug 23 03:59:16 PM UTC 24
Peak memory 235568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685031124 -assert nopostproc +UVM_TESTNAME=hmac_ba
se_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.685031124
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_smoke.549943770
Short name T63
Test name
Test status
Simulation time 2680490212 ps
CPU time 9.2 seconds
Started Aug 23 03:57:52 PM UTC 24
Finished Aug 23 03:58:03 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549943770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.549943770
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_stress_all.2053877538
Short name T165
Test name
Test status
Simulation time 103505054833 ps
CPU time 2311.63 seconds
Started Aug 23 03:58:59 PM UTC 24
Finished Aug 23 04:37:51 PM UTC 24
Peak memory 829636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053877538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2053877538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_hmac256_vectors.3781479318
Short name T180
Test name
Test status
Simulation time 7163377919 ps
CPU time 70.56 seconds
Started Aug 23 03:58:26 PM UTC 24
Finished Aug 23 03:59:38 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781479318 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3781479318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_hmac384_vectors.3974415532
Short name T182
Test name
Test status
Simulation time 32996645164 ps
CPU time 90.28 seconds
Started Aug 23 03:58:32 PM UTC 24
Finished Aug 23 04:00:04 PM UTC 24
Peak memory 207336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974415532 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3974415532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_hmac512_vectors.1176881497
Short name T181
Test name
Test status
Simulation time 2057544899 ps
CPU time 60.92 seconds
Started Aug 23 03:58:54 PM UTC 24
Finished Aug 23 03:59:57 PM UTC 24
Peak memory 207272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176881497 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1176881497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_sha256_vectors.4022622302
Short name T198
Test name
Test status
Simulation time 54560007368 ps
CPU time 589.8 seconds
Started Aug 23 03:58:11 PM UTC 24
Finished Aug 23 04:08:07 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022622302 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.4022622302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_sha256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_sha384_vectors.557268803
Short name T257
Test name
Test status
Simulation time 75709091699 ps
CPU time 1815.31 seconds
Started Aug 23 03:58:20 PM UTC 24
Finished Aug 23 04:28:53 PM UTC 24
Peak memory 221240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557268803 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.557268803
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_test_sha512_vectors.4241836660
Short name T301
Test name
Test status
Simulation time 147061326596 ps
CPU time 2145.38 seconds
Started Aug 23 03:58:22 PM UTC 24
Finished Aug 23 04:34:29 PM UTC 24
Peak memory 221232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241836660 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.4241836660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/3.hmac_wipe_secret.1281688416
Short name T125
Test name
Test status
Simulation time 2775428519 ps
CPU time 42.64 seconds
Started Aug 23 03:58:09 PM UTC 24
Finished Aug 23 03:58:54 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281688416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1281688416
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/3.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_alert_test.386617544
Short name T343
Test name
Test status
Simulation time 12028858 ps
CPU time 0.51 seconds
Started Aug 23 04:39:08 PM UTC 24
Finished Aug 23 04:39:10 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386617544 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.386617544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_back_pressure.3315786338
Short name T339
Test name
Test status
Simulation time 263208591 ps
CPU time 3.72 seconds
Started Aug 23 04:38:14 PM UTC 24
Finished Aug 23 04:38:18 PM UTC 24
Peak memory 207112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315786338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3315786338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_burst_wr.3087690323
Short name T342
Test name
Test status
Simulation time 42590617897 ps
CPU time 48.68 seconds
Started Aug 23 04:38:19 PM UTC 24
Finished Aug 23 04:39:09 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087690323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3087690323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_datapath_stress.290145780
Short name T411
Test name
Test status
Simulation time 60049178871 ps
CPU time 574.42 seconds
Started Aug 23 04:38:19 PM UTC 24
Finished Aug 23 04:47:59 PM UTC 24
Peak memory 723436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290145780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.290145780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_error.596762603
Short name T340
Test name
Test status
Simulation time 1930673974 ps
CPU time 22.41 seconds
Started Aug 23 04:38:28 PM UTC 24
Finished Aug 23 04:38:52 PM UTC 24
Peak memory 207120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596762603 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.596762603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_long_msg.1144770218
Short name T355
Test name
Test status
Simulation time 11593076700 ps
CPU time 137.38 seconds
Started Aug 23 04:38:10 PM UTC 24
Finished Aug 23 04:40:30 PM UTC 24
Peak memory 215760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144770218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1144770218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_smoke.2329657102
Short name T338
Test name
Test status
Simulation time 1321620803 ps
CPU time 12.58 seconds
Started Aug 23 04:38:04 PM UTC 24
Finished Aug 23 04:38:18 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329657102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2329657102
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_stress_all.510244345
Short name T101
Test name
Test status
Simulation time 45361538879 ps
CPU time 546.04 seconds
Started Aug 23 04:38:55 PM UTC 24
Finished Aug 23 04:48:07 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510244345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.510244345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/30.hmac_wipe_secret.923558359
Short name T100
Test name
Test status
Simulation time 3707658247 ps
CPU time 81.54 seconds
Started Aug 23 04:38:53 PM UTC 24
Finished Aug 23 04:40:16 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923558359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.923558359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/30.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_alert_test.4262891846
Short name T352
Test name
Test status
Simulation time 17697707 ps
CPU time 0.49 seconds
Started Aug 23 04:40:08 PM UTC 24
Finished Aug 23 04:40:10 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262891846 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.4262891846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_back_pressure.2335940060
Short name T349
Test name
Test status
Simulation time 2661411703 ps
CPU time 43.13 seconds
Started Aug 23 04:39:19 PM UTC 24
Finished Aug 23 04:40:04 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335940060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2335940060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_burst_wr.2830420911
Short name T348
Test name
Test status
Simulation time 2098769905 ps
CPU time 13.81 seconds
Started Aug 23 04:39:35 PM UTC 24
Finished Aug 23 04:39:50 PM UTC 24
Peak memory 215692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830420911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2830420911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_datapath_stress.3800665319
Short name T476
Test name
Test status
Simulation time 102136105180 ps
CPU time 942.09 seconds
Started Aug 23 04:39:35 PM UTC 24
Finished Aug 23 04:55:25 PM UTC 24
Peak memory 743844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800665319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3800665319
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_error.1663008026
Short name T360
Test name
Test status
Simulation time 3117376908 ps
CPU time 77.69 seconds
Started Aug 23 04:39:49 PM UTC 24
Finished Aug 23 04:41:09 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663008026 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.1663008026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_long_msg.2027531467
Short name T363
Test name
Test status
Simulation time 2835703047 ps
CPU time 137.66 seconds
Started Aug 23 04:39:10 PM UTC 24
Finished Aug 23 04:41:30 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027531467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2027531467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_smoke.117602338
Short name T344
Test name
Test status
Simulation time 454897570 ps
CPU time 8.63 seconds
Started Aug 23 04:39:09 PM UTC 24
Finished Aug 23 04:39:19 PM UTC 24
Peak memory 207372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117602338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.117602338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_stress_all.1178490558
Short name T449
Test name
Test status
Simulation time 195211408809 ps
CPU time 682.67 seconds
Started Aug 23 04:40:06 PM UTC 24
Finished Aug 23 04:51:36 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178490558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1178490558
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/31.hmac_wipe_secret.3091640504
Short name T351
Test name
Test status
Simulation time 1658851736 ps
CPU time 17.89 seconds
Started Aug 23 04:39:50 PM UTC 24
Finished Aug 23 04:40:09 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091640504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3091640504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/31.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_alert_test.4106626028
Short name T359
Test name
Test status
Simulation time 36620734 ps
CPU time 0.47 seconds
Started Aug 23 04:41:00 PM UTC 24
Finished Aug 23 04:41:01 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106626028 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.4106626028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_back_pressure.1497643885
Short name T358
Test name
Test status
Simulation time 951335047 ps
CPU time 42.24 seconds
Started Aug 23 04:40:15 PM UTC 24
Finished Aug 23 04:40:58 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497643885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1497643885
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_burst_wr.3331618376
Short name T361
Test name
Test status
Simulation time 52732040255 ps
CPU time 37.36 seconds
Started Aug 23 04:40:33 PM UTC 24
Finished Aug 23 04:41:12 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331618376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3331618376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_datapath_stress.1484898602
Short name T472
Test name
Test status
Simulation time 6141026174 ps
CPU time 847.31 seconds
Started Aug 23 04:40:17 PM UTC 24
Finished Aug 23 04:54:32 PM UTC 24
Peak memory 753892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484898602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1484898602
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_error.2045166800
Short name T356
Test name
Test status
Simulation time 39430959 ps
CPU time 0.55 seconds
Started Aug 23 04:40:33 PM UTC 24
Finished Aug 23 04:40:35 PM UTC 24
Peak memory 203664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045166800 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2045166800
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_long_msg.3537209257
Short name T371
Test name
Test status
Simulation time 13374930246 ps
CPU time 157.43 seconds
Started Aug 23 04:40:10 PM UTC 24
Finished Aug 23 04:42:50 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537209257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3537209257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_smoke.679393096
Short name T353
Test name
Test status
Simulation time 109404706 ps
CPU time 2.1 seconds
Started Aug 23 04:40:10 PM UTC 24
Finished Aug 23 04:40:14 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679393096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.679393096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_stress_all.851245509
Short name T365
Test name
Test status
Simulation time 7616516451 ps
CPU time 59.66 seconds
Started Aug 23 04:40:48 PM UTC 24
Finished Aug 23 04:41:50 PM UTC 24
Peak memory 215696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851245509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.851245509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/32.hmac_wipe_secret.1564338590
Short name T357
Test name
Test status
Simulation time 624938642 ps
CPU time 9.67 seconds
Started Aug 23 04:40:36 PM UTC 24
Finished Aug 23 04:40:47 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564338590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1564338590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/32.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_alert_test.1599788539
Short name T367
Test name
Test status
Simulation time 77733681 ps
CPU time 0.5 seconds
Started Aug 23 04:42:14 PM UTC 24
Finished Aug 23 04:42:16 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599788539 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1599788539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_back_pressure.1861963609
Short name T369
Test name
Test status
Simulation time 1483761237 ps
CPU time 76.83 seconds
Started Aug 23 04:41:13 PM UTC 24
Finished Aug 23 04:42:32 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861963609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1861963609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_datapath_stress.3196442231
Short name T421
Test name
Test status
Simulation time 15400337673 ps
CPU time 467.65 seconds
Started Aug 23 04:41:14 PM UTC 24
Finished Aug 23 04:49:07 PM UTC 24
Peak memory 528600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196442231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3196442231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_error.2022313501
Short name T376
Test name
Test status
Simulation time 9936283391 ps
CPU time 119.84 seconds
Started Aug 23 04:41:34 PM UTC 24
Finished Aug 23 04:43:36 PM UTC 24
Peak memory 207568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022313501 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2022313501
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_long_msg.4273128247
Short name T366
Test name
Test status
Simulation time 9374457754 ps
CPU time 51.45 seconds
Started Aug 23 04:41:10 PM UTC 24
Finished Aug 23 04:42:03 PM UTC 24
Peak memory 207524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273128247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.4273128247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_smoke.188106875
Short name T362
Test name
Test status
Simulation time 966798765 ps
CPU time 10.66 seconds
Started Aug 23 04:41:02 PM UTC 24
Finished Aug 23 04:41:14 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188106875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.188106875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_stress_all.252992269
Short name T398
Test name
Test status
Simulation time 18151195453 ps
CPU time 222.7 seconds
Started Aug 23 04:42:04 PM UTC 24
Finished Aug 23 04:45:50 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252992269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.252992269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/33.hmac_wipe_secret.1215594570
Short name T373
Test name
Test status
Simulation time 8418990592 ps
CPU time 81.98 seconds
Started Aug 23 04:41:51 PM UTC 24
Finished Aug 23 04:43:15 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215594570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1215594570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/33.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_alert_test.4252511226
Short name T375
Test name
Test status
Simulation time 48806349 ps
CPU time 0.49 seconds
Started Aug 23 04:43:24 PM UTC 24
Finished Aug 23 04:43:26 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252511226 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.4252511226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_back_pressure.3106163734
Short name T377
Test name
Test status
Simulation time 2372312580 ps
CPU time 62.7 seconds
Started Aug 23 04:42:33 PM UTC 24
Finished Aug 23 04:43:38 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106163734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3106163734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_burst_wr.446678622
Short name T379
Test name
Test status
Simulation time 6164886673 ps
CPU time 57.21 seconds
Started Aug 23 04:42:51 PM UTC 24
Finished Aug 23 04:43:50 PM UTC 24
Peak memory 207296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446678622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.446678622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_datapath_stress.1391677455
Short name T503
Test name
Test status
Simulation time 5819769144 ps
CPU time 923.19 seconds
Started Aug 23 04:42:51 PM UTC 24
Finished Aug 23 04:58:23 PM UTC 24
Peak memory 784812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391677455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1391677455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_error.3115609033
Short name T384
Test name
Test status
Simulation time 10757456230 ps
CPU time 42.61 seconds
Started Aug 23 04:43:24 PM UTC 24
Finished Aug 23 04:44:08 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115609033 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3115609033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_long_msg.2620960296
Short name T374
Test name
Test status
Simulation time 10584854422 ps
CPU time 50.97 seconds
Started Aug 23 04:42:25 PM UTC 24
Finished Aug 23 04:43:18 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620960296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2620960296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_smoke.2201163304
Short name T368
Test name
Test status
Simulation time 168617838 ps
CPU time 7.14 seconds
Started Aug 23 04:42:16 PM UTC 24
Finished Aug 23 04:42:25 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201163304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2201163304
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_stress_all.2846555817
Short name T81
Test name
Test status
Simulation time 198405239797 ps
CPU time 1311.93 seconds
Started Aug 23 04:43:24 PM UTC 24
Finished Aug 23 05:05:29 PM UTC 24
Peak memory 514104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846555817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2846555817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/34.hmac_wipe_secret.1188563353
Short name T382
Test name
Test status
Simulation time 10315644055 ps
CPU time 32.62 seconds
Started Aug 23 04:43:24 PM UTC 24
Finished Aug 23 04:43:58 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188563353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1188563353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/34.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_alert_test.1315692457
Short name T385
Test name
Test status
Simulation time 80101569 ps
CPU time 0.54 seconds
Started Aug 23 04:44:08 PM UTC 24
Finished Aug 23 04:44:09 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315692457 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1315692457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_back_pressure.153284852
Short name T381
Test name
Test status
Simulation time 279690367 ps
CPU time 14.2 seconds
Started Aug 23 04:43:39 PM UTC 24
Finished Aug 23 04:43:54 PM UTC 24
Peak memory 207240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153284852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.153284852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_burst_wr.3747137475
Short name T168
Test name
Test status
Simulation time 1128381933 ps
CPU time 25.38 seconds
Started Aug 23 04:43:52 PM UTC 24
Finished Aug 23 04:44:19 PM UTC 24
Peak memory 207196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747137475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3747137475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_datapath_stress.2876067611
Short name T383
Test name
Test status
Simulation time 335968321 ps
CPU time 26.11 seconds
Started Aug 23 04:43:39 PM UTC 24
Finished Aug 23 04:44:06 PM UTC 24
Peak memory 252116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876067611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2876067611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_error.683837733
Short name T389
Test name
Test status
Simulation time 20609610611 ps
CPU time 59.54 seconds
Started Aug 23 04:43:52 PM UTC 24
Finished Aug 23 04:44:53 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683837733 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.683837733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_long_msg.1857177142
Short name T402
Test name
Test status
Simulation time 15419752788 ps
CPU time 158.77 seconds
Started Aug 23 04:43:37 PM UTC 24
Finished Aug 23 04:46:18 PM UTC 24
Peak memory 207520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857177142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1857177142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_smoke.1445492371
Short name T378
Test name
Test status
Simulation time 2736706929 ps
CPU time 10.4 seconds
Started Aug 23 04:43:26 PM UTC 24
Finished Aug 23 04:43:38 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445492371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1445492371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_stress_all.1638147590
Short name T387
Test name
Test status
Simulation time 10305854466 ps
CPU time 22.08 seconds
Started Aug 23 04:43:59 PM UTC 24
Finished Aug 23 04:44:23 PM UTC 24
Peak memory 207288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638147590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1638147590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/35.hmac_wipe_secret.3689258372
Short name T392
Test name
Test status
Simulation time 4956241004 ps
CPU time 73.94 seconds
Started Aug 23 04:43:55 PM UTC 24
Finished Aug 23 04:45:11 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689258372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3689258372
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/35.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_alert_test.3809381291
Short name T391
Test name
Test status
Simulation time 14522594 ps
CPU time 0.51 seconds
Started Aug 23 04:45:04 PM UTC 24
Finished Aug 23 04:45:05 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809381291 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3809381291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_back_pressure.4231413197
Short name T388
Test name
Test status
Simulation time 1810810409 ps
CPU time 14.16 seconds
Started Aug 23 04:44:14 PM UTC 24
Finished Aug 23 04:44:30 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231413197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.4231413197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_burst_wr.172875322
Short name T390
Test name
Test status
Simulation time 4232330393 ps
CPU time 41.26 seconds
Started Aug 23 04:44:19 PM UTC 24
Finished Aug 23 04:45:03 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172875322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.172875322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_datapath_stress.801472292
Short name T523
Test name
Test status
Simulation time 7644123501 ps
CPU time 1129.8 seconds
Started Aug 23 04:44:19 PM UTC 24
Finished Aug 23 05:03:21 PM UTC 24
Peak memory 809272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801472292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.801472292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_error.1606428368
Short name T401
Test name
Test status
Simulation time 4424772784 ps
CPU time 109.38 seconds
Started Aug 23 04:44:23 PM UTC 24
Finished Aug 23 04:46:15 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606428368 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1606428368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_long_msg.1297730076
Short name T394
Test name
Test status
Simulation time 4440489404 ps
CPU time 65.11 seconds
Started Aug 23 04:44:10 PM UTC 24
Finished Aug 23 04:45:16 PM UTC 24
Peak memory 207428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297730076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1297730076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_smoke.4134836231
Short name T386
Test name
Test status
Simulation time 3143528254 ps
CPU time 8.87 seconds
Started Aug 23 04:44:09 PM UTC 24
Finished Aug 23 04:44:19 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134836231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.4134836231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_stress_all.1330180353
Short name T526
Test name
Test status
Simulation time 73460999437 ps
CPU time 1532.38 seconds
Started Aug 23 04:44:54 PM UTC 24
Finished Aug 23 05:10:40 PM UTC 24
Peak memory 739624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330180353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1330180353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/36.hmac_wipe_secret.1048407390
Short name T396
Test name
Test status
Simulation time 9211969069 ps
CPU time 69.73 seconds
Started Aug 23 04:44:31 PM UTC 24
Finished Aug 23 04:45:42 PM UTC 24
Peak memory 207464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048407390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1048407390
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/36.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_alert_test.3257583224
Short name T400
Test name
Test status
Simulation time 15147101 ps
CPU time 0.51 seconds
Started Aug 23 04:46:12 PM UTC 24
Finished Aug 23 04:46:14 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257583224 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3257583224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_back_pressure.840003439
Short name T395
Test name
Test status
Simulation time 1284757832 ps
CPU time 19.21 seconds
Started Aug 23 04:45:12 PM UTC 24
Finished Aug 23 04:45:33 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840003439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.840003439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_burst_wr.2374486520
Short name T397
Test name
Test status
Simulation time 202350423 ps
CPU time 9.42 seconds
Started Aug 23 04:45:34 PM UTC 24
Finished Aug 23 04:45:44 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374486520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2374486520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_datapath_stress.350313171
Short name T407
Test name
Test status
Simulation time 990048486 ps
CPU time 131.81 seconds
Started Aug 23 04:45:18 PM UTC 24
Finished Aug 23 04:47:32 PM UTC 24
Peak memory 649440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350313171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.350313171
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_error.1355867846
Short name T420
Test name
Test status
Simulation time 14133083659 ps
CPU time 197.6 seconds
Started Aug 23 04:45:43 PM UTC 24
Finished Aug 23 04:49:04 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355867846 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1355867846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_long_msg.1789705635
Short name T405
Test name
Test status
Simulation time 2406420189 ps
CPU time 119.31 seconds
Started Aug 23 04:45:12 PM UTC 24
Finished Aug 23 04:47:14 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789705635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1789705635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_smoke.1313800111
Short name T393
Test name
Test status
Simulation time 383112134 ps
CPU time 4.99 seconds
Started Aug 23 04:45:06 PM UTC 24
Finished Aug 23 04:45:12 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313800111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1313800111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_stress_all.2632064875
Short name T438
Test name
Test status
Simulation time 5945150799 ps
CPU time 284.04 seconds
Started Aug 23 04:45:52 PM UTC 24
Finished Aug 23 04:50:40 PM UTC 24
Peak memory 262304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632064875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2632064875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/37.hmac_wipe_secret.2392621217
Short name T399
Test name
Test status
Simulation time 474323093 ps
CPU time 24.69 seconds
Started Aug 23 04:45:45 PM UTC 24
Finished Aug 23 04:46:11 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392621217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2392621217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/37.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_alert_test.637800547
Short name T409
Test name
Test status
Simulation time 46456376 ps
CPU time 0.52 seconds
Started Aug 23 04:47:38 PM UTC 24
Finished Aug 23 04:47:39 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637800547 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.637800547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_back_pressure.3517573998
Short name T408
Test name
Test status
Simulation time 6645278393 ps
CPU time 75.37 seconds
Started Aug 23 04:46:19 PM UTC 24
Finished Aug 23 04:47:36 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517573998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3517573998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_burst_wr.3705242615
Short name T406
Test name
Test status
Simulation time 5696548981 ps
CPU time 19.56 seconds
Started Aug 23 04:47:08 PM UTC 24
Finished Aug 23 04:47:28 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705242615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3705242615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_datapath_stress.994692138
Short name T435
Test name
Test status
Simulation time 3366223247 ps
CPU time 234.38 seconds
Started Aug 23 04:46:26 PM UTC 24
Finished Aug 23 04:50:24 PM UTC 24
Peak memory 477620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994692138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.994692138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_error.4139625596
Short name T428
Test name
Test status
Simulation time 43729693529 ps
CPU time 134.88 seconds
Started Aug 23 04:47:15 PM UTC 24
Finished Aug 23 04:49:32 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139625596 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.4139625596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_long_msg.1918702109
Short name T413
Test name
Test status
Simulation time 4573808612 ps
CPU time 118.18 seconds
Started Aug 23 04:46:16 PM UTC 24
Finished Aug 23 04:48:16 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918702109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1918702109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_smoke.1913872185
Short name T403
Test name
Test status
Simulation time 1952254412 ps
CPU time 10.21 seconds
Started Aug 23 04:46:14 PM UTC 24
Finished Aug 23 04:46:26 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913872185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1913872185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_stress_all.3362740824
Short name T448
Test name
Test status
Simulation time 18809423713 ps
CPU time 239.85 seconds
Started Aug 23 04:47:32 PM UTC 24
Finished Aug 23 04:51:36 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362740824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3362740824
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/38.hmac_wipe_secret.1545370959
Short name T412
Test name
Test status
Simulation time 2708441445 ps
CPU time 45.23 seconds
Started Aug 23 04:47:29 PM UTC 24
Finished Aug 23 04:48:16 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545370959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1545370959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/38.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_alert_test.2346419297
Short name T417
Test name
Test status
Simulation time 19699575 ps
CPU time 0.5 seconds
Started Aug 23 04:48:44 PM UTC 24
Finished Aug 23 04:48:45 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346419297 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2346419297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_back_pressure.564850711
Short name T414
Test name
Test status
Simulation time 417140891 ps
CPU time 21.28 seconds
Started Aug 23 04:48:00 PM UTC 24
Finished Aug 23 04:48:22 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564850711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.564850711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_burst_wr.3319410816
Short name T415
Test name
Test status
Simulation time 2301439371 ps
CPU time 5.73 seconds
Started Aug 23 04:48:17 PM UTC 24
Finished Aug 23 04:48:24 PM UTC 24
Peak memory 207332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319410816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3319410816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_datapath_stress.2202068866
Short name T462
Test name
Test status
Simulation time 2371172892 ps
CPU time 308.6 seconds
Started Aug 23 04:48:09 PM UTC 24
Finished Aug 23 04:53:22 PM UTC 24
Peak memory 686436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202068866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2202068866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_error.2044476612
Short name T430
Test name
Test status
Simulation time 40008257447 ps
CPU time 100.83 seconds
Started Aug 23 04:48:17 PM UTC 24
Finished Aug 23 04:50:00 PM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044476612 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2044476612
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_long_msg.3506207534
Short name T422
Test name
Test status
Simulation time 1654485614 ps
CPU time 81.04 seconds
Started Aug 23 04:47:49 PM UTC 24
Finished Aug 23 04:49:12 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506207534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3506207534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_smoke.1821455675
Short name T410
Test name
Test status
Simulation time 485362019 ps
CPU time 7.25 seconds
Started Aug 23 04:47:40 PM UTC 24
Finished Aug 23 04:47:48 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821455675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1821455675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_stress_all.686039679
Short name T446
Test name
Test status
Simulation time 10354984841 ps
CPU time 171.5 seconds
Started Aug 23 04:48:24 PM UTC 24
Finished Aug 23 04:51:19 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686039679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.686039679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/39.hmac_wipe_secret.1935650440
Short name T418
Test name
Test status
Simulation time 694713390 ps
CPU time 24.7 seconds
Started Aug 23 04:48:23 PM UTC 24
Finished Aug 23 04:48:49 PM UTC 24
Peak memory 207492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935650440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1935650440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/39.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_alert_test.1637876103
Short name T189
Test name
Test status
Simulation time 12148723 ps
CPU time 0.52 seconds
Started Aug 23 04:02:18 PM UTC 24
Finished Aug 23 04:02:20 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637876103 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1637876103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_back_pressure.2081292483
Short name T183
Test name
Test status
Simulation time 573342270 ps
CPU time 28.01 seconds
Started Aug 23 03:59:40 PM UTC 24
Finished Aug 23 04:00:09 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081292483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2081292483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_datapath_stress.1041671720
Short name T173
Test name
Test status
Simulation time 823865760 ps
CPU time 58.11 seconds
Started Aug 23 03:59:58 PM UTC 24
Finished Aug 23 04:00:58 PM UTC 24
Peak memory 436520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041671720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1041671720
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_error.2466847719
Short name T186
Test name
Test status
Simulation time 4468917136 ps
CPU time 70.89 seconds
Started Aug 23 04:00:11 PM UTC 24
Finished Aug 23 04:01:24 PM UTC 24
Peak memory 207452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466847719 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2466847719
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_long_msg.3672443144
Short name T185
Test name
Test status
Simulation time 11543827429 ps
CPU time 103.5 seconds
Started Aug 23 03:59:27 PM UTC 24
Finished Aug 23 04:01:13 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672443144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3672443144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_sec_cm.3968177645
Short name T67
Test name
Test status
Simulation time 102348250 ps
CPU time 0.96 seconds
Started Aug 23 04:02:15 PM UTC 24
Finished Aug 23 04:02:17 PM UTC 24
Peak memory 235572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968177645 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3968177645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_smoke.942350520
Short name T145
Test name
Test status
Simulation time 421947073 ps
CPU time 6.21 seconds
Started Aug 23 03:59:19 PM UTC 24
Finished Aug 23 03:59:27 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942350520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.942350520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_stress_all.2021300078
Short name T488
Test name
Test status
Simulation time 637919696799 ps
CPU time 3246.11 seconds
Started Aug 23 04:02:09 PM UTC 24
Finished Aug 23 04:56:44 PM UTC 24
Peak memory 837960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021300078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2021300078
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_hmac256_vectors.194355099
Short name T187
Test name
Test status
Simulation time 5005409591 ps
CPU time 46.26 seconds
Started Aug 23 04:01:23 PM UTC 24
Finished Aug 23 04:02:10 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194355099 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.194355099
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_hmac256_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_hmac384_vectors.3152118882
Short name T188
Test name
Test status
Simulation time 1664952765 ps
CPU time 47.93 seconds
Started Aug 23 04:01:25 PM UTC 24
Finished Aug 23 04:02:14 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152118882 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.3152118882
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_hmac384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_hmac512_vectors.2517649117
Short name T190
Test name
Test status
Simulation time 11219097721 ps
CPU time 74.57 seconds
Started Aug 23 04:01:38 PM UTC 24
Finished Aug 23 04:02:54 PM UTC 24
Peak memory 207340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517649117 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2517649117
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_hmac512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_sha384_vectors.798182115
Short name T345
Test name
Test status
Simulation time 217525948448 ps
CPU time 2273.23 seconds
Started Aug 23 04:01:12 PM UTC 24
Finished Aug 23 04:39:27 PM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798182115 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.798182115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_sha384_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_test_sha512_vectors.1693232165
Short name T308
Test name
Test status
Simulation time 140796667340 ps
CPU time 2023.48 seconds
Started Aug 23 04:01:14 PM UTC 24
Finished Aug 23 04:35:17 PM UTC 24
Peak memory 227452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_500_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693232165 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1693232165
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_test_sha512_vectors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/4.hmac_wipe_secret.1216633197
Short name T184
Test name
Test status
Simulation time 973630118 ps
CPU time 11.43 seconds
Started Aug 23 04:00:59 PM UTC 24
Finished Aug 23 04:01:11 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216633197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1216633197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/4.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_alert_test.3909284894
Short name T426
Test name
Test status
Simulation time 51905713 ps
CPU time 0.5 seconds
Started Aug 23 04:49:23 PM UTC 24
Finished Aug 23 04:49:25 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909284894 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.3909284894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_back_pressure.1316436335
Short name T423
Test name
Test status
Simulation time 432521339 ps
CPU time 21.26 seconds
Started Aug 23 04:48:52 PM UTC 24
Finished Aug 23 04:49:14 PM UTC 24
Peak memory 207244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316436335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1316436335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_burst_wr.80560130
Short name T424
Test name
Test status
Simulation time 1161395734 ps
CPU time 12.85 seconds
Started Aug 23 04:49:09 PM UTC 24
Finished Aug 23 04:49:23 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80560130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.80560130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_datapath_stress.627481749
Short name T514
Test name
Test status
Simulation time 4874875041 ps
CPU time 673.47 seconds
Started Aug 23 04:49:07 PM UTC 24
Finished Aug 23 05:00:27 PM UTC 24
Peak memory 723168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627481749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.627481749
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_error.4074811497
Short name T425
Test name
Test status
Simulation time 373640012 ps
CPU time 9.06 seconds
Started Aug 23 04:49:13 PM UTC 24
Finished Aug 23 04:49:23 PM UTC 24
Peak memory 207444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074811497 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4074811497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_long_msg.3287710779
Short name T432
Test name
Test status
Simulation time 24028363357 ps
CPU time 77.67 seconds
Started Aug 23 04:48:50 PM UTC 24
Finished Aug 23 04:50:09 PM UTC 24
Peak memory 207460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287710779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3287710779
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_smoke.1790351570
Short name T419
Test name
Test status
Simulation time 913694447 ps
CPU time 3.62 seconds
Started Aug 23 04:48:47 PM UTC 24
Finished Aug 23 04:48:52 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790351570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1790351570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_stress_all.573045800
Short name T80
Test name
Test status
Simulation time 109788882535 ps
CPU time 872.15 seconds
Started Aug 23 04:49:23 PM UTC 24
Finished Aug 23 05:04:04 PM UTC 24
Peak memory 708828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573045800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.573045800
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/40.hmac_wipe_secret.1695295356
Short name T433
Test name
Test status
Simulation time 42649011962 ps
CPU time 64.32 seconds
Started Aug 23 04:49:15 PM UTC 24
Finished Aug 23 04:50:21 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695295356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1695295356
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/40.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_alert_test.2259179560
Short name T434
Test name
Test status
Simulation time 11841675 ps
CPU time 0.49 seconds
Started Aug 23 04:50:22 PM UTC 24
Finished Aug 23 04:50:24 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259179560 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2259179560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_back_pressure.455432492
Short name T431
Test name
Test status
Simulation time 688396822 ps
CPU time 31.43 seconds
Started Aug 23 04:49:29 PM UTC 24
Finished Aug 23 04:50:02 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455432492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.455432492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_burst_wr.3506932465
Short name T439
Test name
Test status
Simulation time 3707968763 ps
CPU time 48.58 seconds
Started Aug 23 04:49:58 PM UTC 24
Finished Aug 23 04:50:48 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506932465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3506932465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_datapath_stress.52617283
Short name T454
Test name
Test status
Simulation time 1381301163 ps
CPU time 163.46 seconds
Started Aug 23 04:49:34 PM UTC 24
Finished Aug 23 04:52:20 PM UTC 24
Peak memory 454928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52617283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.52617283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_error.520607990
Short name T444
Test name
Test status
Simulation time 1492446912 ps
CPU time 70.7 seconds
Started Aug 23 04:50:01 PM UTC 24
Finished Aug 23 04:51:14 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520607990 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.520607990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_long_msg.1735031796
Short name T440
Test name
Test status
Simulation time 3817156422 ps
CPU time 89.79 seconds
Started Aug 23 04:49:25 PM UTC 24
Finished Aug 23 04:50:57 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735031796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1735031796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_smoke.3976987791
Short name T427
Test name
Test status
Simulation time 480487023 ps
CPU time 3 seconds
Started Aug 23 04:49:24 PM UTC 24
Finished Aug 23 04:49:28 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976987791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3976987791
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_stress_all.2898897699
Short name T471
Test name
Test status
Simulation time 76841163462 ps
CPU time 253.1 seconds
Started Aug 23 04:50:10 PM UTC 24
Finished Aug 23 04:54:27 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898897699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2898897699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/41.hmac_wipe_secret.4274576021
Short name T447
Test name
Test status
Simulation time 7240379586 ps
CPU time 81.41 seconds
Started Aug 23 04:50:03 PM UTC 24
Finished Aug 23 04:51:27 PM UTC 24
Peak memory 207284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274576021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4274576021
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/41.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_alert_test.1857243140
Short name T443
Test name
Test status
Simulation time 78877294 ps
CPU time 0.48 seconds
Started Aug 23 04:51:06 PM UTC 24
Finished Aug 23 04:51:08 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857243140 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1857243140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_back_pressure.1765060025
Short name T441
Test name
Test status
Simulation time 1798056446 ps
CPU time 24.1 seconds
Started Aug 23 04:50:33 PM UTC 24
Finished Aug 23 04:50:58 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765060025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1765060025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_burst_wr.479844163
Short name T442
Test name
Test status
Simulation time 3481431824 ps
CPU time 22.89 seconds
Started Aug 23 04:50:42 PM UTC 24
Finished Aug 23 04:51:06 PM UTC 24
Peak memory 207364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479844163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.479844163
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_datapath_stress.2465959339
Short name T525
Test name
Test status
Simulation time 11685703253 ps
CPU time 982.82 seconds
Started Aug 23 04:50:40 PM UTC 24
Finished Aug 23 05:07:11 PM UTC 24
Peak memory 784656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465959339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2465959339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_error.388675921
Short name T458
Test name
Test status
Simulation time 10070204761 ps
CPU time 121.89 seconds
Started Aug 23 04:50:49 PM UTC 24
Finished Aug 23 04:52:53 PM UTC 24
Peak memory 207352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388675921 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.388675921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_long_msg.2847486189
Short name T437
Test name
Test status
Simulation time 480828486 ps
CPU time 12.08 seconds
Started Aug 23 04:50:26 PM UTC 24
Finished Aug 23 04:50:39 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847486189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2847486189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_smoke.1922609210
Short name T436
Test name
Test status
Simulation time 1765513946 ps
CPU time 6.71 seconds
Started Aug 23 04:50:24 PM UTC 24
Finished Aug 23 04:50:32 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922609210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1922609210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_stress_all.2833078910
Short name T529
Test name
Test status
Simulation time 25284796085 ps
CPU time 2128.76 seconds
Started Aug 23 04:50:59 PM UTC 24
Finished Aug 23 05:26:47 PM UTC 24
Peak memory 850300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833078910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2833078910
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/42.hmac_wipe_secret.1768616567
Short name T456
Test name
Test status
Simulation time 28771947034 ps
CPU time 104.95 seconds
Started Aug 23 04:50:58 PM UTC 24
Finished Aug 23 04:52:45 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768616567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1768616567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/42.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_alert_test.3236382255
Short name T452
Test name
Test status
Simulation time 14537835 ps
CPU time 0.52 seconds
Started Aug 23 04:52:06 PM UTC 24
Finished Aug 23 04:52:08 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236382255 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3236382255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_back_pressure.1878264333
Short name T450
Test name
Test status
Simulation time 2516114011 ps
CPU time 28.64 seconds
Started Aug 23 04:51:16 PM UTC 24
Finished Aug 23 04:51:46 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878264333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1878264333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_burst_wr.3755681026
Short name T451
Test name
Test status
Simulation time 3694524981 ps
CPU time 36.01 seconds
Started Aug 23 04:51:28 PM UTC 24
Finished Aug 23 04:52:05 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755681026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3755681026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_datapath_stress.1613758570
Short name T516
Test name
Test status
Simulation time 15487141961 ps
CPU time 566.81 seconds
Started Aug 23 04:51:20 PM UTC 24
Finished Aug 23 05:00:52 PM UTC 24
Peak memory 741824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613758570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1613758570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_error.460412401
Short name T459
Test name
Test status
Simulation time 7404770211 ps
CPU time 90.06 seconds
Started Aug 23 04:51:39 PM UTC 24
Finished Aug 23 04:53:11 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460412401 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.460412401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_long_msg.919835843
Short name T457
Test name
Test status
Simulation time 3678122143 ps
CPU time 95.03 seconds
Started Aug 23 04:51:15 PM UTC 24
Finished Aug 23 04:52:52 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919835843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.919835843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_smoke.1587436793
Short name T445
Test name
Test status
Simulation time 517413283 ps
CPU time 5.82 seconds
Started Aug 23 04:51:08 PM UTC 24
Finished Aug 23 04:51:16 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587436793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1587436793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_stress_all.1389349481
Short name T528
Test name
Test status
Simulation time 28805967784 ps
CPU time 1977.93 seconds
Started Aug 23 04:51:47 PM UTC 24
Finished Aug 23 05:25:04 PM UTC 24
Peak memory 786868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389349481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1389349481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/43.hmac_wipe_secret.1402373699
Short name T455
Test name
Test status
Simulation time 2704196930 ps
CPU time 43.49 seconds
Started Aug 23 04:51:39 PM UTC 24
Finished Aug 23 04:52:24 PM UTC 24
Peak memory 207528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402373699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1402373699
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/43.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_alert_test.112573221
Short name T461
Test name
Test status
Simulation time 56708848 ps
CPU time 0.48 seconds
Started Aug 23 04:53:19 PM UTC 24
Finished Aug 23 04:53:20 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112573221 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.112573221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_back_pressure.901713913
Short name T464
Test name
Test status
Simulation time 1429228133 ps
CPU time 69.03 seconds
Started Aug 23 04:52:21 PM UTC 24
Finished Aug 23 04:53:31 PM UTC 24
Peak memory 207188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901713913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.901713913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_burst_wr.1094084467
Short name T460
Test name
Test status
Simulation time 2366427001 ps
CPU time 30.24 seconds
Started Aug 23 04:52:46 PM UTC 24
Finished Aug 23 04:53:18 PM UTC 24
Peak memory 207236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094084467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1094084467
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_datapath_stress.1223527762
Short name T522
Test name
Test status
Simulation time 18699735043 ps
CPU time 644.22 seconds
Started Aug 23 04:52:25 PM UTC 24
Finished Aug 23 05:03:15 PM UTC 24
Peak memory 729444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223527762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1223527762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_error.475343322
Short name T465
Test name
Test status
Simulation time 4541206523 ps
CPU time 49.57 seconds
Started Aug 23 04:52:53 PM UTC 24
Finished Aug 23 04:53:44 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475343322 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.475343322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_long_msg.2777276166
Short name T466
Test name
Test status
Simulation time 26747342467 ps
CPU time 92.64 seconds
Started Aug 23 04:52:13 PM UTC 24
Finished Aug 23 04:53:48 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777276166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2777276166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_smoke.2414173771
Short name T453
Test name
Test status
Simulation time 93025564 ps
CPU time 3.08 seconds
Started Aug 23 04:52:08 PM UTC 24
Finished Aug 23 04:52:13 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414173771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2414173771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_stress_all.2991036733
Short name T518
Test name
Test status
Simulation time 30731926767 ps
CPU time 487.69 seconds
Started Aug 23 04:53:12 PM UTC 24
Finished Aug 23 05:01:25 PM UTC 24
Peak memory 448748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991036733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2991036733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/44.hmac_wipe_secret.960485315
Short name T467
Test name
Test status
Simulation time 4787064266 ps
CPU time 78.4 seconds
Started Aug 23 04:52:54 PM UTC 24
Finished Aug 23 04:54:14 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960485315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.960485315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/44.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_alert_test.1531451846
Short name T470
Test name
Test status
Simulation time 54094082 ps
CPU time 0.52 seconds
Started Aug 23 04:54:21 PM UTC 24
Finished Aug 23 04:54:23 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531451846 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1531451846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_back_pressure.177584592
Short name T468
Test name
Test status
Simulation time 1065457279 ps
CPU time 45.77 seconds
Started Aug 23 04:53:28 PM UTC 24
Finished Aug 23 04:54:16 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177584592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.177584592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_burst_wr.1675005854
Short name T473
Test name
Test status
Simulation time 2015395381 ps
CPU time 45.28 seconds
Started Aug 23 04:53:45 PM UTC 24
Finished Aug 23 04:54:32 PM UTC 24
Peak memory 215832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675005854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1675005854
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_datapath_stress.3968894668
Short name T510
Test name
Test status
Simulation time 10907570353 ps
CPU time 350.55 seconds
Started Aug 23 04:53:33 PM UTC 24
Finished Aug 23 04:59:28 PM UTC 24
Peak memory 717024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968894668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3968894668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_error.2748082844
Short name T495
Test name
Test status
Simulation time 19038510691 ps
CPU time 226.18 seconds
Started Aug 23 04:53:50 PM UTC 24
Finished Aug 23 04:57:39 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748082844 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2748082844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_long_msg.102088534
Short name T478
Test name
Test status
Simulation time 5148173535 ps
CPU time 134.84 seconds
Started Aug 23 04:53:23 PM UTC 24
Finished Aug 23 04:55:41 PM UTC 24
Peak memory 217752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102088534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.102088534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_smoke.3689841056
Short name T463
Test name
Test status
Simulation time 292300500 ps
CPU time 4.4 seconds
Started Aug 23 04:53:22 PM UTC 24
Finished Aug 23 04:53:27 PM UTC 24
Peak memory 207508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689841056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3689841056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_stress_all.1275457388
Short name T84
Test name
Test status
Simulation time 284632344831 ps
CPU time 1797.83 seconds
Started Aug 23 04:54:17 PM UTC 24
Finished Aug 23 05:24:32 PM UTC 24
Peak memory 796912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275457388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1275457388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/45.hmac_wipe_secret.4249692739
Short name T482
Test name
Test status
Simulation time 2450350016 ps
CPU time 101.88 seconds
Started Aug 23 04:54:16 PM UTC 24
Finished Aug 23 04:56:00 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249692739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4249692739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/45.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_alert_test.2001645017
Short name T479
Test name
Test status
Simulation time 65632389 ps
CPU time 0.5 seconds
Started Aug 23 04:55:42 PM UTC 24
Finished Aug 23 04:55:44 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001645017 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2001645017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_back_pressure.4015565328
Short name T477
Test name
Test status
Simulation time 1113389819 ps
CPU time 58.23 seconds
Started Aug 23 04:54:35 PM UTC 24
Finished Aug 23 04:55:35 PM UTC 24
Peak memory 223592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015565328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4015565328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_burst_wr.2977753949
Short name T475
Test name
Test status
Simulation time 1768781915 ps
CPU time 27.15 seconds
Started Aug 23 04:54:37 PM UTC 24
Finished Aug 23 04:55:05 PM UTC 24
Peak memory 207324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977753949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2977753949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_datapath_stress.224130160
Short name T517
Test name
Test status
Simulation time 11670874783 ps
CPU time 380.95 seconds
Started Aug 23 04:54:35 PM UTC 24
Finished Aug 23 05:01:00 PM UTC 24
Peak memory 666092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224130160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.224130160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_error.338476200
Short name T485
Test name
Test status
Simulation time 46084959194 ps
CPU time 83.39 seconds
Started Aug 23 04:55:06 PM UTC 24
Finished Aug 23 04:56:31 PM UTC 24
Peak memory 207300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338476200 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.338476200
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_long_msg.1424944177
Short name T484
Test name
Test status
Simulation time 17717037865 ps
CPU time 106.65 seconds
Started Aug 23 04:54:28 PM UTC 24
Finished Aug 23 04:56:17 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424944177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1424944177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_smoke.801513213
Short name T474
Test name
Test status
Simulation time 20135966106 ps
CPU time 11.63 seconds
Started Aug 23 04:54:24 PM UTC 24
Finished Aug 23 04:54:36 PM UTC 24
Peak memory 215960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801513213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.801513213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_stress_all.2780157679
Short name T530
Test name
Test status
Simulation time 67555887073 ps
CPU time 2757.77 seconds
Started Aug 23 04:55:36 PM UTC 24
Finished Aug 23 05:42:00 PM UTC 24
Peak memory 847960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780157679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2780157679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/46.hmac_wipe_secret.201697112
Short name T487
Test name
Test status
Simulation time 24739195694 ps
CPU time 72.22 seconds
Started Aug 23 04:55:27 PM UTC 24
Finished Aug 23 04:56:42 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201697112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.201697112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/46.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_alert_test.1694147
Short name T489
Test name
Test status
Simulation time 25786862 ps
CPU time 0.5 seconds
Started Aug 23 04:56:43 PM UTC 24
Finished Aug 23 04:56:45 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694147 -assert nopostproc +UVM_TESTNAME=hmac_bas
e_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1694147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_back_pressure.3980922400
Short name T483
Test name
Test status
Simulation time 120864933 ps
CPU time 6.19 seconds
Started Aug 23 04:56:03 PM UTC 24
Finished Aug 23 04:56:10 PM UTC 24
Peak memory 207164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980922400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3980922400
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_burst_wr.249572618
Short name T486
Test name
Test status
Simulation time 11242274529 ps
CPU time 29.17 seconds
Started Aug 23 04:56:11 PM UTC 24
Finished Aug 23 04:56:42 PM UTC 24
Peak memory 216020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249572618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.249572618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_datapath_stress.359384087
Short name T515
Test name
Test status
Simulation time 1857301140 ps
CPU time 280.58 seconds
Started Aug 23 04:56:04 PM UTC 24
Finished Aug 23 05:00:48 PM UTC 24
Peak memory 721040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359384087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.359384087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_error.3086843923
Short name T509
Test name
Test status
Simulation time 23934029270 ps
CPU time 180.2 seconds
Started Aug 23 04:56:19 PM UTC 24
Finished Aug 23 04:59:21 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086843923 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3086843923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_long_msg.632634792
Short name T496
Test name
Test status
Simulation time 4137348419 ps
CPU time 102.12 seconds
Started Aug 23 04:55:57 PM UTC 24
Finished Aug 23 04:57:41 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632634792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.632634792
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_smoke.840815701
Short name T480
Test name
Test status
Simulation time 2634324930 ps
CPU time 11.35 seconds
Started Aug 23 04:55:44 PM UTC 24
Finished Aug 23 04:55:57 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840815701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.840815701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_stress_all.2495030218
Short name T520
Test name
Test status
Simulation time 94405689531 ps
CPU time 375.89 seconds
Started Aug 23 04:56:42 PM UTC 24
Finished Aug 23 05:03:02 PM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495030218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2495030218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/47.hmac_wipe_secret.1471493977
Short name T490
Test name
Test status
Simulation time 26282612193 ps
CPU time 22.38 seconds
Started Aug 23 04:56:32 PM UTC 24
Finished Aug 23 04:56:56 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471493977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1471493977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/47.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_alert_test.1225938148
Short name T497
Test name
Test status
Simulation time 43344735 ps
CPU time 0.52 seconds
Started Aug 23 04:57:42 PM UTC 24
Finished Aug 23 04:57:44 PM UTC 24
Peak memory 203672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225938148 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1225938148
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_back_pressure.3010534396
Short name T494
Test name
Test status
Simulation time 13265634502 ps
CPU time 40.12 seconds
Started Aug 23 04:56:57 PM UTC 24
Finished Aug 23 04:57:39 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010534396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3010534396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_burst_wr.816462841
Short name T493
Test name
Test status
Simulation time 540354296 ps
CPU time 26.41 seconds
Started Aug 23 04:57:04 PM UTC 24
Finished Aug 23 04:57:31 PM UTC 24
Peak memory 207200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816462841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.816462841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_datapath_stress.1134539385
Short name T519
Test name
Test status
Simulation time 17286898795 ps
CPU time 314.4 seconds
Started Aug 23 04:57:01 PM UTC 24
Finished Aug 23 05:02:19 PM UTC 24
Peak memory 672224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134539385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1134539385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_error.2300426236
Short name T499
Test name
Test status
Simulation time 1861261662 ps
CPU time 19.28 seconds
Started Aug 23 04:57:32 PM UTC 24
Finished Aug 23 04:57:52 PM UTC 24
Peak memory 207124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300426236 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2300426236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_long_msg.367979962
Short name T505
Test name
Test status
Simulation time 4026060021 ps
CPU time 99.01 seconds
Started Aug 23 04:56:52 PM UTC 24
Finished Aug 23 04:58:33 PM UTC 24
Peak memory 207260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367979962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.367979962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_smoke.72415915
Short name T492
Test name
Test status
Simulation time 704225835 ps
CPU time 10.84 seconds
Started Aug 23 04:56:51 PM UTC 24
Finished Aug 23 04:57:03 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72415915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 48.hmac_smoke.72415915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/48.hmac_wipe_secret.983863155
Short name T501
Test name
Test status
Simulation time 8306698706 ps
CPU time 26.38 seconds
Started Aug 23 04:57:41 PM UTC 24
Finished Aug 23 04:58:09 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983863155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/d
efault.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.983863155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/48.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_alert_test.1820027923
Short name T506
Test name
Test status
Simulation time 19007849 ps
CPU time 0.49 seconds
Started Aug 23 04:58:36 PM UTC 24
Finished Aug 23 04:58:38 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820027923 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1820027923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_back_pressure.114200427
Short name T500
Test name
Test status
Simulation time 916177332 ps
CPU time 11.56 seconds
Started Aug 23 04:57:53 PM UTC 24
Finished Aug 23 04:58:06 PM UTC 24
Peak memory 207184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114200427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.114200427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_burst_wr.3694408623
Short name T507
Test name
Test status
Simulation time 11680896576 ps
CPU time 42.62 seconds
Started Aug 23 04:58:07 PM UTC 24
Finished Aug 23 04:58:51 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694408623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3694408623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_datapath_stress.42633259
Short name T502
Test name
Test status
Simulation time 853823509 ps
CPU time 17.4 seconds
Started Aug 23 04:57:58 PM UTC 24
Finished Aug 23 04:58:16 PM UTC 24
Peak memory 249956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42633259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UV
M_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.42633259
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_error.1626289899
Short name T512
Test name
Test status
Simulation time 35625467824 ps
CPU time 102.26 seconds
Started Aug 23 04:58:10 PM UTC 24
Finished Aug 23 04:59:54 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626289899 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1626289899
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_long_msg.2723326368
Short name T508
Test name
Test status
Simulation time 29916310546 ps
CPU time 85.44 seconds
Started Aug 23 04:57:51 PM UTC 24
Finished Aug 23 04:59:19 PM UTC 24
Peak memory 218008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723326368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2723326368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_smoke.808121306
Short name T498
Test name
Test status
Simulation time 1309423915 ps
CPU time 5.12 seconds
Started Aug 23 04:57:44 PM UTC 24
Finished Aug 23 04:57:50 PM UTC 24
Peak memory 207268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808121306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.808121306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_stress_all.1306756681
Short name T511
Test name
Test status
Simulation time 1889275266 ps
CPU time 76.53 seconds
Started Aug 23 04:58:25 PM UTC 24
Finished Aug 23 04:59:43 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306756681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1306756681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/49.hmac_wipe_secret.3371722940
Short name T102
Test name
Test status
Simulation time 36220458651 ps
CPU time 134.29 seconds
Started Aug 23 04:58:17 PM UTC 24
Finished Aug 23 05:00:34 PM UTC 24
Peak memory 207252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371722940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3371722940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/49.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_alert_test.601528250
Short name T192
Test name
Test status
Simulation time 14026638 ps
CPU time 0.5 seconds
Started Aug 23 04:04:26 PM UTC 24
Finished Aug 23 04:04:28 PM UTC 24
Peak memory 203728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601528250 -assert nopostproc +UVM_TESTNAME=hmac_b
ase_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hm
ac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.601528250
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_back_pressure.3412817517
Short name T171
Test name
Test status
Simulation time 2432204629 ps
CPU time 59.94 seconds
Started Aug 23 04:02:55 PM UTC 24
Finished Aug 23 04:03:57 PM UTC 24
Peak memory 207304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412817517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3412817517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_burst_wr.3430281928
Short name T158
Test name
Test status
Simulation time 46079879540 ps
CPU time 45.26 seconds
Started Aug 23 04:03:36 PM UTC 24
Finished Aug 23 04:04:23 PM UTC 24
Peak memory 207320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430281928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3430281928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_datapath_stress.1444381326
Short name T200
Test name
Test status
Simulation time 2528104509 ps
CPU time 329.36 seconds
Started Aug 23 04:03:00 PM UTC 24
Finished Aug 23 04:08:33 PM UTC 24
Peak memory 479596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444381326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1444381326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_error.3708679266
Short name T174
Test name
Test status
Simulation time 9278277961 ps
CPU time 108.87 seconds
Started Aug 23 04:03:55 PM UTC 24
Finished Aug 23 04:05:46 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708679266 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3708679266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_long_msg.961351053
Short name T157
Test name
Test status
Simulation time 6896007904 ps
CPU time 88.92 seconds
Started Aug 23 04:02:27 PM UTC 24
Finished Aug 23 04:03:58 PM UTC 24
Peak memory 217876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961351053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.961351053
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_smoke.2957749764
Short name T147
Test name
Test status
Simulation time 1423003410 ps
CPU time 4.27 seconds
Started Aug 23 04:02:20 PM UTC 24
Finished Aug 23 04:02:26 PM UTC 24
Peak memory 207224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957749764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2957749764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_stress_all.3539650906
Short name T191
Test name
Test status
Simulation time 540018254 ps
CPU time 24.81 seconds
Started Aug 23 04:03:59 PM UTC 24
Finished Aug 23 04:04:25 PM UTC 24
Peak memory 207192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539650906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3539650906
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/5.hmac_wipe_secret.1680841179
Short name T126
Test name
Test status
Simulation time 3195689256 ps
CPU time 45.13 seconds
Started Aug 23 04:03:58 PM UTC 24
Finished Aug 23 04:04:44 PM UTC 24
Peak memory 207504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680841179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1680841179
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/5.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_alert_test.1376393979
Short name T195
Test name
Test status
Simulation time 12815526 ps
CPU time 0.51 seconds
Started Aug 23 04:05:47 PM UTC 24
Finished Aug 23 04:05:49 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376393979 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1376393979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_back_pressure.2882491057
Short name T193
Test name
Test status
Simulation time 210631469 ps
CPU time 9.91 seconds
Started Aug 23 04:04:46 PM UTC 24
Finished Aug 23 04:04:57 PM UTC 24
Peak memory 207088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882491057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2882491057
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_burst_wr.4095619527
Short name T159
Test name
Test status
Simulation time 2134698186 ps
CPU time 24.87 seconds
Started Aug 23 04:04:51 PM UTC 24
Finished Aug 23 04:05:17 PM UTC 24
Peak memory 207264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095619527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4095619527
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_datapath_stress.1514419028
Short name T217
Test name
Test status
Simulation time 17551676255 ps
CPU time 586.81 seconds
Started Aug 23 04:04:47 PM UTC 24
Finished Aug 23 04:14:40 PM UTC 24
Peak memory 770412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514419028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1514419028
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_error.2790249707
Short name T194
Test name
Test status
Simulation time 536090035 ps
CPU time 6.93 seconds
Started Aug 23 04:04:58 PM UTC 24
Finished Aug 23 04:05:06 PM UTC 24
Peak memory 207056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790249707 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2790249707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_long_msg.120147541
Short name T89
Test name
Test status
Simulation time 16463634502 ps
CPU time 124.05 seconds
Started Aug 23 04:04:35 PM UTC 24
Finished Aug 23 04:06:42 PM UTC 24
Peak memory 207308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120147541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.120147541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_smoke.1372300344
Short name T154
Test name
Test status
Simulation time 680311751 ps
CPU time 4.07 seconds
Started Aug 23 04:04:29 PM UTC 24
Finished Aug 23 04:04:35 PM UTC 24
Peak memory 207392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372300344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1372300344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/6.hmac_wipe_secret.1827522035
Short name T127
Test name
Test status
Simulation time 2946129772 ps
CPU time 66.7 seconds
Started Aug 23 04:05:07 PM UTC 24
Finished Aug 23 04:06:15 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827522035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1827522035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/6.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_alert_test.1564119010
Short name T90
Test name
Test status
Simulation time 22461263 ps
CPU time 0.48 seconds
Started Aug 23 04:06:43 PM UTC 24
Finished Aug 23 04:06:45 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564119010 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1564119010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_back_pressure.2794779652
Short name T197
Test name
Test status
Simulation time 1535609331 ps
CPU time 15.56 seconds
Started Aug 23 04:06:01 PM UTC 24
Finished Aug 23 04:06:18 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794779652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2794779652
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_burst_wr.572380270
Short name T27
Test name
Test status
Simulation time 616578683 ps
CPU time 13.28 seconds
Started Aug 23 04:06:16 PM UTC 24
Finished Aug 23 04:06:31 PM UTC 24
Peak memory 207448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572380270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hma
c_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.572380270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_datapath_stress.2434634302
Short name T205
Test name
Test status
Simulation time 7369138739 ps
CPU time 264.06 seconds
Started Aug 23 04:06:04 PM UTC 24
Finished Aug 23 04:10:31 PM UTC 24
Peak memory 688564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434634302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2434634302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_error.476166068
Short name T91
Test name
Test status
Simulation time 642503301 ps
CPU time 30.39 seconds
Started Aug 23 04:06:19 PM UTC 24
Finished Aug 23 04:06:51 PM UTC 24
Peak memory 207136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476166068 -assert nopostproc +UVM_TESTNAME=hma
c_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/
hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.476166068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_long_msg.1651197297
Short name T88
Test name
Test status
Simulation time 2903747326 ps
CPU time 45.07 seconds
Started Aug 23 04:05:52 PM UTC 24
Finished Aug 23 04:06:39 PM UTC 24
Peak memory 207388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651197297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1651197297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_smoke.1618125039
Short name T196
Test name
Test status
Simulation time 43450323 ps
CPU time 1.11 seconds
Started Aug 23 04:05:49 PM UTC 24
Finished Aug 23 04:05:51 PM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618125039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1618125039
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_stress_all.344695335
Short name T166
Test name
Test status
Simulation time 146698016169 ps
CPU time 2238.46 seconds
Started Aug 23 04:06:32 PM UTC 24
Finished Aug 23 04:44:10 PM UTC 24
Peak memory 833704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344695335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.344695335
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/7.hmac_wipe_secret.3103623246
Short name T128
Test name
Test status
Simulation time 4195216192 ps
CPU time 94.96 seconds
Started Aug 23 04:06:27 PM UTC 24
Finished Aug 23 04:08:03 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103623246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.3103623246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/7.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_alert_test.3689250379
Short name T199
Test name
Test status
Simulation time 22208843 ps
CPU time 0.52 seconds
Started Aug 23 04:08:09 PM UTC 24
Finished Aug 23 04:08:11 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689250379 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3689250379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_back_pressure.3769031168
Short name T93
Test name
Test status
Simulation time 539426390 ps
CPU time 27.54 seconds
Started Aug 23 04:06:58 PM UTC 24
Finished Aug 23 04:07:26 PM UTC 24
Peak memory 207220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769031168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3769031168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_burst_wr.1212511176
Short name T94
Test name
Test status
Simulation time 4987251829 ps
CPU time 7.65 seconds
Started Aug 23 04:07:27 PM UTC 24
Finished Aug 23 04:07:36 PM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212511176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1212511176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_datapath_stress.1504570062
Short name T201
Test name
Test status
Simulation time 4037618229 ps
CPU time 118.66 seconds
Started Aug 23 04:07:12 PM UTC 24
Finished Aug 23 04:09:13 PM UTC 24
Peak memory 448800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504570062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hma
c-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1504570062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_error.2454069073
Short name T203
Test name
Test status
Simulation time 98034285150 ps
CPU time 165.92 seconds
Started Aug 23 04:07:37 PM UTC 24
Finished Aug 23 04:10:26 PM UTC 24
Peak memory 207384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454069073 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2454069073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_long_msg.1760058618
Short name T202
Test name
Test status
Simulation time 96531483768 ps
CPU time 181.85 seconds
Started Aug 23 04:06:53 PM UTC 24
Finished Aug 23 04:09:57 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760058618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1760058618
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_smoke.1260524701
Short name T92
Test name
Test status
Simulation time 2423293269 ps
CPU time 9.75 seconds
Started Aug 23 04:06:45 PM UTC 24
Finished Aug 23 04:06:56 PM UTC 24
Peak memory 207256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260524701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1260524701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_stress_all.852548587
Short name T372
Test name
Test status
Simulation time 202291906034 ps
CPU time 2105.52 seconds
Started Aug 23 04:07:48 PM UTC 24
Finished Aug 23 04:43:14 PM UTC 24
Peak memory 768288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852548587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=h
mac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.852548587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_stress_all_with_rand_reset.527561907
Short name T25
Test name
Test status
Simulation time 9394339987 ps
CPU time 177.37 seconds
Started Aug 23 04:08:05 PM UTC 24
Finished Aug 23 04:11:05 PM UTC 24
Peak memory 413816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52756190
7 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.527561907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/8.hmac_wipe_secret.3322685664
Short name T95
Test name
Test status
Simulation time 2574917397 ps
CPU time 7.85 seconds
Started Aug 23 04:07:38 PM UTC 24
Finished Aug 23 04:07:47 PM UTC 24
Peak memory 207160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322685664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3322685664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/8.hmac_wipe_secret/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_alert_test.2663822542
Short name T204
Test name
Test status
Simulation time 133642974 ps
CPU time 0.55 seconds
Started Aug 23 04:10:27 PM UTC 24
Finished Aug 23 04:10:29 PM UTC 24
Peak memory 203668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663822542 -assert nopostproc +UVM_TESTNAME=hmac_
base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/h
mac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2663822542
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_back_pressure.2512977046
Short name T24
Test name
Test status
Simulation time 2379851402 ps
CPU time 58.44 seconds
Started Aug 23 04:08:34 PM UTC 24
Finished Aug 23 04:09:34 PM UTC 24
Peak memory 207516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512977046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +
UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2512977046
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_back_pressure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_burst_wr.82624403
Short name T28
Test name
Test status
Simulation time 943336929 ps
CPU time 42.5 seconds
Started Aug 23 04:09:35 PM UTC 24
Finished Aug 23 04:10:19 PM UTC 24
Peak memory 207328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82624403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac
_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.82624403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_burst_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_datapath_stress.264731320
Short name T236
Test name
Test status
Simulation time 22684595313 ps
CPU time 757.53 seconds
Started Aug 23 04:09:14 PM UTC 24
Finished Aug 23 04:21:58 PM UTC 24
Peak memory 712980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264731320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +U
VM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.264731320
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_datapath_stress/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_error.2717068702
Short name T206
Test name
Test status
Simulation time 5231582659 ps
CPU time 63.03 seconds
Started Aug 23 04:09:59 PM UTC 24
Finished Aug 23 04:11:03 PM UTC 24
Peak memory 207456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717068702 -assert nopostproc +UVM_TESTNAME=hm
ac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22
/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2717068702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_long_msg.2849146701
Short name T170
Test name
Test status
Simulation time 9645603379 ps
CPU time 105.8 seconds
Started Aug 23 04:08:21 PM UTC 24
Finished Aug 23 04:10:09 PM UTC 24
Peak memory 215768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849146701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2849146701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_long_msg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_smoke.1276241816
Short name T152
Test name
Test status
Simulation time 1144053536 ps
CPU time 6.61 seconds
Started Aug 23 04:08:13 PM UTC 24
Finished Aug 23 04:08:20 PM UTC 24
Peak memory 207396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276241816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1276241816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_stress_all.3400475417
Short name T354
Test name
Test status
Simulation time 532891043798 ps
CPU time 1802.61 seconds
Started Aug 23 04:10:09 PM UTC 24
Finished Aug 23 04:40:28 PM UTC 24
Peak memory 778528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400475417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=
hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage
/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3400475417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_stress_all_with_rand_reset.3239428600
Short name T15
Test name
Test status
Simulation time 3104967055 ps
CPU time 49.36 seconds
Started Aug 23 04:10:20 PM UTC 24
Finished Aug 23 04:11:11 PM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +test_vectors_dir=/workspaces/repo/scratch/os_regression_2024_08_22/hmac-s
im-vcs/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_in
strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32394286
00 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3239428600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/default/9.hmac_wipe_secret.3932334817
Short name T96
Test name
Test status
Simulation time 16864768248 ps
CPU time 98.18 seconds
Started Aug 23 04:10:03 PM UTC 24
Finished Aug 23 04:11:43 PM UTC 24
Peak memory 207248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932334817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hm
ac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/coverage/
default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3932334817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/hmac-sim-vcs/9.hmac_wipe_secret/latest
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