Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	16712499	1			T1	11994		T4	751		T5	1672
all_values[1]	16712499	1			T1	11994		T4	751		T5	1672
all_values[2]	16712499	1			T1	11994		T4	751		T5	1672

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270147

1

T6

190

T24

611

T7

2

auto[1]

49867350

1

T1

35982

T4

2253

T5

5016

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42721657

1

T1

31936

T4

1897

T5

4393

auto[1]

7415840

1

T1

4046

T4

356

T5

623

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	87285	1			T6	134		T7	2		T9	1263
all_values[0]	auto[0]	auto[1]	298	1			T9	2		T12	2		T132	2
all_values[0]	auto[1]	auto[0]	16606570	1			T1	11978		T4	742		T5	1651
all_values[0]	auto[1]	auto[1]	18346	1			T1	16		T4	9		T5	21
all_values[1]	auto[0]	auto[0]	103063	1			T6	54		T24	611		T11	1
all_values[1]	auto[0]	auto[1]	178	1			T18	2		T31	1		T32	1
all_values[1]	auto[1]	auto[0]	16608973	1			T1	11994		T4	751		T5	1672
all_values[1]	auto[1]	auto[1]	285	1			T27	7		T28	5		T12	1
all_values[2]	auto[0]	auto[0]	41011	1			T6	1		T10	1		T11	1
all_values[2]	auto[0]	auto[1]	38312	1			T6	1		T10	266		T27	36
all_values[2]	auto[1]	auto[0]	9274755	1			T1	7964		T4	404		T5	1070
all_values[2]	auto[1]	auto[1]	7358421	1			T1	4030		T4	347		T5	602