Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

103920

1

T1

14

T4

12

T5

30

auto[1]

114022

1

T1

26

T4

22

T5

10

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	82185	1			T1	18		T24	6		T8	3
len_1026_2046	5063	1			T4	7		T25	2		T7	1
len_514_1022	3150	1			T5	5		T7	6		T33	2
len_2_510	2791	1			T1	2		T5	1		T7	5
len_2056	175	1			T6	7		T7	3		T148	4
len_2048	318	1			T5	1		T6	2		T7	2
len_2040	170	1			T4	4		T5	2		T7	2
len_1032	195	1			T6	2		T25	3		T7	2
len_1024	1769	1			T4	2		T25	1		T7	2
len_1016	158	1			T5	2		T7	1		T11	3
len_520	171	1			T149	1		T150	1		T151	1
len_512	399	1			T4	2		T6	3		T25	3
len_504	185	1			T4	1		T5	4		T25	4
len_8	1130	1			T24	1		T120	3		T152	2
len_0	11110	1			T4	1		T5	5		T6	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

116

1

T9

2

T56

2

T153

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	41093	1			T1	6		T24	3		T9	6
auto[0]	len_1026_2046	2408	1			T4	1		T25	1		T7	1
auto[0]	len_514_1022	2094	1			T5	5		T7	4		T33	2
auto[0]	len_2_510	1677	1			T1	1		T7	3		T11	4
auto[0]	len_2056	94	1			T6	7		T148	4		T154	1
auto[0]	len_2048	176	1			T5	1		T6	2		T7	1
auto[0]	len_2040	88	1			T4	1		T5	2		T149	2
auto[0]	len_1032	103	1			T6	1		T25	2		T13	3
auto[0]	len_1024	228	1			T7	2		T33	2		T56	1
auto[0]	len_1016	75	1			T11	2		T30	2		T149	3
auto[0]	len_520	100	1			T149	1		T151	1		T64	1
auto[0]	len_512	242	1			T4	2		T6	2		T25	2
auto[0]	len_504	106	1			T4	1		T5	3		T25	2
auto[0]	len_8	31	1			T24	1		T120	2		T155	1
auto[0]	len_0	3443	1			T4	1		T5	4		T6	1
auto[1]	len_2050_plus	41092	1			T1	12		T24	3		T8	3
auto[1]	len_1026_2046	2655	1			T4	6		T25	1		T9	2
auto[1]	len_514_1022	1056	1			T7	2		T54	11		T27	3
auto[1]	len_2_510	1114	1			T1	1		T5	1		T7	2
auto[1]	len_2056	81	1			T7	3		T154	3		T30	1
auto[1]	len_2048	142	1			T7	1		T54	2		T148	1
auto[1]	len_2040	82	1			T4	3		T7	2		T149	1
auto[1]	len_1032	92	1			T6	1		T25	1		T7	2
auto[1]	len_1024	1541	1			T4	2		T25	1		T54	1
auto[1]	len_1016	83	1			T5	2		T7	1		T11	1
auto[1]	len_520	71	1			T150	1		T90	2		T64	4
auto[1]	len_512	157	1			T6	1		T25	1		T7	2
auto[1]	len_504	79	1			T5	1		T25	2		T154	2
auto[1]	len_8	1099	1			T120	1		T152	2		T156	1
auto[1]	len_0	7667	1			T5	1		T25	2		T24	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

64

1

T56

2

T153

2

T157

2

auto[1]

len_upper

52

1

T9

2

T158

3

T152

1