Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/hmac-sim-vcs/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4156238

1

T1

1929

T4

174

T5

308

auto[1]

2695788

1

T1

4063

T4

168

T5

347

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2717872

1

T1

2007

T4

182

T5

516

auto[1]

4134154

1

T1

3985

T4

160

T5

139

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2945312

1

T1

2515

T4

99

T5

329

auto[1]

3906714

1

T1

3477

T4

243

T5

326

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4225628

1

T1

2882

T4

277

T5

268

auto[1]

2626398

1

T1

3110

T4

65

T5

387

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6172170	1			T1	5905		T4	340		T5	601
fifo_depth[1]	115677	1			T1	65		T4	1		T5	5
fifo_depth[2]	91054	1			T1	18		T4	1		T5	5
fifo_depth[3]	72844	1			T1	4		T5	9		T6	5
fifo_depth[4]	64870	1			T5	8		T6	9		T24	50
fifo_depth[5]	51750	1			T5	8		T6	6		T24	34
fifo_depth[6]	40937	1			T5	6		T6	2		T24	20
fifo_depth[7]	27019	1			T5	3		T6	1		T24	7

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679856

1

T1

87

T4

2

T5

54

auto[1]

6172170

1

T1

5905

T4

340

T5

601

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6841251

1

T1

5992

T4

342

T5

655

auto[1]

10775

1

T33

563

T27

153

T28

415

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

34808

1

T5

6

T60

17

T54

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

31515

1

T6

5

T10

1

T26

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30079

1

T5

6

T8

138

T28

3595

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

32948

1

T6

12

T9

1

T28

507

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

161992

1

T33

243

T56

3

T54

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

23216

1

T6

5

T11

12

T33

638

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

23813

1

T1

24

T6

4

T24

197

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

29891

1

T1

13

T11

15

T56

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41091

1

T5

15

T8

53

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37045

1

T11

2

T163

513

T164

32

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39288

1

T1

10

T4

1

T25

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

43509

1

T1

10

T5

5

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39784

1

T1

1

T4

1

T8

49

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34612

1

T1

18

T5

15

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41212

1

T7

1

T9

1

T27

856

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35053

1

T1

11

T5

7

T6

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

141648

1

T5

32

T6

40

T25

37

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

166272

1

T1

9

T4

1

T5

134

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

143187

1

T4

16

T5

106

T8

242

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

156560

1

T4

10

T6

31

T25

13

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1533585

1

T1

436

T4

52

T6

81

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

142422

1

T1

402

T6

47

T25

28

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

134887

1

T1

1105

T5

1

T6

80

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

158489

1

T1

526

T4

20

T5

44

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

428738

1

T4

29

T5

55

T25

52

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

439449

1

T4

19

T5

25

T6

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

477739

1

T1

824

T4

106

T5

46

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

473996

1

T1

1154

T5

86

T6

17

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

507316

1

T1

482

T4

72

T25

48

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

392745

1

T1

581

T5

26

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

446461

1

T5

1

T25

44

T24

303

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

428676

1

T1

386

T4

15

T5

45

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

175543

1

T5

38

T6

40

T25

37

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

197377

1

T1

9

T4

1

T5

134

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

172552

1

T4

16

T5

112

T8

380

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

187443

1

T4

10

T6

43

T25

13

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1694908

1

T1

436

T4

52

T6

81

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

164873

1

T1

402

T6

52

T25

28

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

158290

1

T1

1129

T5

1

T6

84

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

187387

1

T1

539

T4

20

T5

44

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

469058

1

T4

29

T5

70

T25

52

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

476389

1

T4

19

T5

25

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

516313

1

T1

834

T4

107

T5

46

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

517208

1

T1

1164

T5

91

T6

17

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

546598

1

T1

483

T4

73

T25

48

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

426539

1

T1

599

T5

41

T6

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

487272

1

T5

1

T25

44

T24

303

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

463501

1

T1

397

T4

15

T5

52

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

913

1

T28

147

T29

23

T165

28

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

410

1

T27

1

T29

6

T166

13

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

714

1

T28

19

T163

176

T29

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

2065

1

T28

54

T165

1

T166

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

669

1

T33

98

T27

9

T29

32

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

765

1

T33

12

T97

1

T167

162

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

410

1

T27

62

T166

13

T42

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

993

1

T28

12

T29

4

T91

15

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

771

1

T33

453

T28

17

T29

79

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

105

1

T168

20

T169

6

T97

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

714

1

T27

1

T28

1

T15

33

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

297

1

T134

26

T97

1

T170

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

502

1

T27

12

T28

17

T97

11

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

818

1

T28

106

T42

7

T168

8

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

401

1

T27

68

T28

1

T15

23

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

228

1

T28

41

T15

98

T171

7

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

141648

1

T5

32

T6

40

T25

37

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

166272

1

T1

9

T4

1

T5

134

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

143187

1

T4

16

T5

106

T8

242

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

156560

1

T4

10

T6

31

T25

13

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1533585

1

T1

436

T4

52

T6

81

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

142422

1

T1

402

T6

47

T25

28

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

134887

1

T1

1105

T5

1

T6

80

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

158489

1

T1

526

T4

20

T5

44

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

428738

1

T4

29

T5

55

T25

52

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

439449

1

T4

19

T5

25

T6

1

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

477739

1

T1

824

T4

106

T5

46

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

473996

1

T1

1154

T5

86

T6

17

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

507316

1

T1

482

T4

72

T25

48

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

392745

1

T1

581

T5

26

T6

1

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

446461

1

T5

1

T25

44

T24

303

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

428676

1

T1

386

T4

15

T5

45

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3171

1

T60

10

T54

3

T76

14

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3397

1

T6

1

T26

3

T33

9

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3156

1

T5

1

T8

35

T28

7

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

3474

1

T6

2

T28

8

T154

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

42329

1

T33

1

T54

1

T132

10

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

2795

1

T6

1

T11

10

T54

4

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

3006

1

T1

20

T6

1

T24

33

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3671

1

T1

8

T11

11

T54

4

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

5770

1

T5

2

T8

9

T7

1

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

6068

1

T11

1

T163

2

T164

7

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6061

1

T1

6

T4

1

T25

1

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6822

1

T1

6

T25

1

T76

19

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

7947

1

T8

6

T7

3

T28

2

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

4886

1

T1

16

T5

2

T11

1

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6689

1

T7

1

T148

1

T120

27

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6435

1

T1

9

T25

1

T24

9

fifo_depth[2]

auto[0]

auto[0]

auto[0]

auto[0]

2615

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26

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40

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5

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4

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23

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38

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7

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28

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36

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12

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19

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67

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4

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5

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1

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1

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12

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16

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177

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8

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24

fifo_depth[4]

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161

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1

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1

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1

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6

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15

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6

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4

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5

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17

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4

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20

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3

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20

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1

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6

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3

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1

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4

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10

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14

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9

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16

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166

fifo_depth[5]

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7

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2

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150

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39

fifo_depth[5]

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3

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41

fifo_depth[6]

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6

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172

fifo_depth[6]

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8

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1

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13

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8

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1

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4

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23

fifo_depth[6]

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15

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10

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3

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16

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4

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14

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3

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1

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1

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33

fifo_depth[6]

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1

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7

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3

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1

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8

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12

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9

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40

T28

3

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1

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6

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179

T163

3

fifo_depth[7]

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1

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7

T30

1

fifo_depth[7]

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1

T33

1

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182

T55

1

fifo_depth[7]

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1

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2

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1

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1

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1

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3

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19

T76

9

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1

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1

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15

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16

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1

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1

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4

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4

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1

T163

6

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2

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8

fifo_depth[7]

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1

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1

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1

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1

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1

T5

1

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10

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2

fifo_depth[7]

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1

T8

3

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1

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5

fifo_depth[7]

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1

T5

1

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1

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16

fifo_depth[7]

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1

T28

4

T30

1

T149

2

fifo_depth[7]

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1788

1

T6

1

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4

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8